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Pull in additional state setup from the DDX
[mesa.git] / src / mesa / drivers / dri / r600 / r700_chip.h
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #ifndef _R700_CHIP_H_
28 #define _R700_CHIP_H_
29
30 #include "r600_context.h"
31
32 #include "r600_reg.h"
33 #include "r600_reg_auto_r6xx.h"
34 #include "r600_reg_r6xx.h"
35 #include "r600_reg_r7xx.h"
36
37 #include "r700_chipoffset.h"
38
39 #define SETfield(x, val, shift, mask) ( (x) = ((x) & ~(mask)) | ((val) << (shift)) ) /* u32All */
40 #define CLEARfield(x, mask) ( (x) &= ~(mask) )
41 #define SETbit(x, bit) ( (x) |= (bit) )
42 #define CLEARbit(x, bit) ( (x) &= ~(bit) )
43
44 #define R700_TEXTURE_NUMBERUNITS 16
45 #define R700_MAX_RENDER_TARGETS 8
46 #define R700_MAX_VIEWPORTS 16
47 #define R700_MAX_SHADER_EXPORTS 32
48 #define R700_MAX_UCP 6
49
50 /* Enum not show in r600_*.h */
51
52 #define FETCH_RESOURCE_STRIDE 7
53
54 #define ASIC_CONFIG_BASE_INDEX 0x2000
55 #define ASIC_CONTEXT_BASE_INDEX 0xA000
56 #define ASIC_CTL_CONST_BASE_INDEX 0xF3FC
57
58 enum
59 {
60 SQ_ABSOLUTE = 0x00000000,
61 SQ_RELATIVE = 0x00000001,
62 };
63
64 enum
65 {
66 SQ_ALU_SCL_210 = 0x00000000,
67 SQ_ALU_SCL_122 = 0x00000001,
68 SQ_ALU_SCL_212 = 0x00000002,
69 SQ_ALU_SCL_221 = 0x00000003,
70 };
71
72 enum
73 {
74 SQ_TEX_UNNORMALIZED = 0x00000000,
75 SQ_TEX_NORMALIZED = 0x00000001,
76 };
77
78 enum
79 {
80 SQ_CF_PIXEL_MRT0 = 0x00000000,
81 SQ_CF_PIXEL_MRT1 = 0x00000001,
82 SQ_CF_PIXEL_MRT2 = 0x00000002,
83 SQ_CF_PIXEL_MRT3 = 0x00000003,
84 SQ_CF_PIXEL_MRT4 = 0x00000004,
85 SQ_CF_PIXEL_MRT5 = 0x00000005,
86 SQ_CF_PIXEL_MRT6 = 0x00000006,
87 SQ_CF_PIXEL_MRT7 = 0x00000007,
88 SQ_CF_PIXEL_Z = 0x0000003d,
89 };
90
91 typedef enum ENUM_SQ_CF_ARRAY_BASE_POS {
92 SQ_CF_POS_0 = 0x0000003c,
93 SQ_CF_POS_1 = 0x0000003d,
94 SQ_CF_POS_2 = 0x0000003e,
95 SQ_CF_POS_3 = 0x0000003f,
96 } ENUM_SQ_CF_ARRAY_BASE_POS;
97
98 enum
99 {
100 PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit = 23,
101 };
102
103 enum
104 {
105 TEX_XYFilter_Point = 0x00000000,
106 TEX_XYFilter_Linear = 0x00000001,
107 TEX_XYFilter_Cubic = 0x00000002,
108 TEX_XYFilter_Cleartype = 0x00000003,
109
110 TEX_MipFilter_None = 0x00000000,
111 TEX_MipFilter_Point = 0x00000001,
112 TEX_MipFilter_Linear = 0x00000002,
113 };
114
115 enum
116 {
117 SQ_EXPORT_WRITE = 0x00000000,
118 SQ_EXPORT_WRITE_IND = 0x00000001,
119 SQ_EXPORT_WRITE_ACK = 0x00000002,
120 SQ_EXPORT_WRITE_IND_ACK = 0x00000003,
121 };
122
123 /* --------------------------------- */
124
125 enum
126 {
127 R700_PM4_PACKET0_NOP = 0x00000000,
128 R700_PM4_PACKET1_NOP = 0x40000000,
129 R700_PM4_PACKET2_NOP = 0x80000000,
130 R700_PM4_PACKET3_NOP = 0xC0000000,
131 };
132
133 #define PM4_OPCODE_SET_INDEX_TYPE (R700_PM4_PACKET3_NOP | (IT_INDEX_TYPE << 8))
134
135 #define PM4_OPCODE_DRAW_INDEX_AUTO (R700_PM4_PACKET3_NOP | (IT_DRAW_INDEX_AUTO << 8))
136 #define PM4_OPCODE_DRAW_INDEX_IMMD (R700_PM4_PACKET3_NOP | (IT_DRAW_INDEX_IMMD << 8))
137 #define PM4_OPCODE_WAIT_REG_MEM (R700_PM4_PACKET3_NOP | (IT_WAIT_REG_MEM << 8))
138 #define PM4_OPCODE_SET_CONTEXT_REG (R700_PM4_PACKET3_NOP | (IT_SET_CONTEXT_REG << 8))
139 #define PM4_OPCODE_SET_CONFIG_REG (R700_PM4_PACKET3_NOP | (IT_SET_CONFIG_REG << 8))
140 #define PM4_OPCODE_SET_ALU_CONST (R700_PM4_PACKET3_NOP | (IT_SET_ALU_CONST << 8))
141 #define PM4_OPCODE_SET_RESOURCE (R700_PM4_PACKET3_NOP | (IT_SET_RESOURCE << 8))
142 #define PM4_OPCODE_SET_SAMPLER (R700_PM4_PACKET3_NOP | (IT_SET_SAMPLER << 8))
143 #define PM4_OPCODE_CONTEXT_CONTROL (R700_PM4_PACKET3_NOP | (IT_CONTEXT_CONTROL << 8))
144
145 union UINT_FLOAT
146 {
147 unsigned int u32All;
148 float f32All;
149 };
150
151 typedef struct _TEXTURE_STATE_STRUCT
152 {
153 union UINT_FLOAT SQ_TEX_RESOURCE0;
154 union UINT_FLOAT SQ_TEX_RESOURCE1;
155 union UINT_FLOAT SQ_TEX_RESOURCE2;
156 union UINT_FLOAT SQ_TEX_RESOURCE3;
157 union UINT_FLOAT SQ_TEX_RESOURCE4;
158 union UINT_FLOAT SQ_TEX_RESOURCE5;
159 union UINT_FLOAT SQ_TEX_RESOURCE6;
160 GLboolean enabled;
161 } TEXTURE_STATE_STRUCT;
162
163 typedef struct _SAMPLER_STATE_STRUCT
164 {
165 union UINT_FLOAT SQ_TEX_SAMPLER0;
166 union UINT_FLOAT SQ_TEX_SAMPLER1;
167 union UINT_FLOAT SQ_TEX_SAMPLER2;
168 GLboolean enabled;
169 } SAMPLER_STATE_STRUCT;
170
171 typedef struct _R700_TEXTURE_STATES
172 {
173 TEXTURE_STATE_STRUCT *textures[R700_TEXTURE_NUMBERUNITS];
174 SAMPLER_STATE_STRUCT *samplers[R700_TEXTURE_NUMBERUNITS];
175 } R700_TEXTURE_STATES;
176
177 typedef struct _RENDER_TARGET_STATE_STRUCT
178 {
179 union UINT_FLOAT CB_COLOR0_BASE; /* 0xA010 */
180 union UINT_FLOAT CB_COLOR0_SIZE; /* 0xA018 */
181 union UINT_FLOAT CB_COLOR0_VIEW; /* 0xA020 */
182 union UINT_FLOAT CB_COLOR0_INFO; /* 0xA028 */
183 union UINT_FLOAT CB_COLOR0_TILE; /* 0xA030 */
184 union UINT_FLOAT CB_COLOR0_FRAG; /* 0xA038 */
185 union UINT_FLOAT CB_COLOR0_MASK; /* 0xA040 */
186 union UINT_FLOAT CB_BLEND0_CONTROL; /* 0xA1E0 */
187 GLboolean enabled;
188 } RENDER_TARGET_STATE_STRUCT;
189
190 typedef struct _VIEWPORT_STATE_STRUCT
191 {
192 union UINT_FLOAT PA_SC_VPORT_SCISSOR_0_TL; /* 0xA094 */
193 union UINT_FLOAT PA_SC_VPORT_SCISSOR_0_BR; /* 0xA095 */
194 union UINT_FLOAT PA_SC_VPORT_ZMIN_0; /* 0xA0B4 */
195 union UINT_FLOAT PA_SC_VPORT_ZMAX_0; /* 0xA0B5 */
196 union UINT_FLOAT PA_CL_VPORT_XSCALE; /* 0xA10F */
197 union UINT_FLOAT PA_CL_VPORT_XOFFSET; /* 0xA110 */
198 union UINT_FLOAT PA_CL_VPORT_YSCALE; /* 0xA111 */
199 union UINT_FLOAT PA_CL_VPORT_YOFFSET; /* 0xA112 */
200 union UINT_FLOAT PA_CL_VPORT_ZSCALE; /* 0xA113 */
201 union UINT_FLOAT PA_CL_VPORT_ZOFFSET; /* 0xA114 */
202 GLboolean enabled;
203 } VIEWPORT_STATE_STRUCT;
204
205 typedef struct _UCP_STATE_STRUCT
206 {
207 union UINT_FLOAT PA_CL_UCP_0_X;
208 union UINT_FLOAT PA_CL_UCP_0_Y;
209 union UINT_FLOAT PA_CL_UCP_0_Z;
210 union UINT_FLOAT PA_CL_UCP_0_W;
211 GLboolean enabled;
212 } UCP_STATE_STRUCT;
213
214 typedef struct _PS_STATE_STRUCT
215 {
216 union UINT_FLOAT SQ_PGM_START_PS ; /* 0xA210 */
217 union UINT_FLOAT SQ_PGM_RESOURCES_PS ; /* 0xA214 */
218 union UINT_FLOAT SQ_PGM_EXPORTS_PS ; /* 0xA215 */
219 union UINT_FLOAT SQ_PGM_CF_OFFSET_PS ; /* 0xA233 */
220 } PS_STATE_STRUCT;
221
222 typedef struct _VS_STATE_STRUCT
223 {
224 union UINT_FLOAT SQ_PGM_START_VS ; /* 0xA216 */
225 union UINT_FLOAT SQ_PGM_RESOURCES_VS ; /* 0xA21A */
226 union UINT_FLOAT SQ_PGM_CF_OFFSET_VS ; /* 0xA234 */
227 } VS_STATE_STRUCT;
228
229 typedef struct _GS_STATE_STRUCT
230 {
231 union UINT_FLOAT SQ_PGM_START_GS ; /* 0xA21B */
232 union UINT_FLOAT SQ_PGM_RESOURCES_GS ; /* 0xA21F */
233 union UINT_FLOAT SQ_PGM_CF_OFFSET_GS ; /* 0xA235 */
234 } GS_STATE_STRUCT;
235
236 typedef struct _ES_STATE_STRUCT
237 {
238 union UINT_FLOAT SQ_PGM_START_ES ; /* 0xA220 */
239 union UINT_FLOAT SQ_PGM_RESOURCES_ES ; /* 0xA224 */
240 union UINT_FLOAT SQ_PGM_CF_OFFSET_ES ; /* 0xA236 */
241 } ES_STATE_STRUCT;
242
243 typedef struct _FS_STATE_STRUCT
244 {
245 union UINT_FLOAT SQ_PGM_START_FS ; /* 0xA225 */
246 union UINT_FLOAT SQ_PGM_RESOURCES_FS ; /* 0xA229 */
247 union UINT_FLOAT SQ_PGM_CF_OFFSET_FS ; /* 0xA237 */
248 } FS_STATE_STRUCT;
249
250 typedef struct _SQ_CONFIG_STRUCT
251 {
252 union UINT_FLOAT SQ_CONFIG ; /* 0x2300 */
253 union UINT_FLOAT SQ_GPR_RESOURCE_MGMT_1 ; /* 0x2301 */
254 union UINT_FLOAT SQ_GPR_RESOURCE_MGMT_2 ; /* 0x2302 */
255 union UINT_FLOAT SQ_THREAD_RESOURCE_MGMT ; /* 0x2303 */
256 union UINT_FLOAT SQ_STACK_RESOURCE_MGMT_1 ; /* 0x2304 */
257 union UINT_FLOAT SQ_STACK_RESOURCE_MGMT_2 ; /* 0x2305 */
258 } SQ_CONFIG_STRUCT;
259
260 typedef struct ContextState
261 {
262 unsigned int * puiValue;
263 unsigned int unOffset;
264 struct ContextState * pNext;
265 } ContextState;
266
267 typedef struct _R700_CHIP_CONTEXT
268 {
269 // misc
270 union UINT_FLOAT TA_CNTL_AUX ; /* 0x2542 */
271 union UINT_FLOAT VC_ENHANCE ; /* 0x25C5 */
272 union UINT_FLOAT SQ_DYN_GPR_CNTL_PS_FLUSH_REQ; /* 0x2363 */
273 union UINT_FLOAT DB_DEBUG ; /* 0x260C */
274 union UINT_FLOAT DB_WATERMARKS ; /* 0x260E */
275
276 // DB
277 union UINT_FLOAT DB_DEPTH_SIZE ; /* 0xA000 */
278 union UINT_FLOAT DB_DEPTH_VIEW ; /* 0xA001 */
279 union UINT_FLOAT DB_DEPTH_BASE ; /* 0xA003 */
280 union UINT_FLOAT DB_DEPTH_INFO ; /* 0xA004 */
281 union UINT_FLOAT DB_HTILE_DATA_BASE ; /* 0xA005 */
282 union UINT_FLOAT DB_STENCIL_CLEAR ; /* 0xA00A */
283 union UINT_FLOAT DB_DEPTH_CLEAR ; /* 0xA00B */
284 union UINT_FLOAT DB_RENDER_CONTROL ; /* 0xA343 */
285 union UINT_FLOAT DB_RENDER_OVERRIDE ; /* 0xA344 */
286 union UINT_FLOAT DB_HTILE_SURFACE ; /* 0xA349 */
287 union UINT_FLOAT DB_ALPHA_TO_MASK ; /* 0xA351 */
288 union UINT_FLOAT DB_DEPTH_CONTROL ; /* 0xA200 */
289 union UINT_FLOAT DB_SHADER_CONTROL ; /* 0xA203 */
290
291 // SC
292 union UINT_FLOAT PA_SC_SCREEN_SCISSOR_TL ; /* 0xA00C */
293 union UINT_FLOAT PA_SC_SCREEN_SCISSOR_BR ; /* 0xA00D */
294 union UINT_FLOAT PA_SC_WINDOW_OFFSET ; /* 0xA080 */
295 union UINT_FLOAT PA_SC_WINDOW_SCISSOR_TL ; /* 0xA081 */
296 union UINT_FLOAT PA_SC_WINDOW_SCISSOR_BR ; /* 0xA082 */
297 union UINT_FLOAT PA_SC_CLIPRECT_RULE ; /* 0xA083 */
298 union UINT_FLOAT PA_SC_CLIPRECT_0_TL ; /* 0xA084 */
299 union UINT_FLOAT PA_SC_CLIPRECT_0_BR ; /* 0xA085 */
300 union UINT_FLOAT PA_SC_CLIPRECT_1_TL ; /* 0xA086 */
301 union UINT_FLOAT PA_SC_CLIPRECT_1_BR ; /* 0xA087 */
302 union UINT_FLOAT PA_SC_CLIPRECT_2_TL ; /* 0xA088 */
303 union UINT_FLOAT PA_SC_CLIPRECT_2_BR ; /* 0xA089 */
304 union UINT_FLOAT PA_SC_CLIPRECT_3_TL ; /* 0xA08A */
305 union UINT_FLOAT PA_SC_CLIPRECT_3_BR ; /* 0xA08B */
306 union UINT_FLOAT PA_SC_EDGERULE ; /* 0xA08C */
307 union UINT_FLOAT PA_SC_GENERIC_SCISSOR_TL ; /* 0xA090 */
308 union UINT_FLOAT PA_SC_GENERIC_SCISSOR_BR ; /* 0xA091 */
309 union UINT_FLOAT PA_SC_LINE_STIPPLE ; /* 0xA283 */
310 union UINT_FLOAT PA_SC_LINE_CNTL ; /* 0xA300 */
311 union UINT_FLOAT PA_SC_AA_CONFIG ; /* 0xA301 */
312 union UINT_FLOAT PA_SC_MPASS_PS_CNTL ; /* 0xA292 */
313 union UINT_FLOAT PA_SC_MODE_CNTL ; /* 0xA293 */
314 union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_MCTX ; /* 0xA307 */
315 union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX; /* 0xA308 */
316 union UINT_FLOAT PA_SC_AA_MASK ; /* 0xA312 */
317
318 // CL
319 union UINT_FLOAT PA_CL_CLIP_CNTL ; /* 0xA204 */
320 union UINT_FLOAT PA_CL_VTE_CNTL ; /* 0xA206 */
321 union UINT_FLOAT PA_CL_VS_OUT_CNTL ; /* 0xA207 */
322 union UINT_FLOAT PA_CL_NANINF_CNTL ; /* 0xA208 */
323 union UINT_FLOAT PA_CL_GB_VERT_CLIP_ADJ ; /* 0xA303 */
324 union UINT_FLOAT PA_CL_GB_VERT_DISC_ADJ ; /* 0xA304 */
325 union UINT_FLOAT PA_CL_GB_HORZ_CLIP_ADJ ; /* 0xA305 */
326 union UINT_FLOAT PA_CL_GB_HORZ_DISC_ADJ ; /* 0xA306 */
327
328 // SU
329 union UINT_FLOAT PA_SU_SC_MODE_CNTL ; /* 0xA205 */
330 union UINT_FLOAT PA_SU_POINT_SIZE ; /* 0xA280 */
331 union UINT_FLOAT PA_SU_POINT_MINMAX ; /* 0xA281 */
332 union UINT_FLOAT PA_SU_LINE_CNTL ; /* 0xA282 */
333 union UINT_FLOAT PA_SU_VTX_CNTL ; /* 0xA302 */
334 union UINT_FLOAT PA_SU_POLY_OFFSET_DB_FMT_CNTL; /* 0xA37E */
335 union UINT_FLOAT PA_SU_POLY_OFFSET_CLAMP ; /* 0xA37F */
336 union UINT_FLOAT PA_SU_POLY_OFFSET_FRONT_SCALE; /* 0xA380 */
337 union UINT_FLOAT PA_SU_POLY_OFFSET_FRONT_OFFSET; /* 0xA381 */
338 union UINT_FLOAT PA_SU_POLY_OFFSET_BACK_SCALE; /* 0xA382 */
339 union UINT_FLOAT PA_SU_POLY_OFFSET_BACK_OFFSET; /* 0xA383 */
340
341 VIEWPORT_STATE_STRUCT viewport[R700_MAX_VIEWPORTS];
342 UCP_STATE_STRUCT ucp[R700_MAX_UCP];
343
344 // CB
345 union UINT_FLOAT CB_CLEAR_RED_R6XX ; /* 0xA048 */
346 union UINT_FLOAT CB_CLEAR_GREEN_R6XX ; /* 0xA049 */
347 union UINT_FLOAT CB_CLEAR_BLUE_R6XX ; /* 0xA04A */
348 union UINT_FLOAT CB_CLEAR_ALPHA_R6XX ; /* 0xA04B */
349 union UINT_FLOAT CB_TARGET_MASK ; /* 0xA08E */
350 union UINT_FLOAT CB_SHADER_MASK ; /* 0xA08F */
351 union UINT_FLOAT CB_BLEND_RED ; /* 0xA105 */
352 union UINT_FLOAT CB_BLEND_GREEN ; /* 0xA106 */
353 union UINT_FLOAT CB_BLEND_BLUE ; /* 0xA107 */
354 union UINT_FLOAT CB_BLEND_ALPHA ; /* 0xA108 */
355 union UINT_FLOAT CB_FOG_RED_R6XX ; /* 0xA109 */
356 union UINT_FLOAT CB_FOG_GREEN_R6XX ; /* 0xA10A */
357 union UINT_FLOAT CB_FOG_BLUE_R6XX ; /* 0xA10B */
358 union UINT_FLOAT CB_SHADER_CONTROL ; /* 0xA1E8 */
359 union UINT_FLOAT CB_COLOR_CONTROL ; /* 0xA202 */
360 union UINT_FLOAT CB_CLRCMP_CONTROL ; /* 0xA30C */
361 union UINT_FLOAT CB_CLRCMP_SRC ; /* 0xA30D */
362 union UINT_FLOAT CB_CLRCMP_DST ; /* 0xA30E */
363 union UINT_FLOAT CB_CLRCMP_MSK ; /* 0xA30F */
364 union UINT_FLOAT CB_BLEND_CONTROL ; /* 0xABD0 */
365 RENDER_TARGET_STATE_STRUCT render_target[R700_MAX_RENDER_TARGETS];
366
367 // SX
368 union UINT_FLOAT SX_MISC ; /* 0xA0D4 */
369 union UINT_FLOAT SX_ALPHA_TEST_CONTROL ; /* 0xA104 */
370
371 // VGT
372 union UINT_FLOAT VGT_MAX_VTX_INDX ; /* 0xA100 */
373 union UINT_FLOAT VGT_MIN_VTX_INDX ; /* 0xA101 */
374 union UINT_FLOAT VGT_INDX_OFFSET ; /* 0xA102 */
375 union UINT_FLOAT VGT_MULTI_PRIM_IB_RESET_INDX; /* 0xA103 */
376 union UINT_FLOAT VGT_OUTPUT_PATH_CNTL ; /* 0xA284 */
377 union UINT_FLOAT VGT_HOS_CNTL ; /* 0xA285 */
378 union UINT_FLOAT VGT_HOS_MAX_TESS_LEVEL ; /* 0xA286 */
379 union UINT_FLOAT VGT_HOS_MIN_TESS_LEVEL ; /* 0xA287 */
380 union UINT_FLOAT VGT_HOS_REUSE_DEPTH ; /* 0xA288 */
381 union UINT_FLOAT VGT_GROUP_PRIM_TYPE ; /* 0xA289 */
382 union UINT_FLOAT VGT_GROUP_FIRST_DECR ; /* 0xA28A */
383 union UINT_FLOAT VGT_GROUP_DECR ; /* 0xA28B */
384 union UINT_FLOAT VGT_GROUP_VECT_0_CNTL ; /* 0xA28C */
385 union UINT_FLOAT VGT_GROUP_VECT_1_CNTL ; /* 0xA28D */
386 union UINT_FLOAT VGT_GROUP_VECT_0_FMT_CNTL ; /* 0xA28E */
387 union UINT_FLOAT VGT_GROUP_VECT_1_FMT_CNTL ; /* 0xA28F */
388 union UINT_FLOAT VGT_GS_MODE ; /* 0xA290 */
389 union UINT_FLOAT VGT_PRIMITIVEID_EN ; /* 0xA2A1 */
390 union UINT_FLOAT VGT_DMA_NUM_INSTANCES ; /* 0xA2A2 */
391 union UINT_FLOAT VGT_MULTI_PRIM_IB_RESET_EN; /* 0xA2A5 */
392 union UINT_FLOAT VGT_INSTANCE_STEP_RATE_0 ; /* 0xA2A8 */
393 union UINT_FLOAT VGT_INSTANCE_STEP_RATE_1 ; /* 0xA2A9 */
394 union UINT_FLOAT VGT_STRMOUT_EN ; /* 0xA2AC */
395 union UINT_FLOAT VGT_REUSE_OFF ; /* 0xA2AD */
396 union UINT_FLOAT VGT_VTX_CNT_EN ; /* 0xA2AE */
397 union UINT_FLOAT VGT_STRMOUT_BUFFER_EN ; /* 0xA2C8 */
398
399 // SPI
400 union UINT_FLOAT SPI_VS_OUT_ID_0 ; /* 0xA185 */
401 union UINT_FLOAT SPI_VS_OUT_ID_1 ; /* 0xA186 */
402 union UINT_FLOAT SPI_VS_OUT_ID_2 ; /* 0xA187 */
403 union UINT_FLOAT SPI_VS_OUT_ID_3 ; /* 0xA188 */
404 union UINT_FLOAT SPI_VS_OUT_ID_4 ; /* 0xA189 */
405 union UINT_FLOAT SPI_VS_OUT_ID_5 ; /* 0xA18A */
406 union UINT_FLOAT SPI_VS_OUT_ID_6 ; /* 0xA18B */
407 union UINT_FLOAT SPI_VS_OUT_ID_7 ; /* 0xA18C */
408 union UINT_FLOAT SPI_VS_OUT_ID_8 ; /* 0xA18D */
409 union UINT_FLOAT SPI_VS_OUT_ID_9 ; /* 0xA18E */
410 union UINT_FLOAT SPI_VS_OUT_CONFIG ; /* 0xA1B1 */
411 union UINT_FLOAT SPI_THREAD_GROUPING ; /* 0xA1B2 */
412 union UINT_FLOAT SPI_PS_IN_CONTROL_0 ; /* 0xA1B3 */
413 union UINT_FLOAT SPI_PS_IN_CONTROL_1 ; /* 0xA1B4 */
414 union UINT_FLOAT SPI_INTERP_CONTROL_0 ; /* 0xA1B5 */
415 union UINT_FLOAT SPI_INPUT_Z ; /* 0xA1B6 */
416 union UINT_FLOAT SPI_FOG_CNTL ; /* 0xA1B7 */
417 union UINT_FLOAT SPI_FOG_FUNC_SCALE ; /* 0xA1B8 */
418 union UINT_FLOAT SPI_FOG_FUNC_BIAS ; /* 0xA1B9 */
419 union UINT_FLOAT SQ_VTX_SEMANTIC[R700_MAX_SHADER_EXPORTS];
420 union UINT_FLOAT SPI_PS_INPUT_CNTL[R700_MAX_SHADER_EXPORTS];
421
422 // shaders
423 PS_STATE_STRUCT ps;
424 VS_STATE_STRUCT vs;
425 GS_STATE_STRUCT gs;
426 ES_STATE_STRUCT es;
427 PS_STATE_STRUCT fs;
428
429 // SQ CONFIG
430 SQ_CONFIG_STRUCT sq_config;
431
432 // SQ
433 union UINT_FLOAT SQ_ESGS_RING_ITEMSIZE ; /* 0xA22A */
434 union UINT_FLOAT SQ_GSVS_RING_ITEMSIZE ; /* 0xA22B */
435 union UINT_FLOAT SQ_ESTMP_RING_ITEMSIZE ; /* 0xA22C */
436 union UINT_FLOAT SQ_GSTMP_RING_ITEMSIZE ; /* 0xA22D */
437 union UINT_FLOAT SQ_VSTMP_RING_ITEMSIZE ; /* 0xA22E */
438 union UINT_FLOAT SQ_PSTMP_RING_ITEMSIZE ; /* 0xA22F */
439 union UINT_FLOAT SQ_FBUF_RING_ITEMSIZE ; /* 0xA230 */
440 union UINT_FLOAT SQ_REDUC_RING_ITEMSIZE ; /* 0xA231 */
441 union UINT_FLOAT SQ_GS_VERT_ITEMSIZE ; /* 0xA232 */
442
443 ContextState* pStateList;
444
445 R700_TEXTURE_STATES texture_states;
446
447 GLboolean bEnablePerspective;
448
449 } R700_CHIP_CONTEXT;
450
451 #endif /* _R700_CHIP_H_ */
452