src/mesa/drivers/dri/r600/r700_clear.c

   1 /*
   2  * Copyright (C) 2008-2009  Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  */
  21
  22 /*
  23  * Authors:
  24  *   Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
  25  *   CooperYuan <cooper.yuan@amd.com>, <cooperyuan@gmail.com>
  26  */
  27
  28 #include "main/glheader.h"
  29 #include "main/context.h"
  30 #include "main/macros.h"
  31 #include "main/imports.h"
  32 #include "main/mtypes.h"
  33 #include "main/enums.h"
  34
  35 #include "r600_context.h"
  36 #include "r700_chip.h"
  37
  38 #if 0 /* to be enabled */
  39 #include "r700_shaderinst.h"
  40 #include "r700_emit.h"
  41 #endif /* to be enabled */
  42
  43 extern void r700InitState (GLcontext * ctx);
  44
  45 #if 0 /* to be enabled */
  46 extern void r700SetupVTXConstans(GLcontext  * ctx,
  47                           unsigned int nStreamID,
  48                           unsigned int aos_offset,
  49                           unsigned int size,      /* number of elements in vector */
  50                           unsigned int stride,
  51                           unsigned int count);
  52 extern GLboolean r700SendContextStates(context_t *context);
  53 extern GLboolean r700SyncSurf(context_t *context);
  54 #endif /* to be enabled */
  55
  56 static GLboolean r700ClearFast(context_t *context, GLbitfield mask)
  57 {
  58     /* TODO, fast clear need implementation */
  59     return GL_FALSE;
  60 }
  61
  62 static GLboolean r700ClearWithDraw(context_t *context, GLbitfield mask)
  63 {
  64     GLcontext *ctx = GL_CONTEXT(context);
  65
  66 #if 0 /* to be enabled */
  67     R700_CHIP_CONTEXT  r700Saved;
  68     R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj);
  69     struct r600_dma_region  aos_vs;
  70     struct r600_dma_region  aos_fs;
  71     struct r600_dma_region  aos_vb;
  72     aos_vs.buf = NULL;
  73     aos_fs.buf = NULL;
  74     aos_vb.buf = NULL;
  75
  76
  77     unsigned int ui;
  78     GLfloat  fTemp;
  79     GLfloat  fVb[] = { 1.0f,  1.0f, 1.0f, 1.0f,
  80                       -1.0f, -1.0f, 1.0f, 1.0f,
  81                        1.0f, -1.0f, 1.0f, 1.0f,
  82                        1.0f,  1.0f, 1.0f, 1.0f,
  83                       -1.0f,  1.0f, 1.0f, 1.0f,
  84                       -1.0f, -1.0f, 1.0f, 1.0f}; /* TODO : Z set here */
  85     unsigned int uVs[] = { 0xC,        0x81000000, 0x4,        0xA01C0000,
  86                            0xC001203C, 0x94000688, 0xC001C000, 0x94200688,
  87                            0x10000001, 0x540C90,   0x10000401, 0x20540C90,
  88                            0x10000801, 0x40540C90, 0x90000C01, 0x60400C90,
  89                            0x10000100, 0x600C90,   0x10000500, 0x20600C90,
  90                            0x10000900, 0x40600C90, 0x90000D00, 0x60680C90,
  91                            0x7C000000, 0x2D1001,   0x80000,    0xBEADEAF };
  92     unsigned int uFs[] = { 0x2,        0xA00C0000, 0xC0008000, 0x94200688,
  93                            0x10000000, 0x340C90,   0x10000400, 0x20340C90,
  94                            0x10000800, 0x40340C90, 0x90000C00, 0x60200C90};
  95
  96     if (context->screen->chip.type <= CHIP_TYPE_RV670)
  97     {
  98         uVs[9]  = 0x541910;
  99         uVs[11] = 0x20541910;
 100         uVs[13] = 0x40541910;
 101         uVs[15] = 0x60401910;
 102         uVs[17] = 0x601910;
 103         uVs[19] = 0x20601910;
 104         uVs[21] = 0x40601910;
 105         uVs[23] = 0x60681910;
 106         uFs[5]  = 0x341910;
 107         uFs[7]  = 0x20341910;
 108         uFs[9]  = 0x40341910;
 109         uFs[11] = 0x60201910;
 110     }
 111
 112     r700SyncSurf(context);
 113
 114     /* Save current chip object. */
 115     memcpy(&r700Saved, r700, sizeof(R700_CHIP_CONTEXT));
 116
 117     r700InitState(ctx);
 118
 119     r700->CB_COLOR0_BASE.u32All = context->target.rt.gpu >> 8;
 120
 121     /* Turn off perspective divid. */
 122     SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
 123     SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
 124     SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
 125
 126     if( (mask & BUFFER_BIT_FRONT_LEFT) || (mask & BUFFER_BIT_BACK_LEFT) )
 127     {   /* Enable render target output. */
 128         SETfield(r700->CB_TARGET_MASK.u32All, 0xF, TARGET0_ENABLE_shift, TARGET0_ENABLE_mask);
 129     }
 130     else
 131     {   /* Disable render target output. */
 132         CLEARfield(r700->CB_TARGET_MASK.u32All, TARGET0_ENABLE_mask); /* TODO : OGL need 4 rt. */
 133     }
 134     if (mask & BUFFER_BIT_DEPTH)
 135     {
 136         /* Set correct Z to clear. */
 137         SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
 138         SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
 139         SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS, ZFUNC_shift, ZFUNC_mask);
 140         fTemp = ctx->Depth.Clear;
 141         for(ui=2; ui<24;)
 142         {
 143             fVb[ui] = fTemp;
 144             ui += 4;
 145         }
 146     }
 147     else
 148     {
 149         /* Disable Z write. */
 150         CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
 151         CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
 152     }
 153
 154     /* Setup vb */
 155     R700_CMDBUF_CHECK_SPACE(6);
 156     R700EP3 (context, IT_SET_CTL_CONST, 1);
 157     R700E32 (context, mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
 158     R700E32 (context, 0);
 159     R700EP3 (context, IT_SET_CTL_CONST, 1);
 160     R700E32 (context, mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX);
 161     R700E32 (context, 0);
 162     (context->chipobj.EmitVec)(ctx, &aos_vb, (GLvoid *)fVb, 4, 16, 6);
 163     r700SetupVTXConstans(ctx, VERT_ATTRIB_POS, (unsigned int)aos_vb.aos_offset, 4, 16, 6);
 164
 165     /* Setup shaders, copied from dump */
 166     r700->SQ_PGM_RESOURCES_PS.u32All = 0;
 167         r700->SQ_PGM_RESOURCES_VS.u32All = 0;
 168         SETbit(r700->SQ_PGM_RESOURCES_PS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit);
 169     SETbit(r700->SQ_PGM_RESOURCES_VS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit);
 170         /* vs */
 171     (context->chipobj.EmitShader)(ctx, &aos_vs, (GLvoid *)(&uVs[0]), 28);
 172     r700->SQ_PGM_START_VS.u32All     = (aos_vs.aos_offset >> 8) & 0x00FFFFFF;
 173     r700->SQ_PGM_RESOURCES_VS.u32All = 0x00800004;
 174             /* vs const */ /* TODO : Set color here */
 175     R700_CMDBUF_CHECK_SPACE(4 + 2);
 176     R700EP3 (context, IT_SET_ALU_CONST, 4);
 177     R700E32 (context, SQ_ALU_CONSTANT_VS_OFFSET * 4);
 178     R700E32 (context, *((unsigned int*)&(ctx->Color.ClearColor[0])));
 179     R700E32 (context, *((unsigned int*)&(ctx->Color.ClearColor[1])));
 180     R700E32 (context, *((unsigned int*)&(ctx->Color.ClearColor[2])));
 181     R700E32 (context, *((unsigned int*)&(ctx->Color.ClearColor[3])));
 182
 183     r700->SPI_VS_OUT_CONFIG.u32All   = 0x00000000;
 184         r700->SPI_PS_IN_CONTROL_0.u32All = 0x20000001;
 185         /* ps */
 186     (context->chipobj.EmitShader)(ctx, &aos_fs, (GLvoid *)(&uFs[0]), 12);
 187     r700->SQ_PGM_START_PS.u32All     = (aos_fs.aos_offset >> 8) & 0x00FFFFFF;
 188     r700->SQ_PGM_RESOURCES_PS.u32All = 0x00800002;
 189     r700->SQ_PGM_EXPORTS_PS.u32All   = 0x00000002;
 190     r700->DB_SHADER_CONTROL.u32All   = 0x00000200;
 191
 192     r700->CB_SHADER_CONTROL.u32All = 0x00000001;
 193
 194     /* set a valid base address to make the command checker happy */
 195     r700->SQ_PGM_START_FS.u32All     = (aos_fs.aos_offset >> 8) & 0x00FFFFFF;
 196     r700->SQ_PGM_START_ES.u32All     = (aos_fs.aos_offset >> 8) & 0x00FFFFFF;
 197     r700->SQ_PGM_START_GS.u32All     = (aos_fs.aos_offset >> 8) & 0x00FFFFFF;
 198
 199     /* Now, send the states */
 200     r700SendContextStates(context);
 201
 202     /* Draw */
 203     GLuint numEntires, j;
 204     GLuint numIndices = 6;
 205     unsigned int VGT_DRAW_INITIATOR = 0;
 206     unsigned int VGT_INDEX_TYPE     = 0;
 207     unsigned int VGT_PRIMITIVE_TYPE = 0;
 208     unsigned int VGT_NUM_INDICES    = 0;
 209
 210     numEntires = 2                 /* VGT_INDEX_TYPE */
 211                  + 3               /* VGT_PRIMITIVE_TYPE */
 212                  + numIndices + 3; /* DRAW_INDEX_IMMD */
 213
 214     R700_CMDBUF_CHECK_SPACE(numEntires);
 215
 216     SETfield(VGT_INDEX_TYPE, DI_INDEX_SIZE_32_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask);
 217
 218     R700EP3(context, IT_INDEX_TYPE, 0);
 219     R700E32(context, VGT_INDEX_TYPE);
 220
 221     VGT_NUM_INDICES = numIndices;
 222
 223     SETfield(VGT_PRIMITIVE_TYPE, DI_PT_TRILIST, VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask);
 224     R700EP3(context, IT_SET_CONFIG_REG, 1);
 225     R700E32(context, mmVGT_PRIMITIVE_TYPE - ASIC_CONFIG_BASE_INDEX);
 226     R700E32(context, VGT_PRIMITIVE_TYPE);
 227
 228     SETfield(VGT_DRAW_INITIATOR, DI_SRC_SEL_IMMEDIATE, SOURCE_SELECT_shift, SOURCE_SELECT_mask);
 229     SETfield(VGT_DRAW_INITIATOR, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask);
 230
 231     R700EP3(context, IT_DRAW_INDEX_IMMD, (numIndices + 1));
 232     R700E32(context, VGT_NUM_INDICES);
 233     R700E32(context, VGT_DRAW_INITIATOR);
 234
 235     for (j=0; j<numIndices; j++)
 236     {
 237         R700E32(context, j);
 238     }
 239
 240     (context->chipobj.FlushCmdBuffer)(context);
 241
 242     /* TODO : keep these in context, don't load and release every time. */
 243     (context->chipobj.FreeDmaRegion)(context, &aos_vs);
 244     (context->chipobj.FreeDmaRegion)(context, &aos_fs);
 245     (context->chipobj.FreeDmaRegion)(context, &aos_vb);
 246
 247     /* Restore chip object. */
 248     memcpy(r700, &r700Saved, sizeof(R700_CHIP_CONTEXT));
 249
 250 #endif /* to be enabled */
 251
 252     return GL_TRUE;
 253 }
 254
 255 void r700Clear(GLcontext * ctx, GLbitfield mask)
 256 {
 257     context_t *context = R700_CONTEXT(ctx);
 258
 259     if( GL_TRUE == r700ClearFast(context, mask) )
 260     {
 261         return;
 262     }
 263
 264     r700ClearWithDraw(context, mask);
 265 }
 266
 267