src/mesa/drivers/dri/r600/r700_fragprog.c

   1 /*
   2  * Copyright (C) 2008-2009  Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  */
  21
  22 /*
  23  * Authors:
  24  *   Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
  25  *   CooperYuan <cooper.yuan@amd.com>, <cooperyuan@gmail.com>
  26  */
  27
  28 #include <stdio.h>
  29 #include <stdarg.h>
  30 #include <stdlib.h>
  31 #include <string.h>
  32 #include <math.h>
  33
  34 #include "main/imports.h"
  35 #include "shader/prog_parameter.h"
  36 #include "shader/prog_statevars.h"
  37
  38 #include "r600_context.h"
  39 #include "r600_cmdbuf.h"
  40
  41 #include "r700_fragprog.h"
  42
  43 #include "r700_debug.h"
  44
  45 //TODO : Validate FP input with VP output.
  46 void Map_Fragment_Program(r700_AssemblerBase         *pAsm,
  47                                                   struct gl_fragment_program *mesa_fp)
  48 {
  49         unsigned int unBit;
  50     unsigned int i;
  51     GLuint       ui;
  52
  53         pAsm->number_used_registers = 0;
  54
  55 //Input mapping : mesa_fp->Base.InputsRead set the flag, set in
  56         //The flags parsed in parse_attrib_binding. FRAG_ATTRIB_COLx, FRAG_ATTRIB_TEXx, ...
  57         //MUST match order in Map_Vertex_Output
  58         unBit = 1 << FRAG_ATTRIB_WPOS;
  59         if(mesa_fp->Base.InputsRead & unBit)
  60         {
  61                 pAsm->uiFP_AttributeMap[FRAG_ATTRIB_WPOS] = pAsm->number_used_registers++;
  62         }
  63
  64         unBit = 1 << FRAG_ATTRIB_COL0;
  65         if(mesa_fp->Base.InputsRead & unBit)
  66         {
  67                 pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL0] = pAsm->number_used_registers++;
  68         }
  69
  70         unBit = 1 << FRAG_ATTRIB_COL1;
  71         if(mesa_fp->Base.InputsRead & unBit)
  72         {
  73                 pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL1] = pAsm->number_used_registers++;
  74         }
  75
  76         unBit = 1 << FRAG_ATTRIB_FOGC;
  77         if(mesa_fp->Base.InputsRead & unBit)
  78         {
  79                 pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FOGC] = pAsm->number_used_registers++;
  80         }
  81
  82         for(i=0; i<8; i++)
  83         {
  84                 unBit = 1 << (FRAG_ATTRIB_TEX0 + i);
  85                 if(mesa_fp->Base.InputsRead & unBit)
  86                 {
  87                         pAsm->uiFP_AttributeMap[FRAG_ATTRIB_TEX0 + i] = pAsm->number_used_registers++;
  88                 }
  89         }
  90
  91 /* Map temporary registers (GPRs) */
  92     pAsm->starting_temp_register_number = pAsm->number_used_registers;
  93
  94     if(mesa_fp->Base.NumNativeTemporaries >= mesa_fp->Base.NumTemporaries)
  95     {
  96             pAsm->number_used_registers += mesa_fp->Base.NumNativeTemporaries;
  97     }
  98     else
  99     {
 100         pAsm->number_used_registers += mesa_fp->Base.NumTemporaries;
 101     }
 102
 103 /* Output mapping */
 104         pAsm->number_of_exports = 0;
 105         pAsm->number_of_colorandz_exports = 0; /* don't include stencil and mask out. */
 106         pAsm->starting_export_register_number = pAsm->number_used_registers;
 107         unBit = 1 << FRAG_RESULT_COLOR;
 108         if(mesa_fp->Base.OutputsWritten & unBit)
 109         {
 110                 pAsm->uiFP_OutputMap[FRAG_RESULT_COLOR] = pAsm->number_used_registers++;
 111                 pAsm->number_of_exports++;
 112                 pAsm->number_of_colorandz_exports++;
 113         }
 114         unBit = 1 << FRAG_RESULT_DEPTH;
 115         if(mesa_fp->Base.OutputsWritten & unBit)
 116         {
 117         pAsm->depth_export_register_number = pAsm->number_used_registers;
 118                 pAsm->uiFP_OutputMap[FRAG_RESULT_DEPTH] = pAsm->number_used_registers++;
 119                 pAsm->number_of_exports++;
 120                 pAsm->number_of_colorandz_exports++;
 121                 pAsm->pR700Shader->depthIsExported = 1;
 122         }
 123
 124     pAsm->pucOutMask = (unsigned char*) MALLOC(pAsm->number_of_exports);
 125     for(ui=0; ui<pAsm->number_of_exports; ui++)
 126     {
 127         pAsm->pucOutMask[ui] = 0x0;
 128     }
 129
 130         pAsm->uFirstHelpReg = pAsm->number_used_registers;
 131 }
 132
 133 GLboolean Find_Instruction_Dependencies_fp(struct r700_fragment_program *fp,
 134                                                                 struct gl_fragment_program   *mesa_fp)
 135 {
 136     GLuint i, j;
 137     GLint * puiTEMPwrites;
 138     struct prog_instruction * pILInst;
 139     InstDeps         *pInstDeps;
 140     struct prog_instruction * texcoord_DepInst;
 141     GLint              nDepInstID;
 142
 143     puiTEMPwrites = (GLint*) MALLOC(sizeof(GLuint)*mesa_fp->Base.NumTemporaries);
 144     for(i=0; i<mesa_fp->Base.NumTemporaries; i++)
 145     {
 146         puiTEMPwrites[i] = -1;
 147     }
 148
 149     pInstDeps = (InstDeps*)MALLOC(sizeof(InstDeps)*mesa_fp->Base.NumInstructions);
 150
 151     for(i=0; i<mesa_fp->Base.NumInstructions; i++)
 152     {
 153         pInstDeps[i].nDstDep = -1;
 154         pILInst = &(mesa_fp->Base.Instructions[i]);
 155
 156         //Dst
 157         if(pILInst->DstReg.File == PROGRAM_TEMPORARY)
 158         {
 159             //Set lastwrite for the temp
 160             puiTEMPwrites[pILInst->DstReg.Index] = i;
 161         }
 162
 163         //Src
 164         for(j=0; j<3; j++)
 165         {
 166             if(pILInst->SrcReg[j].File == PROGRAM_TEMPORARY)
 167             {
 168                 //Set dep.
 169                 pInstDeps[i].nSrcDeps[j] = puiTEMPwrites[pILInst->SrcReg[j].Index];
 170             }
 171             else
 172             {
 173                 pInstDeps[i].nSrcDeps[j] = -1;
 174             }
 175         }
 176     }
 177
 178     fp->r700AsmCode.pInstDeps = pInstDeps;
 179
 180     FREE(puiTEMPwrites);
 181
 182     //Find dep for tex inst
 183     for(i=0; i<mesa_fp->Base.NumInstructions; i++)
 184     {
 185         pILInst = &(mesa_fp->Base.Instructions[i]);
 186
 187         if(GL_TRUE == IsTex(pILInst->Opcode))
 188         {   //src0 is the tex coord register, src1 is texunit, src2 is textype
 189             nDepInstID = pInstDeps[i].nSrcDeps[0];
 190             if(nDepInstID >= 0)
 191             {
 192                 texcoord_DepInst = &(mesa_fp->Base.Instructions[nDepInstID]);
 193                 if(GL_TRUE == IsAlu(texcoord_DepInst->Opcode) )
 194                 {
 195                     pInstDeps[nDepInstID].nDstDep = i;
 196                     pInstDeps[i].nDstDep = i;
 197                 }
 198                 else if(GL_TRUE == IsTex(texcoord_DepInst->Opcode) )
 199                 {
 200                     pInstDeps[i].nDstDep = i;
 201                 }
 202                 else
 203                 {   //... other deps?
 204                 }
 205             }
 206         }
 207         }
 208
 209     return GL_TRUE;
 210 }
 211
 212 GLboolean r700TranslateFragmentShader(struct r700_fragment_program *fp,
 213                                                              struct gl_fragment_program   *mesa_fp)
 214 {
 215         GLuint    number_of_colors_exported;
 216         GLboolean z_enabled = GL_FALSE;
 217         GLuint    unBit;
 218
 219     //Init_Program
 220         Init_r700_AssemblerBase( SPT_FP, &(fp->r700AsmCode), &(fp->r700Shader) );
 221         Map_Fragment_Program(&(fp->r700AsmCode), mesa_fp);
 222
 223     if( GL_FALSE == Find_Instruction_Dependencies_fp(fp, mesa_fp) )
 224         {
 225                 return GL_FALSE;
 226     }
 227
 228         if( GL_FALSE == AssembleInstr(mesa_fp->Base.NumInstructions,
 229                                   &(mesa_fp->Base.Instructions[0]),
 230                                   &(fp->r700AsmCode)) )
 231         {
 232                 return GL_FALSE;
 233         }
 234
 235     if(GL_FALSE == Process_Fragment_Exports(&(fp->r700AsmCode), mesa_fp->Base.OutputsWritten) )
 236     {
 237         return GL_FALSE;
 238     }
 239
 240     fp->r700Shader.nRegs = (fp->r700AsmCode.number_used_registers == 0) ? 0
 241                          : (fp->r700AsmCode.number_used_registers - 1);
 242
 243         fp->r700Shader.nParamExports = fp->r700AsmCode.number_of_exports;
 244
 245         number_of_colors_exported = fp->r700AsmCode.number_of_colorandz_exports;
 246
 247         unBit = 1 << FRAG_RESULT_DEPTH;
 248         if(mesa_fp->Base.OutputsWritten & unBit)
 249         {
 250                 z_enabled = GL_TRUE;
 251                 number_of_colors_exported--;
 252         }
 253
 254         fp->r700Shader.exportMode = number_of_colors_exported << 1 | z_enabled;
 255
 256     fp->translated = GL_TRUE;
 257
 258         return GL_TRUE;
 259 }
 260
 261 void * r700GetActiveFpShaderBo(GLcontext * ctx)
 262 {
 263     struct r700_fragment_program *fp = (struct r700_fragment_program *)
 264                                            (ctx->FragmentProgram._Current);
 265
 266     return fp->shaderbo;
 267 }
 268
 269 GLboolean r700SetupFragmentProgram(GLcontext * ctx)
 270 {
 271     context_t *context = R700_CONTEXT(ctx);
 272     R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
 273     struct r700_fragment_program *fp = (struct r700_fragment_program *)
 274                                            (ctx->FragmentProgram._Current);
 275     r700_AssemblerBase         *pAsm = &(fp->r700AsmCode);
 276     struct gl_fragment_program *mesa_fp = &(fp->mesa_program);
 277     struct gl_program_parameter_list *paramList;
 278     unsigned int unNumParamData;
 279     unsigned int ui, i;
 280     unsigned int unNumOfReg;
 281     unsigned int unBit;
 282     GLuint exportCount;
 283
 284     if(GL_FALSE == fp->loaded)
 285     {
 286         if(fp->r700Shader.bNeedsAssembly == GL_TRUE)
 287             {
 288                     Assemble( &(fp->r700Shader) );
 289             }
 290
 291         /* Load fp to gpu */
 292         r600EmitShader(ctx,
 293                        &(fp->shaderbo),
 294                        (GLvoid *)(fp->r700Shader.pProgram),
 295                        fp->r700Shader.uShaderBinaryDWORDSize,
 296                        "FS");
 297
 298         fp->loaded = GL_TRUE;
 299     }
 300
 301     DumpHwBinary(DUMP_PIXEL_SHADER, (GLvoid *)(fp->r700Shader.pProgram),
 302                  fp->r700Shader.uShaderBinaryDWORDSize);
 303
 304     /* TODO : enable this after MemUse fixed *=
 305     (context->chipobj.MemUse)(context, fp->shadercode.buf->id);
 306     */
 307
 308     R600_STATECHANGE(context, ps);
 309
 310     r700->ps.SQ_PGM_RESOURCES_PS.u32All = 0;
 311     SETbit(r700->ps.SQ_PGM_RESOURCES_PS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit);
 312
 313     r700->ps.SQ_PGM_START_PS.u32All = 0; /* set from buffer obj */
 314
 315     R600_STATECHANGE(context, spi);
 316
 317     unNumOfReg = fp->r700Shader.nRegs + 1;
 318
 319     ui = (r700->SPI_PS_IN_CONTROL_0.u32All & NUM_INTERP_mask) / (1 << NUM_INTERP_shift);
 320
 321     /* PS uses fragment.position */
 322     if (mesa_fp->Base.InputsRead & (1 << FRAG_ATTRIB_WPOS))
 323     {
 324         ui += 1;
 325         SETfield(r700->SPI_PS_IN_CONTROL_0.u32All, ui, NUM_INTERP_shift, NUM_INTERP_mask);
 326         SETfield(r700->SPI_PS_IN_CONTROL_0.u32All, CENTERS_ONLY, BARYC_SAMPLE_CNTL_shift, BARYC_SAMPLE_CNTL_mask);
 327         SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, POSITION_ENA_bit);
 328         SETbit(r700->SPI_INPUT_Z.u32All, PROVIDE_Z_TO_SPI_bit);
 329     }
 330
 331     ui = (unNumOfReg < ui) ? ui : unNumOfReg;
 332
 333     SETfield(r700->ps.SQ_PGM_RESOURCES_PS.u32All, ui, NUM_GPRS_shift, NUM_GPRS_mask);
 334
 335     CLEARbit(r700->ps.SQ_PGM_RESOURCES_PS.u32All, UNCACHED_FIRST_INST_bit);
 336
 337     if(fp->r700Shader.uStackSize) /* we don't use branch for now, it should be zero. */
 338         {
 339         SETfield(r700->ps.SQ_PGM_RESOURCES_PS.u32All, fp->r700Shader.uStackSize,
 340                  STACK_SIZE_shift, STACK_SIZE_mask);
 341     }
 342
 343     SETfield(r700->ps.SQ_PGM_EXPORTS_PS.u32All, fp->r700Shader.exportMode,
 344              EXPORT_MODE_shift, EXPORT_MODE_mask);
 345
 346     R600_STATECHANGE(context, db);
 347
 348     if(fp->r700Shader.killIsUsed)
 349     {
 350             SETbit(r700->DB_SHADER_CONTROL.u32All, KILL_ENABLE_bit);
 351     }
 352     else
 353     {
 354         CLEARbit(r700->DB_SHADER_CONTROL.u32All, KILL_ENABLE_bit);
 355     }
 356
 357     if(fp->r700Shader.depthIsExported)
 358     {
 359             SETbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit);
 360     }
 361     else
 362     {
 363         CLEARbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit);
 364     }
 365
 366     // emit ps input map
 367     unBit = 1 << FRAG_ATTRIB_WPOS;
 368     if(mesa_fp->Base.InputsRead & unBit)
 369     {
 370             ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_WPOS];
 371             SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
 372             SETfield(r700->SPI_PS_INPUT_CNTL[ui].u32All, ui,
 373                      SEMANTIC_shift, SEMANTIC_mask);
 374             if (r700->SPI_INTERP_CONTROL_0.u32All & FLAT_SHADE_ENA_bit)
 375                     SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
 376             else
 377                     CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
 378     }
 379
 380     unBit = 1 << FRAG_ATTRIB_COL0;
 381     if(mesa_fp->Base.InputsRead & unBit)
 382     {
 383             ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL0];
 384             SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
 385             SETfield(r700->SPI_PS_INPUT_CNTL[ui].u32All, ui,
 386                      SEMANTIC_shift, SEMANTIC_mask);
 387             if (r700->SPI_INTERP_CONTROL_0.u32All & FLAT_SHADE_ENA_bit)
 388                     SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
 389             else
 390                     CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
 391     }
 392
 393     unBit = 1 << FRAG_ATTRIB_COL1;
 394     if(mesa_fp->Base.InputsRead & unBit)
 395     {
 396             ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL1];
 397             SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
 398             SETfield(r700->SPI_PS_INPUT_CNTL[ui].u32All, ui,
 399                      SEMANTIC_shift, SEMANTIC_mask);
 400             if (r700->SPI_INTERP_CONTROL_0.u32All & FLAT_SHADE_ENA_bit)
 401                     SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
 402             else
 403                     CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
 404     }
 405
 406     unBit = 1 << FRAG_ATTRIB_FOGC;
 407     if(mesa_fp->Base.InputsRead & unBit)
 408     {
 409             ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FOGC];
 410             SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
 411             SETfield(r700->SPI_PS_INPUT_CNTL[ui].u32All, ui,
 412                      SEMANTIC_shift, SEMANTIC_mask);
 413             if (r700->SPI_INTERP_CONTROL_0.u32All & FLAT_SHADE_ENA_bit)
 414                     SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
 415             else
 416                     CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
 417     }
 418
 419     for(i=0; i<8; i++)
 420     {
 421             unBit = 1 << (FRAG_ATTRIB_TEX0 + i);
 422             if(mesa_fp->Base.InputsRead & unBit)
 423             {
 424                     ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_TEX0 + i];
 425                     SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
 426                     SETfield(r700->SPI_PS_INPUT_CNTL[ui].u32All, ui,
 427                              SEMANTIC_shift, SEMANTIC_mask);
 428                     CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
 429             }
 430     }
 431
 432     R600_STATECHANGE(context, cb);
 433     exportCount = (r700->ps.SQ_PGM_EXPORTS_PS.u32All & EXPORT_MODE_mask) / (1 << EXPORT_MODE_shift);
 434     r700->CB_SHADER_CONTROL.u32All = (1 << exportCount) - 1;
 435
 436     /* sent out shader constants. */
 437     paramList = fp->mesa_program.Base.Parameters;
 438
 439     if(NULL != paramList) {
 440             _mesa_load_state_parameters(ctx, paramList);
 441
 442             if (paramList->NumParameters > R700_MAX_DX9_CONSTS)
 443                     return GL_FALSE;
 444
 445             R600_STATECHANGE(context, ps_consts);
 446
 447             r700->ps.num_consts = paramList->NumParameters;
 448
 449             unNumParamData = paramList->NumParameters;
 450
 451             for(ui=0; ui<unNumParamData; ui++) {
 452                     r700->ps.consts[ui][0].f32All = paramList->ParameterValues[ui][0];
 453                     r700->ps.consts[ui][1].f32All = paramList->ParameterValues[ui][1];
 454                     r700->ps.consts[ui][2].f32All = paramList->ParameterValues[ui][2];
 455                     r700->ps.consts[ui][3].f32All = paramList->ParameterValues[ui][3];
 456             }
 457     } else
 458             r700->ps.num_consts = 0;
 459
 460     return GL_TRUE;
 461 }
 462