2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 * CooperYuan <cooper.yuan@amd.com>, <cooperyuan@gmail.com>
28 #include "main/glheader.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/context.h"
35 #include "main/simple_list.h"
36 #include "main/api_arrayelt.h"
37 #include "swrast/swrast.h"
38 #include "swrast_setup/swrast_setup.h"
42 #include "tnl/t_vp_build.h"
43 #include "tnl/t_context.h"
44 #include "tnl/t_vertex.h"
45 #include "vbo/vbo_context.h"
47 #include "r600_context.h"
48 #include "r600_cmdbuf.h"
52 #include "r700_vertprog.h"
53 #include "r700_fragprog.h"
54 #include "r700_state.h"
56 #include "radeon_buffer_objects.h"
57 #include "radeon_common_context.h"
59 void r700WaitForIdle(context_t
*context
);
60 void r700WaitForIdleClean(context_t
*context
);
61 static unsigned int r700PrimitiveType(int prim
);
62 GLboolean
r700SyncSurf(context_t
*context
,
63 struct radeon_bo
*pbo
,
65 uint32_t write_domain
,
68 void r700WaitForIdle(context_t
*context
)
70 BATCH_LOCALS(&context
->radeon
);
71 radeon_print(RADEON_RENDER
| RADEON_STATE
, RADEON_TRACE
, "%s\n", __func__
);
72 BEGIN_BATCH_NO_AUTOSTATE(3);
74 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG
, 1));
75 R600_OUT_BATCH(mmWAIT_UNTIL
- ASIC_CONFIG_BASE_INDEX
);
76 R600_OUT_BATCH(WAIT_3D_IDLE_bit
);
82 void r700WaitForIdleClean(context_t
*context
)
84 BATCH_LOCALS(&context
->radeon
);
85 radeon_print(RADEON_RENDER
| RADEON_STATE
, RADEON_TRACE
, "%s\n", __func__
);
86 BEGIN_BATCH_NO_AUTOSTATE(5);
88 R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE
, 0));
89 R600_OUT_BATCH(CACHE_FLUSH_AND_INV_EVENT
);
91 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG
, 1));
92 R600_OUT_BATCH(mmWAIT_UNTIL
- ASIC_CONFIG_BASE_INDEX
);
93 R600_OUT_BATCH(WAIT_3D_IDLE_bit
| WAIT_3D_IDLECLEAN_bit
);
99 void r700Start3D(context_t
*context
)
101 BATCH_LOCALS(&context
->radeon
);
102 radeon_print(RADEON_RENDER
| RADEON_STATE
, RADEON_TRACE
, "%s\n", __func__
);
103 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
)
105 BEGIN_BATCH_NO_AUTOSTATE(2);
106 R600_OUT_BATCH(CP_PACKET3(R600_IT_START_3D_CMDBUF
, 0));
111 BEGIN_BATCH_NO_AUTOSTATE(3);
112 R600_OUT_BATCH(CP_PACKET3(R600_IT_CONTEXT_CONTROL
, 1));
113 R600_OUT_BATCH(0x80000000);
114 R600_OUT_BATCH(0x80000000);
120 GLboolean
r700SyncSurf(context_t
*context
,
121 struct radeon_bo
*pbo
,
122 uint32_t read_domain
,
123 uint32_t write_domain
,
126 BATCH_LOCALS(&context
->radeon
);
127 radeon_print(RADEON_RENDER
| RADEON_STATE
, RADEON_TRACE
, "%s\n", __func__
);
128 uint32_t cp_coher_size
;
133 if (pbo
->size
== 0xffffffff)
134 cp_coher_size
= 0xffffffff;
136 cp_coher_size
= ((pbo
->size
+ 255) >> 8);
138 BEGIN_BATCH_NO_AUTOSTATE(5 + 2);
139 R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_SYNC
, 3));
140 R600_OUT_BATCH(sync_type
);
141 R600_OUT_BATCH(cp_coher_size
);
144 R600_OUT_BATCH_RELOC(0,
147 read_domain
, write_domain
, 0);
154 static unsigned int r700PrimitiveType(int prim
)
156 switch (prim
& PRIM_MODE_MASK
)
159 return DI_PT_POINTLIST
;
162 return DI_PT_LINELIST
;
165 return DI_PT_LINESTRIP
;
168 return DI_PT_LINELOOP
;
171 return DI_PT_TRILIST
;
173 case GL_TRIANGLE_STRIP
:
174 return DI_PT_TRISTRIP
;
176 case GL_TRIANGLE_FAN
:
180 return DI_PT_QUADLIST
;
183 return DI_PT_QUADSTRIP
;
186 return DI_PT_POLYGON
;
195 static int r700NumVerts(int num_verts
, int prim
)
199 switch (prim
& PRIM_MODE_MASK
) {
204 verts_off
= num_verts
% 2;
208 verts_off
= num_verts
;
212 verts_off
= num_verts
;
215 verts_off
= num_verts
% 3;
217 case GL_TRIANGLE_STRIP
:
219 verts_off
= num_verts
;
221 case GL_TRIANGLE_FAN
:
223 verts_off
= num_verts
;
226 verts_off
= num_verts
% 4;
230 verts_off
= num_verts
;
232 verts_off
= num_verts
% 2;
236 verts_off
= num_verts
;
244 return num_verts
- verts_off
;
247 static void r700RunRenderPrimitive(GLcontext
* ctx
, int start
, int end
,
248 int prim
, GLint basevertex
)
250 context_t
*context
= R700_CONTEXT(ctx
);
251 BATCH_LOCALS(&context
->radeon
);
252 int type
, total_emit
;
254 uint32_t vgt_draw_initiator
= 0;
255 uint32_t vgt_index_type
= 0;
256 uint32_t vgt_primitive_type
= 0;
257 uint32_t vgt_num_indices
= 0;
259 type
= r700PrimitiveType(prim
);
260 num_indices
= r700NumVerts(end
- start
, prim
);
262 radeon_print(RADEON_RENDER
, RADEON_TRACE
,
263 "%s type %x num_indices %d\n",
264 __func__
, type
, num_indices
);
266 if (type
< 0 || num_indices
<= 0)
269 SETfield(vgt_primitive_type
, type
,
270 VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift
, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask
);
272 SETfield(vgt_index_type
, DI_INDEX_SIZE_32_BIT
, INDEX_TYPE_shift
, INDEX_TYPE_mask
);
274 if(GL_TRUE
!= context
->ind_buf
.is_32bit
)
276 SETfield(vgt_index_type
, DI_INDEX_SIZE_16_BIT
, INDEX_TYPE_shift
, INDEX_TYPE_mask
);
279 vgt_num_indices
= num_indices
;
280 SETfield(vgt_draw_initiator
, DI_SRC_SEL_DMA
, SOURCE_SELECT_shift
, SOURCE_SELECT_mask
);
281 SETfield(vgt_draw_initiator
, DI_MAJOR_MODE_0
, MAJOR_MODE_shift
, MAJOR_MODE_mask
);
283 total_emit
= 3 /* VGT_PRIMITIVE_TYPE */
284 + 2 /* VGT_INDEX_TYPE */
285 + 2 /* NUM_INSTANCES */
286 + 4 /* VTX_BASE_VTX_LOC + VTX_START_INST_LOC */
287 + 5 + 2; /* DRAW_INDEX */
289 BEGIN_BATCH_NO_AUTOSTATE(total_emit
);
291 R600_OUT_BATCH_REGSEQ(VGT_PRIMITIVE_TYPE
, 1);
292 R600_OUT_BATCH(vgt_primitive_type
);
294 R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE
, 0));
295 R600_OUT_BATCH(vgt_index_type
);
297 R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES
, 0));
300 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST
, 2));
301 R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC
- ASIC_CTL_CONST_BASE_INDEX
);
302 R600_OUT_BATCH(basevertex
); //VTX_BASE_VTX_LOC
303 R600_OUT_BATCH(0); //VTX_START_INST_LOC
305 R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX
, 3));
306 R600_OUT_BATCH(context
->ind_buf
.bo_offset
);
308 R600_OUT_BATCH(vgt_num_indices
);
309 R600_OUT_BATCH(vgt_draw_initiator
);
310 R600_OUT_BATCH_RELOC(context
->ind_buf
.bo_offset
,
312 context
->ind_buf
.bo_offset
,
313 RADEON_GEM_DOMAIN_GTT
, 0, 0);
318 static void r700RunRenderPrimitiveImmediate(GLcontext
* ctx
, int start
, int end
, int prim
)
320 context_t
*context
= R700_CONTEXT(ctx
);
321 BATCH_LOCALS(&context
->radeon
);
323 uint32_t num_indices
, total_emit
= 0;
324 uint32_t vgt_draw_initiator
= 0;
325 uint32_t vgt_index_type
= 0;
326 uint32_t vgt_primitive_type
= 0;
327 uint32_t vgt_num_indices
= 0;
329 type
= r700PrimitiveType(prim
);
330 num_indices
= r700NumVerts(end
- start
, prim
);
332 radeon_print(RADEON_RENDER
, RADEON_TRACE
,
333 "%s type %x num_indices %d\n",
334 __func__
, type
, num_indices
);
336 if (type
< 0 || num_indices
<= 0)
339 SETfield(vgt_primitive_type
, type
,
340 VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift
, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask
);
342 if (num_indices
> 0xffff)
344 SETfield(vgt_index_type
, DI_INDEX_SIZE_32_BIT
, INDEX_TYPE_shift
, INDEX_TYPE_mask
);
348 SETfield(vgt_index_type
, DI_INDEX_SIZE_16_BIT
, INDEX_TYPE_shift
, INDEX_TYPE_mask
);
351 vgt_num_indices
= num_indices
;
352 SETfield(vgt_draw_initiator
, DI_MAJOR_MODE_0
, MAJOR_MODE_shift
, MAJOR_MODE_mask
);
356 SETfield(vgt_draw_initiator
, DI_SRC_SEL_AUTO_INDEX
, SOURCE_SELECT_shift
, SOURCE_SELECT_mask
);
360 if (num_indices
> 0xffff)
362 total_emit
+= num_indices
;
366 total_emit
+= (num_indices
+ 1) / 2;
368 SETfield(vgt_draw_initiator
, DI_SRC_SEL_IMMEDIATE
, SOURCE_SELECT_shift
, SOURCE_SELECT_mask
);
371 total_emit
+= 3 /* VGT_PRIMITIVE_TYPE */
372 + 2 /* VGT_INDEX_TYPE */
373 + 2 /* NUM_INSTANCES */
374 + 4 /* VTX_BASE_VTX_LOC + VTX_START_INST_LOC */
377 BEGIN_BATCH_NO_AUTOSTATE(total_emit
);
379 R600_OUT_BATCH_REGSEQ(VGT_PRIMITIVE_TYPE
, 1);
380 R600_OUT_BATCH(vgt_primitive_type
);
382 R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE
, 0));
383 R600_OUT_BATCH(vgt_index_type
);
385 R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES
, 0));
388 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST
, 2));
389 R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC
- ASIC_CTL_CONST_BASE_INDEX
);
390 R600_OUT_BATCH(0); //VTX_BASE_VTX_LOC
391 R600_OUT_BATCH(0); //VTX_START_INST_LOC
395 R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO
, 1));
396 R600_OUT_BATCH(vgt_num_indices
);
397 R600_OUT_BATCH(vgt_draw_initiator
);
401 if (num_indices
> 0xffff)
403 R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD
, (num_indices
+ 1)));
404 R600_OUT_BATCH(vgt_num_indices
);
405 R600_OUT_BATCH(vgt_draw_initiator
);
406 for (i
= start
; i
< (start
+ num_indices
); i
++)
413 R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD
, (((num_indices
+ 1) / 2) + 1)));
414 R600_OUT_BATCH(vgt_num_indices
);
415 R600_OUT_BATCH(vgt_draw_initiator
);
416 for (i
= start
; i
< (start
+ num_indices
); i
+= 2)
418 if ((i
+ 1) == (start
+ num_indices
))
424 R600_OUT_BATCH(((i
+ 1) << 16) | (i
));
434 /* start 3d, idle, cb/db flush */
435 #define PRE_EMIT_STATE_BUFSZ 5 + 5 + 14
437 static GLuint
r700PredictRenderSize(GLcontext
* ctx
,
438 const struct _mesa_prim
*prim
,
439 const struct _mesa_index_buffer
*ib
,
442 context_t
*context
= R700_CONTEXT(ctx
);
447 dwords
= PRE_EMIT_STATE_BUFSZ
;
449 dwords
+= nr_prims
* 18;
451 for (i
= 0; i
< nr_prims
; ++i
)
453 if (prim
[i
].start
== 0)
455 else if (prim
[i
].count
> 0xffff)
456 dwords
+= prim
[i
].count
+ 14;
458 dwords
+= ((prim
[i
].count
+ 1) / 2) + 14;
462 state_size
= radeonCountStateEmitSize(&context
->radeon
);
463 flushed
= rcommonEnsureCmdBufSpace(&context
->radeon
,
467 dwords
+= radeonCountStateEmitSize(&context
->radeon
);
469 dwords
+= state_size
;
471 radeon_print(RADEON_RENDER
, RADEON_VERBOSE
, "%s: total prediction size is %d.\n", __FUNCTION__
, dwords
);
476 #define CONVERT( TYPE, MACRO ) do { \
479 if (input->Normalized) { \
480 for (i = 0; i < count; i++) { \
481 const TYPE *in = (TYPE *)src_ptr; \
482 for (j = 0; j < sz; j++) { \
483 *dst_ptr++ = MACRO(*in); \
489 for (i = 0; i < count; i++) { \
490 const TYPE *in = (TYPE *)src_ptr; \
491 for (j = 0; j < sz; j++) { \
492 *dst_ptr++ = (GLfloat)(*in); \
501 * Convert attribute data type to float
502 * If the attribute uses named buffer object replace the bo with newly allocated bo
504 static void r700ConvertAttrib(GLcontext
*ctx
, int count
,
505 const struct gl_client_array
*input
,
506 struct StreamDesc
*attr
)
508 context_t
*context
= R700_CONTEXT(ctx
);
509 const GLvoid
*src_ptr
;
510 GLboolean mapped_named_bo
= GL_FALSE
;
514 stride
= (input
->StrideB
== 0) ? getTypeSize(input
->Type
) * input
->Size
: input
->StrideB
;
516 /* Convert value for first element only */
517 if (input
->StrideB
== 0)
522 if (input
->BufferObj
->Name
)
524 if (!input
->BufferObj
->Pointer
)
526 ctx
->Driver
.MapBuffer(ctx
, GL_ARRAY_BUFFER
, GL_READ_ONLY_ARB
, input
->BufferObj
);
527 mapped_named_bo
= GL_TRUE
;
530 src_ptr
= ADD_POINTERS(input
->BufferObj
->Pointer
, input
->Ptr
);
534 src_ptr
= input
->Ptr
;
537 radeonAllocDmaRegion(&context
->radeon
, &attr
->bo
, &attr
->bo_offset
,
538 sizeof(GLfloat
) * input
->Size
* count
, 32);
540 radeon_bo_map(attr
->bo
, 1);
542 dst_ptr
= (GLfloat
*)ADD_POINTERS(attr
->bo
->ptr
, attr
->bo_offset
);
544 assert(src_ptr
!= NULL
);
549 CONVERT(GLdouble
, (GLfloat
));
551 case GL_UNSIGNED_INT
:
552 CONVERT(GLuint
, UINT_TO_FLOAT
);
555 CONVERT(GLint
, INT_TO_FLOAT
);
557 case GL_UNSIGNED_SHORT
:
558 CONVERT(GLushort
, USHORT_TO_FLOAT
);
561 CONVERT(GLshort
, SHORT_TO_FLOAT
);
563 case GL_UNSIGNED_BYTE
:
564 assert(input
->Format
!= GL_BGRA
);
565 CONVERT(GLubyte
, UBYTE_TO_FLOAT
);
568 CONVERT(GLbyte
, BYTE_TO_FLOAT
);
575 radeon_bo_unmap(attr
->bo
);
579 ctx
->Driver
.UnmapBuffer(ctx
, GL_ARRAY_BUFFER
, input
->BufferObj
);
583 static void r700AlignDataToDword(GLcontext
*ctx
,
584 const struct gl_client_array
*input
,
586 struct StreamDesc
*attr
)
588 context_t
*context
= R700_CONTEXT(ctx
);
589 const int dst_stride
= (input
->StrideB
+ 3) & ~3;
590 const int size
= getTypeSize(input
->Type
) * input
->Size
* count
;
591 GLboolean mapped_named_bo
= GL_FALSE
;
593 radeonAllocDmaRegion(&context
->radeon
, &attr
->bo
, &attr
->bo_offset
, size
, 32);
595 radeon_bo_map(attr
->bo
, 1);
597 if (!input
->BufferObj
->Pointer
)
599 ctx
->Driver
.MapBuffer(ctx
, GL_ARRAY_BUFFER
, GL_READ_ONLY_ARB
, input
->BufferObj
);
600 mapped_named_bo
= GL_TRUE
;
604 GLvoid
*src_ptr
= ADD_POINTERS(input
->BufferObj
->Pointer
, input
->Ptr
);
605 GLvoid
*dst_ptr
= ADD_POINTERS(attr
->bo
->ptr
, attr
->bo_offset
);
608 for (i
= 0; i
< count
; ++i
)
610 memcpy(dst_ptr
, src_ptr
, input
->StrideB
);
611 src_ptr
+= input
->StrideB
;
612 dst_ptr
+= dst_stride
;
616 radeon_bo_unmap(attr
->bo
);
619 ctx
->Driver
.UnmapBuffer(ctx
, GL_ARRAY_BUFFER
, input
->BufferObj
);
622 attr
->stride
= dst_stride
;
625 static void r700SetupStreams(GLcontext
*ctx
, const struct gl_client_array
*input
[], int count
)
627 context_t
*context
= R700_CONTEXT(ctx
);
632 R600_STATECHANGE(context
, vtx
);
634 for(index
= 0; index
< context
->nNumActiveAos
; index
++)
636 struct radeon_aos
*aos
= &context
->radeon
.tcl
.aos
[index
];
637 i
= context
->stream_desc
[index
].element
;
639 stride
= (input
[i
]->StrideB
== 0) ? getTypeSize(input
[i
]->Type
) * input
[i
]->Size
: input
[i
]->StrideB
;
641 if (input
[i
]->Type
== GL_DOUBLE
|| input
[i
]->Type
== GL_UNSIGNED_INT
|| input
[i
]->Type
== GL_INT
643 || getTypeSize(input
[i
]->Type
) != 4
647 r700ConvertAttrib(ctx
, count
, input
[i
], &context
->stream_desc
[index
]);
651 if (input
[i
]->BufferObj
->Name
)
653 context
->stream_desc
[index
].stride
= input
[i
]->StrideB
;
654 context
->stream_desc
[index
].bo_offset
= (intptr_t) input
[i
]->Ptr
;
655 context
->stream_desc
[index
].bo
= get_radeon_buffer_object(input
[i
]->BufferObj
)->bo
;
656 context
->stream_desc
[index
].is_named_bo
= GL_TRUE
;
661 int local_count
= count
;
664 if (input
[i
]->StrideB
== 0)
666 size
= getTypeSize(input
[i
]->Type
) * input
[i
]->Size
;
671 size
= getTypeSize(input
[i
]->Type
) * input
[i
]->Size
* local_count
;
674 radeonAllocDmaRegion(&context
->radeon
, &context
->stream_desc
[index
].bo
,
675 &context
->stream_desc
[index
].bo_offset
, size
, 32);
677 radeon_bo_map(context
->stream_desc
[index
].bo
, 1);
678 assert(context
->stream_desc
[index
].bo
->ptr
!= NULL
);
681 dst
= (uint32_t *)ADD_POINTERS(context
->stream_desc
[index
].bo
->ptr
,
682 context
->stream_desc
[index
].bo_offset
);
684 switch (context
->stream_desc
[index
].dwords
)
687 radeonEmitVec4(dst
, input
[i
]->Ptr
, input
[i
]->StrideB
, local_count
);
690 radeonEmitVec8(dst
, input
[i
]->Ptr
, input
[i
]->StrideB
, local_count
);
693 radeonEmitVec12(dst
, input
[i
]->Ptr
, input
[i
]->StrideB
, local_count
);
696 radeonEmitVec16(dst
, input
[i
]->Ptr
, input
[i
]->StrideB
, local_count
);
702 radeon_bo_unmap(context
->stream_desc
[index
].bo
);
706 aos
->count
= context
->stream_desc
[index
].stride
== 0 ? 1 : count
;
707 aos
->stride
= context
->stream_desc
[index
].stride
/ sizeof(float);
708 aos
->components
= context
->stream_desc
[index
].dwords
;
709 aos
->bo
= context
->stream_desc
[index
].bo
;
710 aos
->offset
= context
->stream_desc
[index
].bo_offset
;
712 if(context
->stream_desc
[index
].is_named_bo
)
714 radeon_cs_space_add_persistent_bo(context
->radeon
.cmdbuf
.cs
,
715 context
->stream_desc
[index
].bo
,
716 RADEON_GEM_DOMAIN_GTT
, 0);
720 ret
= radeon_cs_space_check_with_bo(context
->radeon
.cmdbuf
.cs
,
721 first_elem(&context
->radeon
.dma
.reserved
)->bo
,
722 RADEON_GEM_DOMAIN_GTT
, 0);
725 static void r700FreeData(GLcontext
*ctx
)
727 /* Need to zero tcl.aos[n].bo and tcl.elt_dma_bo
728 * to prevent double unref in radeonReleaseArrays
729 * called during context destroy
731 context_t
*context
= R700_CONTEXT(ctx
);
735 for (i
= 0; i
< context
->nNumActiveAos
; i
++)
737 if (!context
->stream_desc
[i
].is_named_bo
)
739 radeon_bo_unref(context
->stream_desc
[i
].bo
);
741 context
->radeon
.tcl
.aos
[i
].bo
= NULL
;
744 if (context
->ind_buf
.bo
!= NULL
)
746 radeon_bo_unref(context
->ind_buf
.bo
);
750 static void r700FixupIndexBuffer(GLcontext
*ctx
, const struct _mesa_index_buffer
*mesa_ind_buf
)
752 context_t
*context
= R700_CONTEXT(ctx
);
756 GLboolean mapped_named_bo
= GL_FALSE
;
758 if (mesa_ind_buf
->obj
->Name
&& !mesa_ind_buf
->obj
->Pointer
)
760 ctx
->Driver
.MapBuffer(ctx
, GL_ELEMENT_ARRAY_BUFFER
, GL_READ_ONLY_ARB
, mesa_ind_buf
->obj
);
761 mapped_named_bo
= GL_TRUE
;
762 assert(mesa_ind_buf
->obj
->Pointer
!= NULL
);
764 src_ptr
= ADD_POINTERS(mesa_ind_buf
->obj
->Pointer
, mesa_ind_buf
->ptr
);
766 if (mesa_ind_buf
->type
== GL_UNSIGNED_BYTE
)
768 GLuint size
= sizeof(GLushort
) * ((mesa_ind_buf
->count
+ 1) & ~1);
769 GLubyte
*in
= (GLubyte
*)src_ptr
;
771 radeonAllocDmaRegion(&context
->radeon
, &context
->ind_buf
.bo
,
772 &context
->ind_buf
.bo_offset
, size
, 4);
774 radeon_bo_map(context
->ind_buf
.bo
, 1);
775 assert(context
->ind_buf
.bo
->ptr
!= NULL
);
776 out
= (GLuint
*)ADD_POINTERS(context
->ind_buf
.bo
->ptr
, context
->ind_buf
.bo_offset
);
778 for (i
= 0; i
+ 1 < mesa_ind_buf
->count
; i
+= 2)
780 *out
++ = in
[i
] | in
[i
+ 1] << 16;
783 if (i
< mesa_ind_buf
->count
)
788 radeon_bo_unmap(context
->ind_buf
.bo
);
792 { /* if (mesa_ind_buf->type == GL_UNSIGNED_SHORT) */
793 GLushort
*in
= (GLushort
*)src_ptr
;
794 GLuint size
= sizeof(GLushort
) * ((mesa_ind_buf
->count
+ 1) & ~1);
796 radeonAllocDmaRegion(&context
->radeon
, &context
->ind_buf
.bo
,
797 &context
->ind_buf
.bo_offset
, size
, 4);
799 radeon_bo_map(context
->ind_buf
.bo
, 1);
800 assert(context
->ind_buf
.bo
->ptr
!= NULL
);
801 out
= (GLuint
*)ADD_POINTERS(context
->ind_buf
.bo
->ptr
, context
->ind_buf
.bo_offset
);
803 for (i
= 0; i
+ 1 < mesa_ind_buf
->count
; i
+= 2)
805 *out
++ = in
[i
] | in
[i
+ 1] << 16;
808 if (i
< mesa_ind_buf
->count
)
812 radeon_bo_unmap(context
->ind_buf
.bo
);
816 context
->ind_buf
.is_32bit
= GL_FALSE
;
817 context
->ind_buf
.count
= mesa_ind_buf
->count
;
821 ctx
->Driver
.UnmapBuffer(ctx
, GL_ELEMENT_ARRAY_BUFFER
, mesa_ind_buf
->obj
);
825 static void r700SetupIndexBuffer(GLcontext
*ctx
, const struct _mesa_index_buffer
*mesa_ind_buf
)
827 context_t
*context
= R700_CONTEXT(ctx
);
830 context
->ind_buf
.bo
= NULL
;
835 if (mesa_ind_buf
->type
== GL_UNSIGNED_INT
)
837 if (mesa_ind_buf
->type
!= GL_UNSIGNED_BYTE
)
840 const GLvoid
*src_ptr
;
842 GLboolean mapped_named_bo
= GL_FALSE
;
844 if (mesa_ind_buf
->obj
->Name
&& !mesa_ind_buf
->obj
->Pointer
)
846 ctx
->Driver
.MapBuffer(ctx
, GL_ELEMENT_ARRAY_BUFFER
, GL_READ_ONLY_ARB
, mesa_ind_buf
->obj
);
847 assert(mesa_ind_buf
->obj
->Pointer
!= NULL
);
848 mapped_named_bo
= GL_TRUE
;
851 src_ptr
= ADD_POINTERS(mesa_ind_buf
->obj
->Pointer
, mesa_ind_buf
->ptr
);
853 const GLuint size
= mesa_ind_buf
->count
* getTypeSize(mesa_ind_buf
->type
);
855 radeonAllocDmaRegion(&context
->radeon
, &context
->ind_buf
.bo
,
856 &context
->ind_buf
.bo_offset
, size
, 4);
857 radeon_bo_map(context
->ind_buf
.bo
, 1);
858 assert(context
->ind_buf
.bo
->ptr
!= NULL
);
859 dst_ptr
= ADD_POINTERS(context
->ind_buf
.bo
->ptr
, context
->ind_buf
.bo_offset
);
861 memcpy(dst_ptr
, src_ptr
, size
);
863 radeon_bo_unmap(context
->ind_buf
.bo
);
864 context
->ind_buf
.is_32bit
= (mesa_ind_buf
->type
== GL_UNSIGNED_INT
);
865 context
->ind_buf
.count
= mesa_ind_buf
->count
;
869 ctx
->Driver
.UnmapBuffer(ctx
, GL_ELEMENT_ARRAY_BUFFER
, mesa_ind_buf
->obj
);
874 r700FixupIndexBuffer(ctx
, mesa_ind_buf
);
878 static GLboolean
check_fallbacks(GLcontext
*ctx
)
880 if (ctx
->RenderMode
!= GL_RENDER
)
886 static GLboolean
r700TryDrawPrims(GLcontext
*ctx
,
887 const struct gl_client_array
*arrays
[],
888 const struct _mesa_prim
*prim
,
890 const struct _mesa_index_buffer
*ib
,
894 context_t
*context
= R700_CONTEXT(ctx
);
895 radeonContextPtr radeon
= &context
->radeon
;
897 struct radeon_renderbuffer
*rrb
;
900 _mesa_update_state( ctx
);
902 if (check_fallbacks(ctx
))
905 _tnl_UpdateFixedFunctionProgram(ctx
);
906 r700SetVertexFormat(ctx
, arrays
, max_index
+ 1);
907 /* shaders need to be updated before buffers are validated */
908 r700UpdateShaders(ctx
);
909 if (!r600ValidateBuffers(ctx
))
912 /* always emit CB base to prevent
913 * lock ups on some chips.
915 R600_STATECHANGE(context
, cb_target
);
916 /* mark vtx as dirty since it changes per-draw */
917 R600_STATECHANGE(context
, vtx
);
919 r700SetScissor(context
);
920 r700SetupVertexProgram(ctx
);
921 r700SetupFragmentProgram(ctx
);
922 r700UpdateShaderStates(ctx
);
924 GLuint emit_end
= r700PredictRenderSize(ctx
, prim
, ib
, nr_prims
)
925 + context
->radeon
.cmdbuf
.cs
->cdw
;
927 r700SetupIndexBuffer(ctx
, ib
);
928 r700SetupStreams(ctx
, arrays
, max_index
+ 1);
930 radeonEmitState(radeon
);
932 radeon_debug_add_indent();
933 for (i
= 0; i
< nr_prims
; ++i
)
935 if (context
->ind_buf
.bo
)
936 r700RunRenderPrimitive(ctx
,
938 prim
[i
].start
+ prim
[i
].count
,
942 r700RunRenderPrimitiveImmediate(ctx
,
944 prim
[i
].start
+ prim
[i
].count
,
947 radeon_debug_remove_indent();
949 /* Flush render op cached for last several quads. */
950 /* XXX drm should handle this in fence submit */
951 r700WaitForIdleClean(context
);
953 rrb
= radeon_get_colorbuffer(&context
->radeon
);
955 r700SyncSurf(context
, rrb
->bo
, 0, RADEON_GEM_DOMAIN_VRAM
,
956 CB_ACTION_ENA_bit
| (1 << (id
+ 6)));
958 rrb
= radeon_get_depthbuffer(&context
->radeon
);
960 r700SyncSurf(context
, rrb
->bo
, 0, RADEON_GEM_DOMAIN_VRAM
,
961 DB_ACTION_ENA_bit
| DB_DEST_BASE_ENA_bit
);
965 if (emit_end
< context
->radeon
.cmdbuf
.cs
->cdw
)
967 WARN_ONCE("Rendering was %d commands larger than predicted size."
968 " We might overflow command buffer.\n", context
->radeon
.cmdbuf
.cs
->cdw
- emit_end
);
974 static void r700DrawPrims(GLcontext
*ctx
,
975 const struct gl_client_array
*arrays
[],
976 const struct _mesa_prim
*prim
,
978 const struct _mesa_index_buffer
*ib
,
979 GLboolean index_bounds_valid
,
983 GLboolean retval
= GL_FALSE
;
985 context_t
*context
= R700_CONTEXT(ctx
);
986 radeonContextPtr radeon
= &context
->radeon
;
987 radeon_prepare_render(radeon
);
989 /* This check should get folded into just the places that
990 * min/max index are really needed.
993 if (!vbo_all_varyings_in_vbos(arrays
)) {
994 if (!index_bounds_valid
)
995 vbo_get_minmax_index(ctx
, prim
, ib
, &min_index
, &max_index
);
996 /* do we want to rebase, minimizes the
997 * amount of data to upload? */
999 vbo_rebase_prims( ctx
, arrays
, prim
, nr_prims
, ib
, min_index
, max_index
, r700DrawPrims
);
1003 /* Make an attempt at drawing */
1004 retval
= r700TryDrawPrims(ctx
, arrays
, prim
, nr_prims
, ib
, min_index
, max_index
);
1006 /* If failed run tnl pipeline - it should take care of fallbacks */
1008 _swsetup_Wakeup(ctx
);
1009 _tnl_draw_prims(ctx
, arrays
, prim
, nr_prims
, ib
, min_index
, max_index
);
1013 void r700InitDraw(GLcontext
*ctx
)
1015 struct vbo_context
*vbo
= vbo_context(ctx
);
1018 vbo
->draw_prims
= r700DrawPrims
;