2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 * CooperYuan <cooper.yuan@amd.com>, <cooperyuan@gmail.com>
28 #include "main/glheader.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/context.h"
35 #include "main/simple_list.h"
36 #include "main/api_arrayelt.h"
37 #include "swrast/swrast.h"
38 #include "swrast_setup/swrast_setup.h"
42 #include "tnl/t_vp_build.h"
43 #include "tnl/t_context.h"
44 #include "tnl/t_vertex.h"
45 #include "vbo/vbo_context.h"
47 #include "r600_context.h"
48 #include "r600_cmdbuf.h"
52 #include "r700_vertprog.h"
53 #include "r700_fragprog.h"
54 #include "r700_state.h"
56 #include "radeon_buffer_objects.h"
57 #include "radeon_common_context.h"
59 void r700WaitForIdle(context_t
*context
);
60 void r700WaitForIdleClean(context_t
*context
);
61 static unsigned int r700PrimitiveType(int prim
);
62 GLboolean
r700SyncSurf(context_t
*context
,
63 struct radeon_bo
*pbo
,
65 uint32_t write_domain
,
68 void r700WaitForIdle(context_t
*context
)
70 BATCH_LOCALS(&context
->radeon
);
71 radeon_print(RADEON_RENDER
| RADEON_STATE
, RADEON_TRACE
, "%s\n", __func__
);
72 BEGIN_BATCH_NO_AUTOSTATE(3);
74 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG
, 1));
75 R600_OUT_BATCH(mmWAIT_UNTIL
- ASIC_CONFIG_BASE_INDEX
);
76 R600_OUT_BATCH(WAIT_3D_IDLE_bit
);
82 void r700WaitForIdleClean(context_t
*context
)
84 BATCH_LOCALS(&context
->radeon
);
85 radeon_print(RADEON_RENDER
| RADEON_STATE
, RADEON_TRACE
, "%s\n", __func__
);
86 BEGIN_BATCH_NO_AUTOSTATE(5);
88 R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE
, 0));
89 R600_OUT_BATCH(CACHE_FLUSH_AND_INV_EVENT
);
91 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG
, 1));
92 R600_OUT_BATCH(mmWAIT_UNTIL
- ASIC_CONFIG_BASE_INDEX
);
93 R600_OUT_BATCH(WAIT_3D_IDLE_bit
| WAIT_3D_IDLECLEAN_bit
);
99 void r700Start3D(context_t
*context
)
101 BATCH_LOCALS(&context
->radeon
);
102 radeon_print(RADEON_RENDER
| RADEON_STATE
, RADEON_TRACE
, "%s\n", __func__
);
103 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
)
105 BEGIN_BATCH_NO_AUTOSTATE(2);
106 R600_OUT_BATCH(CP_PACKET3(R600_IT_START_3D_CMDBUF
, 0));
111 BEGIN_BATCH_NO_AUTOSTATE(3);
112 R600_OUT_BATCH(CP_PACKET3(R600_IT_CONTEXT_CONTROL
, 1));
113 R600_OUT_BATCH(0x80000000);
114 R600_OUT_BATCH(0x80000000);
119 r700WaitForIdleClean(context
);
122 GLboolean
r700SyncSurf(context_t
*context
,
123 struct radeon_bo
*pbo
,
124 uint32_t read_domain
,
125 uint32_t write_domain
,
128 BATCH_LOCALS(&context
->radeon
);
129 radeon_print(RADEON_RENDER
| RADEON_STATE
, RADEON_TRACE
, "%s\n", __func__
);
130 uint32_t cp_coher_size
;
135 if (pbo
->size
== 0xffffffff)
136 cp_coher_size
= 0xffffffff;
138 cp_coher_size
= ((pbo
->size
+ 255) >> 8);
140 BEGIN_BATCH_NO_AUTOSTATE(5 + 2);
141 R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_SYNC
, 3));
142 R600_OUT_BATCH(sync_type
);
143 R600_OUT_BATCH(cp_coher_size
);
146 R600_OUT_BATCH_RELOC(0,
149 read_domain
, write_domain
, 0);
156 static unsigned int r700PrimitiveType(int prim
)
158 switch (prim
& PRIM_MODE_MASK
)
161 return DI_PT_POINTLIST
;
164 return DI_PT_LINELIST
;
167 return DI_PT_LINESTRIP
;
170 return DI_PT_LINELOOP
;
173 return DI_PT_TRILIST
;
175 case GL_TRIANGLE_STRIP
:
176 return DI_PT_TRISTRIP
;
178 case GL_TRIANGLE_FAN
:
182 return DI_PT_QUADLIST
;
185 return DI_PT_QUADSTRIP
;
188 return DI_PT_POLYGON
;
197 static int r700NumVerts(int num_verts
, int prim
)
201 switch (prim
& PRIM_MODE_MASK
) {
206 verts_off
= num_verts
% 2;
210 verts_off
= num_verts
;
214 verts_off
= num_verts
;
217 verts_off
= num_verts
% 3;
219 case GL_TRIANGLE_STRIP
:
221 verts_off
= num_verts
;
223 case GL_TRIANGLE_FAN
:
225 verts_off
= num_verts
;
228 verts_off
= num_verts
% 4;
232 verts_off
= num_verts
;
234 verts_off
= num_verts
% 2;
238 verts_off
= num_verts
;
246 return num_verts
- verts_off
;
249 static void r700RunRenderPrimitive(GLcontext
* ctx
, int start
, int end
, int prim
)
251 context_t
*context
= R700_CONTEXT(ctx
);
252 BATCH_LOCALS(&context
->radeon
);
253 int type
, total_emit
;
255 uint32_t vgt_draw_initiator
= 0;
256 uint32_t vgt_index_type
= 0;
257 uint32_t vgt_primitive_type
= 0;
258 uint32_t vgt_num_indices
= 0;
260 type
= r700PrimitiveType(prim
);
261 num_indices
= r700NumVerts(end
- start
, prim
);
263 radeon_print(RADEON_RENDER
, RADEON_TRACE
,
264 "%s type %x num_indices %d\n",
265 __func__
, type
, num_indices
);
267 if (type
< 0 || num_indices
<= 0)
270 SETfield(vgt_primitive_type
, type
,
271 VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift
, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask
);
273 SETfield(vgt_index_type
, DI_INDEX_SIZE_32_BIT
, INDEX_TYPE_shift
, INDEX_TYPE_mask
);
275 if(GL_TRUE
!= context
->ind_buf
.is_32bit
)
277 SETfield(vgt_index_type
, DI_INDEX_SIZE_16_BIT
, INDEX_TYPE_shift
, INDEX_TYPE_mask
);
280 vgt_num_indices
= num_indices
;
281 SETfield(vgt_draw_initiator
, DI_SRC_SEL_DMA
, SOURCE_SELECT_shift
, SOURCE_SELECT_mask
);
282 SETfield(vgt_draw_initiator
, DI_MAJOR_MODE_0
, MAJOR_MODE_shift
, MAJOR_MODE_mask
);
284 total_emit
= 3 /* VGT_PRIMITIVE_TYPE */
285 + 2 /* VGT_INDEX_TYPE */
286 + 2 /* NUM_INSTANCES */
287 + 5 + 2; /* DRAW_INDEX */
289 BEGIN_BATCH_NO_AUTOSTATE(total_emit
);
291 R600_OUT_BATCH_REGSEQ(VGT_PRIMITIVE_TYPE
, 1);
292 R600_OUT_BATCH(vgt_primitive_type
);
294 R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE
, 0));
295 R600_OUT_BATCH(vgt_index_type
);
297 R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES
, 0));
300 R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX
, 3));
301 R600_OUT_BATCH(context
->ind_buf
.bo_offset
);
303 R600_OUT_BATCH(vgt_num_indices
);
304 R600_OUT_BATCH(vgt_draw_initiator
);
305 R600_OUT_BATCH_RELOC(context
->ind_buf
.bo_offset
,
307 context
->ind_buf
.bo_offset
,
308 RADEON_GEM_DOMAIN_GTT
, 0, 0);
313 static void r700RunRenderPrimitiveImmediate(GLcontext
* ctx
, int start
, int end
, int prim
)
315 context_t
*context
= R700_CONTEXT(ctx
);
316 BATCH_LOCALS(&context
->radeon
);
318 uint32_t num_indices
, total_emit
= 0;
319 uint32_t vgt_draw_initiator
= 0;
320 uint32_t vgt_index_type
= 0;
321 uint32_t vgt_primitive_type
= 0;
322 uint32_t vgt_num_indices
= 0;
324 type
= r700PrimitiveType(prim
);
325 num_indices
= r700NumVerts(end
- start
, prim
);
327 radeon_print(RADEON_RENDER
, RADEON_TRACE
,
328 "%s type %x num_indices %d\n",
329 __func__
, type
, num_indices
);
331 if (type
< 0 || num_indices
<= 0)
334 SETfield(vgt_primitive_type
, type
,
335 VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift
, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask
);
337 if (num_indices
> 0xffff)
339 SETfield(vgt_index_type
, DI_INDEX_SIZE_32_BIT
, INDEX_TYPE_shift
, INDEX_TYPE_mask
);
343 SETfield(vgt_index_type
, DI_INDEX_SIZE_16_BIT
, INDEX_TYPE_shift
, INDEX_TYPE_mask
);
346 vgt_num_indices
= num_indices
;
347 SETfield(vgt_draw_initiator
, DI_MAJOR_MODE_0
, MAJOR_MODE_shift
, MAJOR_MODE_mask
);
351 SETfield(vgt_draw_initiator
, DI_SRC_SEL_AUTO_INDEX
, SOURCE_SELECT_shift
, SOURCE_SELECT_mask
);
355 if (num_indices
> 0xffff)
357 total_emit
+= num_indices
;
361 total_emit
+= (num_indices
+ 1) / 2;
363 SETfield(vgt_draw_initiator
, DI_SRC_SEL_IMMEDIATE
, SOURCE_SELECT_shift
, SOURCE_SELECT_mask
);
366 total_emit
+= 3 /* VGT_PRIMITIVE_TYPE */
367 + 2 /* VGT_INDEX_TYPE */
368 + 2 /* NUM_INSTANCES */
371 BEGIN_BATCH_NO_AUTOSTATE(total_emit
);
373 R600_OUT_BATCH_REGSEQ(VGT_PRIMITIVE_TYPE
, 1);
374 R600_OUT_BATCH(vgt_primitive_type
);
376 R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE
, 0));
377 R600_OUT_BATCH(vgt_index_type
);
379 R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES
, 0));
384 R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO
, 1));
385 R600_OUT_BATCH(vgt_num_indices
);
386 R600_OUT_BATCH(vgt_draw_initiator
);
390 if (num_indices
> 0xffff)
392 R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD
, (num_indices
+ 1)));
393 R600_OUT_BATCH(vgt_num_indices
);
394 R600_OUT_BATCH(vgt_draw_initiator
);
395 for (i
= start
; i
< (start
+ num_indices
); i
++)
402 R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD
, (((num_indices
+ 1) / 2) + 1)));
403 R600_OUT_BATCH(vgt_num_indices
);
404 R600_OUT_BATCH(vgt_draw_initiator
);
405 for (i
= start
; i
< (start
+ num_indices
); i
+= 2)
407 if ((i
+ 1) == (start
+ num_indices
))
413 R600_OUT_BATCH(((i
+ 1) << 16) | (i
));
423 /* start 3d, idle, cb/db flush */
424 #define PRE_EMIT_STATE_BUFSZ 10 + 5 + 18
426 static GLuint
r700PredictRenderSize(GLcontext
* ctx
,
427 const struct _mesa_prim
*prim
,
428 const struct _mesa_index_buffer
*ib
,
431 context_t
*context
= R700_CONTEXT(ctx
);
436 dwords
= PRE_EMIT_STATE_BUFSZ
;
438 dwords
+= nr_prims
* 14;
440 for (i
= 0; i
< nr_prims
; ++i
)
442 if (prim
[i
].start
== 0)
444 else if (prim
[i
].count
> 0xffff)
445 dwords
+= prim
[i
].count
+ 10;
447 dwords
+= ((prim
[i
].count
+ 1) / 2) + 10;
451 state_size
= radeonCountStateEmitSize(&context
->radeon
);
452 flushed
= rcommonEnsureCmdBufSpace(&context
->radeon
,
456 dwords
+= radeonCountStateEmitSize(&context
->radeon
);
458 dwords
+= state_size
;
460 radeon_print(RADEON_RENDER
, RADEON_VERBOSE
, "%s: total prediction size is %d.\n", __FUNCTION__
, dwords
);
465 #define CONVERT( TYPE, MACRO ) do { \
468 if (input->Normalized) { \
469 for (i = 0; i < count; i++) { \
470 const TYPE *in = (TYPE *)src_ptr; \
471 for (j = 0; j < sz; j++) { \
472 *dst_ptr++ = MACRO(*in); \
478 for (i = 0; i < count; i++) { \
479 const TYPE *in = (TYPE *)src_ptr; \
480 for (j = 0; j < sz; j++) { \
481 *dst_ptr++ = (GLfloat)(*in); \
490 * Convert attribute data type to float
491 * If the attribute uses named buffer object replace the bo with newly allocated bo
493 static void r700ConvertAttrib(GLcontext
*ctx
, int count
,
494 const struct gl_client_array
*input
,
495 struct StreamDesc
*attr
)
497 context_t
*context
= R700_CONTEXT(ctx
);
498 const GLvoid
*src_ptr
;
499 GLboolean mapped_named_bo
= GL_FALSE
;
503 stride
= (input
->StrideB
== 0) ? getTypeSize(input
->Type
) * input
->Size
: input
->StrideB
;
505 /* Convert value for first element only */
506 if (input
->StrideB
== 0)
511 if (input
->BufferObj
->Name
)
513 if (!input
->BufferObj
->Pointer
)
515 ctx
->Driver
.MapBuffer(ctx
, GL_ARRAY_BUFFER
, GL_READ_ONLY_ARB
, input
->BufferObj
);
516 mapped_named_bo
= GL_TRUE
;
519 src_ptr
= ADD_POINTERS(input
->BufferObj
->Pointer
, input
->Ptr
);
523 src_ptr
= input
->Ptr
;
526 radeonAllocDmaRegion(&context
->radeon
, &attr
->bo
, &attr
->bo_offset
,
527 sizeof(GLfloat
) * input
->Size
* count
, 32);
529 radeon_bo_map(attr
->bo
, 1);
531 dst_ptr
= (GLfloat
*)ADD_POINTERS(attr
->bo
->ptr
, attr
->bo_offset
);
533 assert(src_ptr
!= NULL
);
538 CONVERT(GLdouble
, (GLfloat
));
540 case GL_UNSIGNED_INT
:
541 CONVERT(GLuint
, UINT_TO_FLOAT
);
544 CONVERT(GLint
, INT_TO_FLOAT
);
546 case GL_UNSIGNED_SHORT
:
547 CONVERT(GLushort
, USHORT_TO_FLOAT
);
550 CONVERT(GLshort
, SHORT_TO_FLOAT
);
552 case GL_UNSIGNED_BYTE
:
553 assert(input
->Format
!= GL_BGRA
);
554 CONVERT(GLubyte
, UBYTE_TO_FLOAT
);
557 CONVERT(GLbyte
, BYTE_TO_FLOAT
);
564 radeon_bo_unmap(attr
->bo
);
568 ctx
->Driver
.UnmapBuffer(ctx
, GL_ARRAY_BUFFER
, input
->BufferObj
);
572 static void r700AlignDataToDword(GLcontext
*ctx
,
573 const struct gl_client_array
*input
,
575 struct StreamDesc
*attr
)
577 context_t
*context
= R700_CONTEXT(ctx
);
578 const int dst_stride
= (input
->StrideB
+ 3) & ~3;
579 const int size
= getTypeSize(input
->Type
) * input
->Size
* count
;
580 GLboolean mapped_named_bo
= GL_FALSE
;
582 radeonAllocDmaRegion(&context
->radeon
, &attr
->bo
, &attr
->bo_offset
, size
, 32);
584 radeon_bo_map(attr
->bo
, 1);
586 if (!input
->BufferObj
->Pointer
)
588 ctx
->Driver
.MapBuffer(ctx
, GL_ARRAY_BUFFER
, GL_READ_ONLY_ARB
, input
->BufferObj
);
589 mapped_named_bo
= GL_TRUE
;
593 GLvoid
*src_ptr
= ADD_POINTERS(input
->BufferObj
->Pointer
, input
->Ptr
);
594 GLvoid
*dst_ptr
= ADD_POINTERS(attr
->bo
->ptr
, attr
->bo_offset
);
597 for (i
= 0; i
< count
; ++i
)
599 _mesa_memcpy(dst_ptr
, src_ptr
, input
->StrideB
);
600 src_ptr
+= input
->StrideB
;
601 dst_ptr
+= dst_stride
;
605 radeon_bo_unmap(attr
->bo
);
608 ctx
->Driver
.UnmapBuffer(ctx
, GL_ARRAY_BUFFER
, input
->BufferObj
);
611 attr
->stride
= dst_stride
;
614 static void r700SetupStreams(GLcontext
*ctx
, const struct gl_client_array
*input
[], int count
)
616 context_t
*context
= R700_CONTEXT(ctx
);
621 R600_STATECHANGE(context
, vtx
);
623 for(index
= 0; index
< context
->nNumActiveAos
; index
++)
625 struct radeon_aos
*aos
= &context
->radeon
.tcl
.aos
[index
];
626 i
= context
->stream_desc
[index
].element
;
628 stride
= (input
[i
]->StrideB
== 0) ? getTypeSize(input
[i
]->Type
) * input
[i
]->Size
: input
[i
]->StrideB
;
630 if (input
[i
]->Type
== GL_DOUBLE
|| input
[i
]->Type
== GL_UNSIGNED_INT
|| input
[i
]->Type
== GL_INT
||
632 getTypeSize(input
[i
]->Type
) != 4 ||
636 r700ConvertAttrib(ctx
, count
, input
[i
], &context
->stream_desc
[index
]);
640 if (input
[i
]->BufferObj
->Name
)
644 assert(((intptr_t) input
[i
]->Ptr
) % input
[i
]->StrideB
== 0);
645 r700AlignDataToDword(ctx
, input
[i
], count
, &context
->stream_desc
[index
]);
646 context
->stream_desc
[index
].is_named_bo
= GL_FALSE
;
650 context
->stream_desc
[index
].stride
= input
[i
]->StrideB
;
651 context
->stream_desc
[index
].bo_offset
= (intptr_t) input
[i
]->Ptr
;
652 context
->stream_desc
[index
].bo
= get_radeon_buffer_object(input
[i
]->BufferObj
)->bo
;
653 context
->stream_desc
[index
].is_named_bo
= GL_TRUE
;
659 int local_count
= count
;
662 if (input
[i
]->StrideB
== 0)
664 size
= getTypeSize(input
[i
]->Type
) * input
[i
]->Size
;
669 size
= getTypeSize(input
[i
]->Type
) * input
[i
]->Size
* local_count
;
672 radeonAllocDmaRegion(&context
->radeon
, &context
->stream_desc
[index
].bo
,
673 &context
->stream_desc
[index
].bo_offset
, size
, 32);
675 radeon_bo_map(context
->stream_desc
[index
].bo
, 1);
676 assert(context
->stream_desc
[index
].bo
->ptr
!= NULL
);
679 dst
= (uint32_t *)ADD_POINTERS(context
->stream_desc
[index
].bo
->ptr
,
680 context
->stream_desc
[index
].bo_offset
);
682 switch (context
->stream_desc
[index
].dwords
)
685 radeonEmitVec4(dst
, input
[i
]->Ptr
, input
[i
]->StrideB
, local_count
);
688 radeonEmitVec8(dst
, input
[i
]->Ptr
, input
[i
]->StrideB
, local_count
);
691 radeonEmitVec12(dst
, input
[i
]->Ptr
, input
[i
]->StrideB
, local_count
);
694 radeonEmitVec16(dst
, input
[i
]->Ptr
, input
[i
]->StrideB
, local_count
);
700 radeon_bo_unmap(context
->stream_desc
[index
].bo
);
704 aos
->count
= context
->stream_desc
[index
].stride
== 0 ? 1 : count
;
705 aos
->stride
= context
->stream_desc
[index
].stride
/ sizeof(float);
706 aos
->components
= context
->stream_desc
[index
].dwords
;
707 aos
->bo
= context
->stream_desc
[index
].bo
;
708 aos
->offset
= context
->stream_desc
[index
].bo_offset
;
710 if(context
->stream_desc
[index
].is_named_bo
)
712 radeon_cs_space_add_persistent_bo(context
->radeon
.cmdbuf
.cs
,
713 context
->stream_desc
[index
].bo
,
714 RADEON_GEM_DOMAIN_GTT
, 0);
718 ret
= radeon_cs_space_check_with_bo(context
->radeon
.cmdbuf
.cs
,
719 first_elem(&context
->radeon
.dma
.reserved
)->bo
,
720 RADEON_GEM_DOMAIN_GTT
, 0);
723 static void r700FreeData(GLcontext
*ctx
)
725 /* Need to zero tcl.aos[n].bo and tcl.elt_dma_bo
726 * to prevent double unref in radeonReleaseArrays
727 * called during context destroy
729 context_t
*context
= R700_CONTEXT(ctx
);
733 for (i
= 0; i
< context
->nNumActiveAos
; i
++)
735 if (!context
->stream_desc
[i
].is_named_bo
)
737 radeon_bo_unref(context
->stream_desc
[i
].bo
);
739 context
->radeon
.tcl
.aos
[i
].bo
= NULL
;
742 if (context
->ind_buf
.bo
!= NULL
)
744 radeon_bo_unref(context
->ind_buf
.bo
);
748 static void r700FixupIndexBuffer(GLcontext
*ctx
, const struct _mesa_index_buffer
*mesa_ind_buf
)
750 context_t
*context
= R700_CONTEXT(ctx
);
754 GLboolean mapped_named_bo
= GL_FALSE
;
756 if (mesa_ind_buf
->obj
->Name
&& !mesa_ind_buf
->obj
->Pointer
)
758 ctx
->Driver
.MapBuffer(ctx
, GL_ELEMENT_ARRAY_BUFFER
, GL_READ_ONLY_ARB
, mesa_ind_buf
->obj
);
759 mapped_named_bo
= GL_TRUE
;
760 assert(mesa_ind_buf
->obj
->Pointer
!= NULL
);
762 src_ptr
= ADD_POINTERS(mesa_ind_buf
->obj
->Pointer
, mesa_ind_buf
->ptr
);
764 if (mesa_ind_buf
->type
== GL_UNSIGNED_BYTE
)
766 GLuint size
= sizeof(GLushort
) * ((mesa_ind_buf
->count
+ 1) & ~1);
767 GLubyte
*in
= (GLubyte
*)src_ptr
;
769 radeonAllocDmaRegion(&context
->radeon
, &context
->ind_buf
.bo
,
770 &context
->ind_buf
.bo_offset
, size
, 4);
772 radeon_bo_map(context
->ind_buf
.bo
, 1);
773 assert(context
->ind_buf
.bo
->ptr
!= NULL
);
774 out
= (GLuint
*)ADD_POINTERS(context
->ind_buf
.bo
->ptr
, context
->ind_buf
.bo_offset
);
776 for (i
= 0; i
+ 1 < mesa_ind_buf
->count
; i
+= 2)
778 *out
++ = in
[i
] | in
[i
+ 1] << 16;
781 if (i
< mesa_ind_buf
->count
)
786 radeon_bo_unmap(context
->ind_buf
.bo
);
790 { /* if (mesa_ind_buf->type == GL_UNSIGNED_SHORT) */
791 GLushort
*in
= (GLushort
*)src_ptr
;
792 GLuint size
= sizeof(GLushort
) * ((mesa_ind_buf
->count
+ 1) & ~1);
794 radeonAllocDmaRegion(&context
->radeon
, &context
->ind_buf
.bo
,
795 &context
->ind_buf
.bo_offset
, size
, 4);
797 radeon_bo_map(context
->ind_buf
.bo
, 1);
798 assert(context
->ind_buf
.bo
->ptr
!= NULL
);
799 out
= (GLuint
*)ADD_POINTERS(context
->ind_buf
.bo
->ptr
, context
->ind_buf
.bo_offset
);
801 for (i
= 0; i
+ 1 < mesa_ind_buf
->count
; i
+= 2)
803 *out
++ = in
[i
] | in
[i
+ 1] << 16;
806 if (i
< mesa_ind_buf
->count
)
810 radeon_bo_unmap(context
->ind_buf
.bo
);
814 context
->ind_buf
.is_32bit
= GL_FALSE
;
815 context
->ind_buf
.count
= mesa_ind_buf
->count
;
819 ctx
->Driver
.UnmapBuffer(ctx
, GL_ELEMENT_ARRAY_BUFFER
, mesa_ind_buf
->obj
);
823 static void r700SetupIndexBuffer(GLcontext
*ctx
, const struct _mesa_index_buffer
*mesa_ind_buf
)
825 context_t
*context
= R700_CONTEXT(ctx
);
828 context
->ind_buf
.bo
= NULL
;
833 if (mesa_ind_buf
->type
== GL_UNSIGNED_INT
)
836 if (mesa_ind_buf
->type
!= GL_UNSIGNED_BYTE
)
839 const GLvoid
*src_ptr
;
841 GLboolean mapped_named_bo
= GL_FALSE
;
843 if (mesa_ind_buf
->obj
->Name
&& !mesa_ind_buf
->obj
->Pointer
)
845 ctx
->Driver
.MapBuffer(ctx
, GL_ELEMENT_ARRAY_BUFFER
, GL_READ_ONLY_ARB
, mesa_ind_buf
->obj
);
846 assert(mesa_ind_buf
->obj
->Pointer
!= NULL
);
847 mapped_named_bo
= GL_TRUE
;
850 src_ptr
= ADD_POINTERS(mesa_ind_buf
->obj
->Pointer
, mesa_ind_buf
->ptr
);
852 const GLuint size
= mesa_ind_buf
->count
* getTypeSize(mesa_ind_buf
->type
);
854 radeonAllocDmaRegion(&context
->radeon
, &context
->ind_buf
.bo
,
855 &context
->ind_buf
.bo_offset
, size
, 4);
856 radeon_bo_map(context
->ind_buf
.bo
, 1);
857 assert(context
->ind_buf
.bo
->ptr
!= NULL
);
858 dst_ptr
= ADD_POINTERS(context
->ind_buf
.bo
->ptr
, context
->ind_buf
.bo_offset
);
860 _mesa_memcpy(dst_ptr
, src_ptr
, size
);
862 radeon_bo_unmap(context
->ind_buf
.bo
);
863 context
->ind_buf
.is_32bit
= (mesa_ind_buf
->type
== GL_UNSIGNED_INT
);
864 context
->ind_buf
.count
= mesa_ind_buf
->count
;
868 ctx
->Driver
.UnmapBuffer(ctx
, GL_ELEMENT_ARRAY_BUFFER
, mesa_ind_buf
->obj
);
873 r700FixupIndexBuffer(ctx
, mesa_ind_buf
);
877 static GLboolean
r700TryDrawPrims(GLcontext
*ctx
,
878 const struct gl_client_array
*arrays
[],
879 const struct _mesa_prim
*prim
,
881 const struct _mesa_index_buffer
*ib
,
885 context_t
*context
= R700_CONTEXT(ctx
);
886 radeonContextPtr radeon
= &context
->radeon
;
888 struct radeon_renderbuffer
*rrb
;
891 _mesa_update_state( ctx
);
893 _tnl_UpdateFixedFunctionProgram(ctx
);
894 r700SetVertexFormat(ctx
, arrays
, max_index
+ 1);
895 /* shaders need to be updated before buffers are validated */
896 r700UpdateShaders(ctx
);
897 if (!r600ValidateBuffers(ctx
))
900 /* always emit CB base to prevent
901 * lock ups on some chips.
903 R600_STATECHANGE(context
, cb_target
);
904 /* mark vtx as dirty since it changes per-draw */
905 R600_STATECHANGE(context
, vtx
);
907 r700SetScissor(context
);
908 r700SetupVertexProgram(ctx
);
909 r700SetupFragmentProgram(ctx
);
910 r700UpdateShaderStates(ctx
);
912 GLuint emit_end
= r700PredictRenderSize(ctx
, prim
, ib
, nr_prims
)
913 + context
->radeon
.cmdbuf
.cs
->cdw
;
915 r700SetupIndexBuffer(ctx
, ib
);
916 r700SetupStreams(ctx
, arrays
, max_index
+ 1);
918 radeonEmitState(radeon
);
920 radeon_debug_add_indent();
921 for (i
= 0; i
< nr_prims
; ++i
)
923 if (context
->ind_buf
.bo
)
924 r700RunRenderPrimitive(ctx
,
926 prim
[i
].start
+ prim
[i
].count
,
929 r700RunRenderPrimitiveImmediate(ctx
,
931 prim
[i
].start
+ prim
[i
].count
,
934 radeon_debug_remove_indent();
936 /* Flush render op cached for last several quads. */
937 r700WaitForIdleClean(context
);
939 rrb
= radeon_get_colorbuffer(&context
->radeon
);
941 r700SyncSurf(context
, rrb
->bo
, 0, RADEON_GEM_DOMAIN_VRAM
,
942 CB_ACTION_ENA_bit
| (1 << (id
+ 6)));
944 rrb
= radeon_get_depthbuffer(&context
->radeon
);
946 r700SyncSurf(context
, rrb
->bo
, 0, RADEON_GEM_DOMAIN_VRAM
,
947 DB_ACTION_ENA_bit
| DB_DEST_BASE_ENA_bit
);
951 if (emit_end
< context
->radeon
.cmdbuf
.cs
->cdw
)
953 WARN_ONCE("Rendering was %d commands larger than predicted size."
954 " We might overflow command buffer.\n", context
->radeon
.cmdbuf
.cs
->cdw
- emit_end
);
960 static void r700DrawPrims(GLcontext
*ctx
,
961 const struct gl_client_array
*arrays
[],
962 const struct _mesa_prim
*prim
,
964 const struct _mesa_index_buffer
*ib
,
965 GLboolean index_bounds_valid
,
969 GLboolean retval
= GL_FALSE
;
971 /* This check should get folded into just the places that
972 * min/max index are really needed.
974 if (!index_bounds_valid
) {
975 vbo_get_minmax_index(ctx
, prim
, ib
, &min_index
, &max_index
);
979 vbo_rebase_prims( ctx
, arrays
, prim
, nr_prims
, ib
, min_index
, max_index
, r700DrawPrims
);
983 /* Make an attempt at drawing */
984 retval
= r700TryDrawPrims(ctx
, arrays
, prim
, nr_prims
, ib
, min_index
, max_index
);
986 /* If failed run tnl pipeline - it should take care of fallbacks */
988 _tnl_draw_prims(ctx
, arrays
, prim
, nr_prims
, ib
, min_index
, max_index
);
991 void r700InitDraw(GLcontext
*ctx
)
993 struct vbo_context
*vbo
= vbo_context(ctx
);
996 vbo
->draw_prims
= r700DrawPrims
;