src/mesa/drivers/dri/r600/r700_render.c

   1 /*
   2  * Copyright (C) 2008-2009  Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  */
  21
  22 /*
  23  * Authors:
  24  *   Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
  25  *   CooperYuan <cooper.yuan@amd.com>, <cooperyuan@gmail.com>
  26  */
  27
  28 #include "main/glheader.h"
  29 #include "main/state.h"
  30 #include "main/imports.h"
  31 #include "main/enums.h"
  32 #include "main/macros.h"
  33 #include "main/context.h"
  34 #include "main/dd.h"
  35 #include "main/simple_list.h"
  36 #include "main/api_arrayelt.h"
  37 #include "swrast/swrast.h"
  38 #include "swrast_setup/swrast_setup.h"
  39 #include "vbo/vbo.h"
  40
  41 #include "tnl/tnl.h"
  42 #include "tnl/t_vp_build.h"
  43 #include "tnl/t_context.h"
  44 #include "tnl/t_vertex.h"
  45 #include "tnl/t_pipeline.h"
  46
  47 #include "r600_context.h"
  48 #include "r600_cmdbuf.h"
  49
  50 #include "r600_tex.h"
  51
  52 #include "r700_vertprog.h"
  53 #include "r700_fragprog.h"
  54 #include "r700_state.h"
  55
  56 void r700WaitForIdle(context_t *context);
  57 void r700WaitForIdleClean(context_t *context);
  58 void r700Start3D(context_t *context);
  59 GLboolean r700SendTextureState(context_t *context);
  60 static unsigned int r700PrimitiveType(int prim);
  61 void r600UpdateTextureState(GLcontext * ctx);
  62 GLboolean r700SyncSurf(context_t *context,
  63                        struct radeon_bo *pbo,
  64                        uint32_t read_domain,
  65                        uint32_t write_domain,
  66                        uint32_t sync_type);
  67
  68 void r700WaitForIdle(context_t *context)
  69 {
  70     BATCH_LOCALS(&context->radeon);
  71     BEGIN_BATCH_NO_AUTOSTATE(3);
  72
  73     R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
  74     R600_OUT_BATCH(mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX);
  75     R600_OUT_BATCH(WAIT_3D_IDLE_bit);
  76
  77     END_BATCH();
  78     COMMIT_BATCH();
  79 }
  80
  81 void r700WaitForIdleClean(context_t *context)
  82 {
  83     BATCH_LOCALS(&context->radeon);
  84     BEGIN_BATCH_NO_AUTOSTATE(5);
  85
  86     R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
  87     R600_OUT_BATCH(CACHE_FLUSH_AND_INV_EVENT);
  88
  89     R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
  90     R600_OUT_BATCH(mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX);
  91     R600_OUT_BATCH(WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
  92
  93     END_BATCH();
  94     COMMIT_BATCH();
  95 }
  96
  97 void r700Start3D(context_t *context)
  98 {
  99     BATCH_LOCALS(&context->radeon);
 100     if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
 101     {
 102         BEGIN_BATCH_NO_AUTOSTATE(2);
 103         R600_OUT_BATCH(CP_PACKET3(R600_IT_START_3D_CMDBUF, 0));
 104         R600_OUT_BATCH(0);
 105         END_BATCH();
 106     }
 107
 108     BEGIN_BATCH_NO_AUTOSTATE(3);
 109     R600_OUT_BATCH(CP_PACKET3(R600_IT_CONTEXT_CONTROL, 1));
 110     R600_OUT_BATCH(0x80000000);
 111     R600_OUT_BATCH(0x80000000);
 112     END_BATCH();
 113
 114     COMMIT_BATCH();
 115
 116     r700WaitForIdleClean(context);
 117 }
 118
 119 static GLboolean r700SetupShaders(GLcontext * ctx)
 120 {
 121     context_t *context = R700_CONTEXT(ctx);
 122
 123     R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
 124
 125     GLuint exportCount;
 126
 127     r700->ps.SQ_PGM_RESOURCES_PS.u32All = 0;
 128     r700->vs.SQ_PGM_RESOURCES_VS.u32All = 0;
 129
 130     SETbit(r700->ps.SQ_PGM_RESOURCES_PS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit);
 131     SETbit(r700->vs.SQ_PGM_RESOURCES_VS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit);
 132
 133     r700SetupVertexProgram(ctx);
 134
 135     r700SetupFragmentProgram(ctx);
 136
 137     exportCount = (r700->ps.SQ_PGM_EXPORTS_PS.u32All & EXPORT_MODE_mask) / (1 << EXPORT_MODE_shift);
 138     r700->CB_SHADER_CONTROL.u32All = (1 << exportCount) - 1;
 139
 140     r600UpdateTextureState(ctx);
 141
 142     return GL_TRUE;
 143 }
 144
 145 GLboolean r700SyncSurf(context_t *context,
 146                        struct radeon_bo *pbo,
 147                        uint32_t read_domain,
 148                        uint32_t write_domain,
 149                        uint32_t sync_type)
 150 {
 151     BATCH_LOCALS(&context->radeon);
 152     uint32_t cp_coher_size;
 153
 154     if (!pbo)
 155             return GL_FALSE;
 156
 157     if (pbo->size == 0xffffffff)
 158             cp_coher_size = 0xffffffff;
 159     else
 160             cp_coher_size = ((pbo->size + 255) >> 8);
 161
 162     BEGIN_BATCH_NO_AUTOSTATE(5);
 163     R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_SYNC, 3));
 164     R600_OUT_BATCH(sync_type);
 165     R600_OUT_BATCH(cp_coher_size);
 166     R600_OUT_BATCH_RELOC(0,
 167                          pbo,
 168                          0,
 169                          read_domain, write_domain, 0); // ???
 170     R600_OUT_BATCH(10);
 171
 172     END_BATCH();
 173     COMMIT_BATCH();
 174
 175     return GL_TRUE;
 176 }
 177
 178 static unsigned int r700PrimitiveType(int prim)
 179 {
 180     switch (prim & PRIM_MODE_MASK)
 181     {
 182     case GL_POINTS:
 183         return DI_PT_POINTLIST;
 184         break;
 185     case GL_LINES:
 186         return DI_PT_LINELIST;
 187         break;
 188     case GL_LINE_STRIP:
 189         return DI_PT_LINESTRIP;
 190         break;
 191     case GL_LINE_LOOP:
 192         return DI_PT_LINELOOP;
 193         break;
 194     case GL_TRIANGLES:
 195         return DI_PT_TRILIST;
 196         break;
 197     case GL_TRIANGLE_STRIP:
 198         return DI_PT_TRISTRIP;
 199         break;
 200     case GL_TRIANGLE_FAN:
 201         return DI_PT_TRIFAN;
 202         break;
 203     case GL_QUADS:
 204         return DI_PT_QUADLIST;
 205         break;
 206     case GL_QUAD_STRIP:
 207         return DI_PT_QUADSTRIP;
 208         break;
 209     case GL_POLYGON:
 210         return DI_PT_POLYGON;
 211         break;
 212     default:
 213         assert(0);
 214         return -1;
 215         break;
 216     }
 217 }
 218
 219 static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim)
 220 {
 221         context_t *context = R700_CONTEXT(ctx);
 222         BATCH_LOCALS(&context->radeon);
 223         int type, i, total_emit;
 224         int num_indices = end - start;
 225         uint32_t vgt_draw_initiator = 0;
 226         uint32_t vgt_index_type     = 0;
 227         uint32_t vgt_primitive_type = 0;
 228         uint32_t vgt_num_indices    = 0;
 229
 230         type = r700PrimitiveType(prim);
 231
 232         if (type < 0 || num_indices <= 0)
 233                 return;
 234
 235         total_emit =   3 /* VGT_PRIMITIVE_TYPE */
 236                      + 2 /* VGT_INDEX_TYPE */
 237                      + 2 /* NUM_INSTANCES */
 238                      + num_indices + 3; /* DRAW_INDEX_IMMD */
 239
 240         BEGIN_BATCH_NO_AUTOSTATE(total_emit);
 241         // prim
 242         SETfield(vgt_primitive_type, type,
 243                  VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask);
 244         R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
 245         R600_OUT_BATCH(mmVGT_PRIMITIVE_TYPE - ASIC_CONFIG_BASE_INDEX);
 246         R600_OUT_BATCH(vgt_primitive_type);
 247
 248         // index type
 249         SETfield(vgt_index_type, DI_INDEX_SIZE_32_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask);
 250         R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
 251         R600_OUT_BATCH(vgt_index_type);
 252
 253         // num instances
 254         R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
 255         R600_OUT_BATCH(1);
 256
 257         // draw packet
 258         vgt_num_indices = num_indices;
 259         SETfield(vgt_draw_initiator, DI_SRC_SEL_IMMEDIATE, SOURCE_SELECT_shift, SOURCE_SELECT_mask);
 260         SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask);
 261
 262         R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (num_indices + 1)));
 263         R600_OUT_BATCH(vgt_num_indices);
 264         R600_OUT_BATCH(vgt_draw_initiator);
 265
 266         for (i = start; i < end; i++) {
 267             R600_OUT_BATCH(i);
 268         }
 269         END_BATCH();
 270         COMMIT_BATCH();
 271
 272 }
 273
 274 void r700EmitState(GLcontext * ctx)
 275 {
 276         context_t *context = R700_CONTEXT(ctx);
 277
 278         rcommonEnsureCmdBufSpace(&context->radeon,
 279                                  context->radeon.hw.max_state_size, __FUNCTION__);
 280
 281         r700Start3D(context);
 282         r700SendSQConfig(context);
 283         r700SendFSState(context); // FIXME just a place holder for now
 284         r700SendPSState(context);
 285         r700SendVSState(context);
 286
 287         r700SendTextureState(context);
 288         r700SetupStreams(ctx);
 289
 290         r700SendUCPState(context);
 291         r700SendContextStates(context);
 292         r700SendViewportState(context, 0);
 293         r700SendRenderTargetState(context, 0);
 294         r700SendDepthTargetState(context);
 295
 296 }
 297
 298 static GLboolean r700RunRender(GLcontext * ctx,
 299                                            struct tnl_pipeline_stage *stage)
 300 {
 301     context_t *context = R700_CONTEXT(ctx);
 302     unsigned int i;
 303     TNLcontext *tnl = TNL_CONTEXT(ctx);
 304     struct vertex_buffer *vb = &tnl->vb;
 305
 306     r700UpdateShaders(ctx);
 307     r700SetScissor(context);
 308     r700SetupShaders(ctx);
 309
 310     r700SetRenderTarget(context, 0);
 311     r700SetDepthTarget(context);
 312
 313     r700EmitState(ctx);
 314
 315     /* richard test code */
 316     for (i = 0; i < vb->PrimitiveCount; i++) {
 317         GLuint prim = _tnl_translate_prim(&vb->Primitive[i]);
 318         GLuint start = vb->Primitive[i].start;
 319         GLuint end = vb->Primitive[i].start + vb->Primitive[i].count;
 320         r700RunRenderPrimitive(ctx, start, end, prim);
 321     }
 322
 323     /* Flush render op cached for last several quads. */
 324     r700WaitForIdleClean(context);
 325
 326     radeonReleaseArrays(ctx, ~0);
 327
 328     rcommonFlushCmdBuf( &context->radeon, __FUNCTION__ );
 329
 330     return GL_FALSE;
 331 }
 332
 333 static GLboolean r700RunNonTCLRender(GLcontext * ctx,
 334                                      struct tnl_pipeline_stage *stage) /* -------------------- */
 335 {
 336         GLboolean bRet = GL_TRUE;
 337
 338         return bRet;
 339 }
 340
 341 static GLboolean r700RunTCLRender(GLcontext * ctx,  /*----------------------*/
 342                                   struct tnl_pipeline_stage *stage)
 343 {
 344         GLboolean bRet = GL_FALSE;
 345
 346     /* TODO : sw fallback */
 347
 348     /**
 349     * Ensure all enabled and complete textures are uploaded along with any buffers being used.
 350     */
 351     if(!r600ValidateBuffers(ctx))
 352     {
 353         return GL_TRUE;
 354     }
 355
 356     bRet = r700RunRender(ctx, stage);
 357
 358     return bRet;
 359         //GL_FALSE will stop to do other pipe stage in _tnl_run_pipeline
 360     //The render here DOES finish the whole pipe, so GL_FALSE should be returned for success.
 361 }
 362
 363 const struct tnl_pipeline_stage _r700_render_stage = {
 364         "r700 Hardware Rasterization",
 365         NULL,
 366         NULL,
 367         NULL,
 368         NULL,
 369         r700RunNonTCLRender
 370 };
 371
 372 const struct tnl_pipeline_stage _r700_tcl_stage = {
 373         "r700 Hardware Transform, Clipping and Lighting",
 374         NULL,
 375         NULL,
 376         NULL,
 377         NULL,
 378         r700RunTCLRender
 379 };
 380
 381 const struct tnl_pipeline_stage *r700_pipeline[] =
 382 {
 383     &_r700_tcl_stage,
 384     &_tnl_vertex_transform_stage,
 385         &_tnl_normal_transform_stage,
 386         &_tnl_lighting_stage,
 387         &_tnl_fog_coordinate_stage,
 388         &_tnl_texgen_stage,
 389         &_tnl_texture_transform_stage,
 390         &_tnl_vertex_program_stage,
 391
 392     &_r700_render_stage,
 393     &_tnl_render_stage,
 394     0,
 395 };
 396
 397