2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 * CooperYuan <cooper.yuan@amd.com>, <cooperyuan@gmail.com>
28 #include "main/glheader.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/context.h"
35 #include "main/simple_list.h"
36 #include "main/api_arrayelt.h"
37 #include "swrast/swrast.h"
38 #include "swrast_setup/swrast_setup.h"
42 #include "tnl/t_vp_build.h"
43 #include "tnl/t_context.h"
44 #include "tnl/t_vertex.h"
45 #include "tnl/t_pipeline.h"
47 #include "r600_context.h"
48 #include "r600_cmdbuf.h"
52 #include "r700_vertprog.h"
53 #include "r700_fragprog.h"
54 #include "r700_state.h"
56 void r700WaitForIdle(context_t
*context
);
57 void r700WaitForIdleClean(context_t
*context
);
58 GLboolean
r700SendTextureState(context_t
*context
);
59 static unsigned int r700PrimitiveType(int prim
);
60 void r600UpdateTextureState(GLcontext
* ctx
);
61 GLboolean
r700SyncSurf(context_t
*context
,
62 struct radeon_bo
*pbo
,
64 uint32_t write_domain
,
67 void r700WaitForIdle(context_t
*context
)
69 BATCH_LOCALS(&context
->radeon
);
70 BEGIN_BATCH_NO_AUTOSTATE(3);
72 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG
, 1));
73 R600_OUT_BATCH(mmWAIT_UNTIL
- ASIC_CONFIG_BASE_INDEX
);
74 R600_OUT_BATCH(WAIT_3D_IDLE_bit
);
80 void r700WaitForIdleClean(context_t
*context
)
82 BATCH_LOCALS(&context
->radeon
);
83 BEGIN_BATCH_NO_AUTOSTATE(5);
85 R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE
, 0));
86 R600_OUT_BATCH(CACHE_FLUSH_AND_INV_EVENT
);
88 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG
, 1));
89 R600_OUT_BATCH(mmWAIT_UNTIL
- ASIC_CONFIG_BASE_INDEX
);
90 R600_OUT_BATCH(WAIT_3D_IDLE_bit
| WAIT_3D_IDLECLEAN_bit
);
96 void r700Start3D(context_t
*context
)
98 BATCH_LOCALS(&context
->radeon
);
99 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
)
101 BEGIN_BATCH_NO_AUTOSTATE(2);
102 R600_OUT_BATCH(CP_PACKET3(R600_IT_START_3D_CMDBUF
, 0));
107 BEGIN_BATCH_NO_AUTOSTATE(3);
108 R600_OUT_BATCH(CP_PACKET3(R600_IT_CONTEXT_CONTROL
, 1));
109 R600_OUT_BATCH(0x80000000);
110 R600_OUT_BATCH(0x80000000);
115 r700WaitForIdleClean(context
);
118 GLboolean
r700SyncSurf(context_t
*context
,
119 struct radeon_bo
*pbo
,
120 uint32_t read_domain
,
121 uint32_t write_domain
,
124 BATCH_LOCALS(&context
->radeon
);
125 uint32_t cp_coher_size
;
130 if (pbo
->size
== 0xffffffff)
131 cp_coher_size
= 0xffffffff;
133 cp_coher_size
= ((pbo
->size
+ 255) >> 8);
135 BEGIN_BATCH_NO_AUTOSTATE(5 + 2);
136 R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_SYNC
, 3));
137 R600_OUT_BATCH(sync_type
);
138 R600_OUT_BATCH(cp_coher_size
);
141 R600_OUT_BATCH_RELOC(0,
144 read_domain
, write_domain
, 0); // ???
152 static unsigned int r700PrimitiveType(int prim
)
154 switch (prim
& PRIM_MODE_MASK
)
157 return DI_PT_POINTLIST
;
160 return DI_PT_LINELIST
;
163 return DI_PT_LINESTRIP
;
166 return DI_PT_LINELOOP
;
169 return DI_PT_TRILIST
;
171 case GL_TRIANGLE_STRIP
:
172 return DI_PT_TRISTRIP
;
174 case GL_TRIANGLE_FAN
:
178 return DI_PT_QUADLIST
;
181 return DI_PT_QUADSTRIP
;
184 return DI_PT_POLYGON
;
193 static int r700NumVerts(int num_verts
, int prim
)
197 switch (prim
& PRIM_MODE_MASK
) {
202 verts_off
= num_verts
% 2;
206 verts_off
= num_verts
;
210 verts_off
= num_verts
;
213 verts_off
= num_verts
% 3;
215 case GL_TRIANGLE_STRIP
:
217 verts_off
= num_verts
;
219 case GL_TRIANGLE_FAN
:
221 verts_off
= num_verts
;
224 verts_off
= num_verts
% 4;
228 verts_off
= num_verts
;
230 verts_off
= num_verts
% 2;
234 verts_off
= num_verts
;
242 return num_verts
- verts_off
;
245 static void r700RunRenderPrimitive(GLcontext
* ctx
, int start
, int end
, int prim
)
247 context_t
*context
= R700_CONTEXT(ctx
);
248 BATCH_LOCALS(&context
->radeon
);
249 int type
, i
, total_emit
;
251 uint32_t vgt_draw_initiator
= 0;
252 uint32_t vgt_index_type
= 0;
253 uint32_t vgt_primitive_type
= 0;
254 uint32_t vgt_num_indices
= 0;
256 type
= r700PrimitiveType(prim
);
257 num_indices
= r700NumVerts(end
- start
, prim
);
259 if (type
< 0 || num_indices
<= 0)
262 total_emit
= 3 /* VGT_PRIMITIVE_TYPE */
263 + 2 /* VGT_INDEX_TYPE */
264 + 2 /* NUM_INSTANCES */
265 + num_indices
+ 3; /* DRAW_INDEX_IMMD */
267 BEGIN_BATCH_NO_AUTOSTATE(total_emit
);
269 SETfield(vgt_primitive_type
, type
,
270 VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift
, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask
);
271 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG
, 1));
272 R600_OUT_BATCH(mmVGT_PRIMITIVE_TYPE
- ASIC_CONFIG_BASE_INDEX
);
273 R600_OUT_BATCH(vgt_primitive_type
);
276 SETfield(vgt_index_type
, DI_INDEX_SIZE_32_BIT
, INDEX_TYPE_shift
, INDEX_TYPE_mask
);
277 R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE
, 0));
278 R600_OUT_BATCH(vgt_index_type
);
281 R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES
, 0));
285 vgt_num_indices
= num_indices
;
286 SETfield(vgt_draw_initiator
, DI_SRC_SEL_IMMEDIATE
, SOURCE_SELECT_shift
, SOURCE_SELECT_mask
);
287 SETfield(vgt_draw_initiator
, DI_MAJOR_MODE_0
, MAJOR_MODE_shift
, MAJOR_MODE_mask
);
289 R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD
, (num_indices
+ 1)));
290 R600_OUT_BATCH(vgt_num_indices
);
291 R600_OUT_BATCH(vgt_draw_initiator
);
293 for (i
= start
; i
< (start
+ num_indices
); i
++) {
301 /* FIXME: radom values fix with correct */
302 #define PRE_EMIT_STATE_BUFSZ 30
304 static GLuint
r700PredictRenderSize(GLcontext
* ctx
)
306 context_t
*context
= R700_CONTEXT(ctx
);
307 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
308 struct vertex_buffer
*vb
= &tnl
->vb
;
313 dwords
= PRE_EMIT_STATE_BUFSZ
;
314 for (i
= 0; i
< vb
->PrimitiveCount
; i
++)
315 dwords
+= vb
->Primitive
[i
].count
+ 10;
316 state_size
= radeonCountStateEmitSize(&context
->radeon
);
317 flushed
= rcommonEnsureCmdBufSpace(&context
->radeon
,
318 dwords
+ state_size
, __FUNCTION__
);
321 dwords
+= radeonCountStateEmitSize(&context
->radeon
);
323 dwords
+= state_size
;
325 if (RADEON_DEBUG
& DEBUG_PRIMS
)
326 fprintf(stderr
, "%s: total prediction size is %d.\n", __FUNCTION__
, dwords
);
330 static GLboolean
r700RunRender(GLcontext
* ctx
,
331 struct tnl_pipeline_stage
*stage
)
333 context_t
*context
= R700_CONTEXT(ctx
);
334 radeonContextPtr radeon
= &context
->radeon
;
335 unsigned int i
, id
= 0;
336 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
337 struct vertex_buffer
*vb
= &tnl
->vb
;
338 struct radeon_renderbuffer
*rrb
;
340 /* just an estimate, need to properly calculate this */
342 r700UpdateShaders(ctx
);
343 r700SetScissor(context
);
344 r700SetupVertexProgram(ctx
);
345 r700SetupFragmentProgram(ctx
);
346 r600UpdateTextureState(ctx
);
348 r700PredictRenderSize(ctx
);
349 r700SetupStreams(ctx
);
351 radeonEmitState(radeon
);
353 /* richard test code */
354 for (i
= 0; i
< vb
->PrimitiveCount
; i
++) {
355 GLuint prim
= _tnl_translate_prim(&vb
->Primitive
[i
]);
356 GLuint start
= vb
->Primitive
[i
].start
;
357 GLuint end
= vb
->Primitive
[i
].start
+ vb
->Primitive
[i
].count
;
358 r700RunRenderPrimitive(ctx
, start
, end
, prim
);
361 /* Flush render op cached for last several quads. */
362 r700WaitForIdleClean(context
);
364 rrb
= radeon_get_colorbuffer(&context
->radeon
);
365 if (!rrb
|| !rrb
->bo
)
366 r700SyncSurf(context
, rrb
->bo
, 0, RADEON_GEM_DOMAIN_VRAM
,
367 CB_ACTION_ENA_bit
| (1 << (id
+ 6)));
369 rrb
= radeon_get_depthbuffer(&context
->radeon
);
370 if (!rrb
|| !rrb
->bo
)
371 r700SyncSurf(context
, rrb
->bo
, 0, RADEON_GEM_DOMAIN_VRAM
,
372 DB_ACTION_ENA_bit
| DB_DEST_BASE_ENA_bit
);
374 radeonReleaseArrays(ctx
, ~0);
379 static GLboolean
r700RunNonTCLRender(GLcontext
* ctx
,
380 struct tnl_pipeline_stage
*stage
) /* -------------------- */
382 GLboolean bRet
= GL_TRUE
;
387 static GLboolean
r700RunTCLRender(GLcontext
* ctx
, /*----------------------*/
388 struct tnl_pipeline_stage
*stage
)
390 GLboolean bRet
= GL_FALSE
;
392 /* TODO : sw fallback */
395 * Ensure all enabled and complete textures are uploaded along with any buffers being used.
397 if(!r600ValidateBuffers(ctx
))
402 bRet
= r700RunRender(ctx
, stage
);
405 //GL_FALSE will stop to do other pipe stage in _tnl_run_pipeline
406 //The render here DOES finish the whole pipe, so GL_FALSE should be returned for success.
409 const struct tnl_pipeline_stage _r700_render_stage
= {
410 "r700 Hardware Rasterization",
418 const struct tnl_pipeline_stage _r700_tcl_stage
= {
419 "r700 Hardware Transform, Clipping and Lighting",
427 const struct tnl_pipeline_stage
*r700_pipeline
[] =
430 &_tnl_vertex_transform_stage
,
431 &_tnl_normal_transform_stage
,
432 &_tnl_lighting_stage
,
433 &_tnl_fog_coordinate_stage
,
435 &_tnl_texture_transform_stage
,
436 &_tnl_vertex_program_stage
,