src/mesa/drivers/dri/r600/r700_render.c

   1 /*
   2  * Copyright (C) 2008-2009  Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  */
  21
  22 /*
  23  * Authors:
  24  *   Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
  25  *   CooperYuan <cooper.yuan@amd.com>, <cooperyuan@gmail.com>
  26  */
  27
  28 #include "main/glheader.h"
  29 #include "main/state.h"
  30 #include "main/imports.h"
  31 #include "main/enums.h"
  32 #include "main/macros.h"
  33 #include "main/context.h"
  34 #include "main/dd.h"
  35 #include "main/simple_list.h"
  36 #include "main/api_arrayelt.h"
  37 #include "swrast/swrast.h"
  38 #include "swrast_setup/swrast_setup.h"
  39 #include "vbo/vbo.h"
  40
  41 #include "tnl/tnl.h"
  42 #include "tnl/t_vp_build.h"
  43 #include "tnl/t_context.h"
  44 #include "tnl/t_vertex.h"
  45 #include "tnl/t_pipeline.h"
  46
  47 #include "r600_context.h"
  48 #include "r600_cmdbuf.h"
  49
  50 #include "r600_tex.h"
  51
  52 #include "r700_vertprog.h"
  53 #include "r700_fragprog.h"
  54 #include "r700_state.h"
  55
  56 void r700WaitForIdle(context_t *context);
  57 void r700WaitForIdleClean(context_t *context);
  58 void r700Start3D(context_t *context);
  59 GLboolean r700SendTextureState(context_t *context);
  60 static unsigned int r700PrimitiveType(int prim);
  61 void r600UpdateTextureState(GLcontext * ctx);
  62 GLboolean r700SyncSurf(context_t *context,
  63                        struct radeon_bo *pbo,
  64                        uint32_t read_domain,
  65                        uint32_t write_domain,
  66                        uint32_t sync_type);
  67
  68 void r700WaitForIdle(context_t *context)
  69 {
  70     BATCH_LOCALS(&context->radeon);
  71     BEGIN_BATCH_NO_AUTOSTATE(3);
  72
  73     R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
  74     R600_OUT_BATCH(mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX);
  75     R600_OUT_BATCH(WAIT_3D_IDLE_bit);
  76
  77     END_BATCH();
  78     COMMIT_BATCH();
  79 }
  80
  81 void r700WaitForIdleClean(context_t *context)
  82 {
  83     BATCH_LOCALS(&context->radeon);
  84     BEGIN_BATCH_NO_AUTOSTATE(5);
  85
  86     R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
  87     R600_OUT_BATCH(CACHE_FLUSH_AND_INV_EVENT);
  88
  89     R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
  90     R600_OUT_BATCH(mmWAIT_UNTIL - ASIC_CONFIG_BASE_INDEX);
  91     R600_OUT_BATCH(WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
  92
  93     END_BATCH();
  94     COMMIT_BATCH();
  95 }
  96
  97 void r700Start3D(context_t *context)
  98 {
  99     BATCH_LOCALS(&context->radeon);
 100     if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
 101     {
 102         BEGIN_BATCH_NO_AUTOSTATE(2);
 103         R600_OUT_BATCH(CP_PACKET3(R600_IT_START_3D_CMDBUF, 0));
 104         R600_OUT_BATCH(0);
 105         END_BATCH();
 106     }
 107
 108     BEGIN_BATCH_NO_AUTOSTATE(3);
 109     R600_OUT_BATCH(CP_PACKET3(R600_IT_CONTEXT_CONTROL, 1));
 110     R600_OUT_BATCH(0x80000000);
 111     R600_OUT_BATCH(0x80000000);
 112     END_BATCH();
 113
 114     COMMIT_BATCH();
 115
 116     r700WaitForIdleClean(context);
 117 }
 118
 119 static GLboolean r700SetupShaders(GLcontext * ctx)
 120 {
 121     context_t *context = R700_CONTEXT(ctx);
 122
 123     R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
 124
 125     GLuint exportCount;
 126
 127     r700->ps.SQ_PGM_RESOURCES_PS.u32All = 0;
 128     r700->vs.SQ_PGM_RESOURCES_VS.u32All = 0;
 129
 130     SETbit(r700->ps.SQ_PGM_RESOURCES_PS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit);
 131     SETbit(r700->vs.SQ_PGM_RESOURCES_VS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit);
 132
 133     r700SetupVertexProgram(ctx);
 134
 135     r700SetupFragmentProgram(ctx);
 136
 137     exportCount = (r700->ps.SQ_PGM_EXPORTS_PS.u32All & EXPORT_MODE_mask) / (1 << EXPORT_MODE_shift);
 138     r700->CB_SHADER_CONTROL.u32All = (1 << exportCount) - 1;
 139
 140     r600UpdateTextureState(ctx);
 141
 142     r700SendFSState(context); // FIXME just a place holder for now
 143     r700SendPSState(context);
 144     r700SendVSState(context);
 145
 146     r700SendTextureState(context);
 147     r700SetupStreams(ctx);
 148
 149     return GL_TRUE;
 150 }
 151
 152 GLboolean r700SyncSurf(context_t *context,
 153                        struct radeon_bo *pbo,
 154                        uint32_t read_domain,
 155                        uint32_t write_domain,
 156                        uint32_t sync_type)
 157 {
 158     BATCH_LOCALS(&context->radeon);
 159     uint32_t cp_coher_size;
 160
 161     if (!pbo)
 162             return GL_FALSE;
 163
 164     if (pbo->size == 0xffffffff)
 165             cp_coher_size = 0xffffffff;
 166     else
 167             cp_coher_size = ((pbo->size + 255) >> 8);
 168
 169     BEGIN_BATCH_NO_AUTOSTATE(5);
 170     R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_SYNC, 3));
 171     R600_OUT_BATCH(sync_type);
 172     R600_OUT_BATCH(cp_coher_size);
 173     R600_OUT_BATCH_RELOC(0,
 174                          pbo,
 175                          0,
 176                          read_domain, write_domain, 0); // ???
 177     R600_OUT_BATCH(10);
 178
 179     END_BATCH();
 180     COMMIT_BATCH();
 181
 182     return GL_TRUE;
 183 }
 184
 185 static unsigned int r700PrimitiveType(int prim)
 186 {
 187     switch (prim & PRIM_MODE_MASK)
 188     {
 189     case GL_POINTS:
 190         return DI_PT_POINTLIST;
 191         break;
 192     case GL_LINES:
 193         return DI_PT_LINELIST;
 194         break;
 195     case GL_LINE_STRIP:
 196         return DI_PT_LINESTRIP;
 197         break;
 198     case GL_LINE_LOOP:
 199         return DI_PT_LINELOOP;
 200         break;
 201     case GL_TRIANGLES:
 202         return DI_PT_TRILIST;
 203         break;
 204     case GL_TRIANGLE_STRIP:
 205         return DI_PT_TRISTRIP;
 206         break;
 207     case GL_TRIANGLE_FAN:
 208         return DI_PT_TRIFAN;
 209         break;
 210     case GL_QUADS:
 211         return DI_PT_QUADLIST;
 212         break;
 213     case GL_QUAD_STRIP:
 214         return DI_PT_QUADSTRIP;
 215         break;
 216     case GL_POLYGON:
 217         return DI_PT_POLYGON;
 218         break;
 219     default:
 220         assert(0);
 221         return -1;
 222         break;
 223     }
 224 }
 225
 226 static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim)
 227 {
 228         context_t *context = R700_CONTEXT(ctx);
 229         BATCH_LOCALS(&context->radeon);
 230         int type, i, total_emit;
 231         int num_indices = end - start;
 232         uint32_t vgt_draw_initiator = 0;
 233         uint32_t vgt_index_type     = 0;
 234         uint32_t vgt_primitive_type = 0;
 235         uint32_t vgt_num_indices    = 0;
 236
 237         type = r700PrimitiveType(prim);
 238
 239         if (type < 0 || num_indices <= 0)
 240                 return;
 241
 242         total_emit =   3 /* VGT_PRIMITIVE_TYPE */
 243                      + 2 /* VGT_INDEX_TYPE */
 244                      + 2 /* NUM_INSTANCES */
 245                      + num_indices + 3; /* DRAW_INDEX_IMMD */
 246
 247         BEGIN_BATCH_NO_AUTOSTATE(total_emit);
 248         // prim
 249         SETfield(vgt_primitive_type, type,
 250                  VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask);
 251         R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
 252         R600_OUT_BATCH(mmVGT_PRIMITIVE_TYPE - ASIC_CONFIG_BASE_INDEX);
 253         R600_OUT_BATCH(vgt_primitive_type);
 254
 255         // index type
 256         SETfield(vgt_index_type, DI_INDEX_SIZE_32_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask);
 257         R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
 258         R600_OUT_BATCH(vgt_index_type);
 259
 260         // num instances
 261         R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
 262         R600_OUT_BATCH(1);
 263
 264         // draw packet
 265         vgt_num_indices = num_indices;
 266         SETfield(vgt_draw_initiator, DI_SRC_SEL_IMMEDIATE, SOURCE_SELECT_shift, SOURCE_SELECT_mask);
 267         SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask);
 268
 269         R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (num_indices + 1)));
 270         R600_OUT_BATCH(vgt_num_indices);
 271         R600_OUT_BATCH(vgt_draw_initiator);
 272
 273         for (i = start; i < end; i++) {
 274             R600_OUT_BATCH(i);
 275         }
 276         END_BATCH();
 277         COMMIT_BATCH();
 278
 279 }
 280
 281 void r700EmitState(GLcontext * ctx)
 282 {
 283         context_t *context = R700_CONTEXT(ctx);
 284         radeonContextPtr radeon = &context->radeon;
 285
 286         if (radeon->cmdbuf.cs->cdw && !radeon->hw.is_dirty && !radeon->hw.all_dirty)
 287                 return;
 288
 289         rcommonEnsureCmdBufSpace(&context->radeon,
 290                                  context->radeon.hw.max_state_size, __FUNCTION__);
 291
 292         r700SendSQConfig(context);
 293
 294         r700SendUCPState(context);
 295         r700SendContextStates(context);
 296         r700SendViewportState(context, 0);
 297         r700SendRenderTargetState(context, 0);
 298         r700SendDepthTargetState(context);
 299
 300 }
 301
 302 static GLboolean r700RunRender(GLcontext * ctx,
 303                                            struct tnl_pipeline_stage *stage)
 304 {
 305     context_t *context = R700_CONTEXT(ctx);
 306     unsigned int i;
 307     TNLcontext *tnl = TNL_CONTEXT(ctx);
 308     struct vertex_buffer *vb = &tnl->vb;
 309
 310     r700Start3D(context);
 311
 312     r700UpdateShaders(ctx);
 313     r700SetScissor(context);
 314     r700SetupShaders(ctx);
 315
 316     r700EmitState(ctx);
 317
 318     /* richard test code */
 319     for (i = 0; i < vb->PrimitiveCount; i++) {
 320         GLuint prim = _tnl_translate_prim(&vb->Primitive[i]);
 321         GLuint start = vb->Primitive[i].start;
 322         GLuint end = vb->Primitive[i].start + vb->Primitive[i].count;
 323         r700RunRenderPrimitive(ctx, start, end, prim);
 324     }
 325
 326     /* Flush render op cached for last several quads. */
 327     r700WaitForIdleClean(context);
 328
 329     radeonReleaseArrays(ctx, ~0);
 330
 331     return GL_FALSE;
 332 }
 333
 334 static GLboolean r700RunNonTCLRender(GLcontext * ctx,
 335                                      struct tnl_pipeline_stage *stage) /* -------------------- */
 336 {
 337         GLboolean bRet = GL_TRUE;
 338
 339         return bRet;
 340 }
 341
 342 static GLboolean r700RunTCLRender(GLcontext * ctx,  /*----------------------*/
 343                                   struct tnl_pipeline_stage *stage)
 344 {
 345         GLboolean bRet = GL_FALSE;
 346
 347     /* TODO : sw fallback */
 348
 349     /**
 350     * Ensure all enabled and complete textures are uploaded along with any buffers being used.
 351     */
 352     if(!r600ValidateBuffers(ctx))
 353     {
 354         return GL_TRUE;
 355     }
 356
 357     bRet = r700RunRender(ctx, stage);
 358
 359     return bRet;
 360         //GL_FALSE will stop to do other pipe stage in _tnl_run_pipeline
 361     //The render here DOES finish the whole pipe, so GL_FALSE should be returned for success.
 362 }
 363
 364 const struct tnl_pipeline_stage _r700_render_stage = {
 365         "r700 Hardware Rasterization",
 366         NULL,
 367         NULL,
 368         NULL,
 369         NULL,
 370         r700RunNonTCLRender
 371 };
 372
 373 const struct tnl_pipeline_stage _r700_tcl_stage = {
 374         "r700 Hardware Transform, Clipping and Lighting",
 375         NULL,
 376         NULL,
 377         NULL,
 378         NULL,
 379         r700RunTCLRender
 380 };
 381
 382 const struct tnl_pipeline_stage *r700_pipeline[] =
 383 {
 384     &_r700_tcl_stage,
 385     &_tnl_vertex_transform_stage,
 386         &_tnl_normal_transform_stage,
 387         &_tnl_lighting_stage,
 388         &_tnl_fog_coordinate_stage,
 389         &_tnl_texgen_stage,
 390         &_tnl_texture_transform_stage,
 391         &_tnl_vertex_program_stage,
 392
 393     &_r700_render_stage,
 394     &_tnl_render_stage,
 395     0,
 396 };
 397
 398