2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 * CooperYuan <cooper.yuan@amd.com>, <cooperyuan@gmail.com>
28 #include "main/glheader.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/context.h"
35 #include "main/simple_list.h"
36 #include "main/api_arrayelt.h"
37 #include "swrast/swrast.h"
38 #include "swrast_setup/swrast_setup.h"
42 #include "tnl/t_vp_build.h"
43 #include "tnl/t_context.h"
44 #include "tnl/t_vertex.h"
45 #include "tnl/t_pipeline.h"
47 #include "r600_context.h"
48 #include "r600_cmdbuf.h"
52 #include "r700_vertprog.h"
53 #include "r700_fragprog.h"
54 #include "r700_state.h"
56 #include "radeon_common_context.h"
58 void r700WaitForIdle(context_t
*context
);
59 void r700WaitForIdleClean(context_t
*context
);
60 GLboolean
r700SendTextureState(context_t
*context
);
61 static unsigned int r700PrimitiveType(int prim
);
62 void r600UpdateTextureState(GLcontext
* ctx
);
63 GLboolean
r700SyncSurf(context_t
*context
,
64 struct radeon_bo
*pbo
,
66 uint32_t write_domain
,
69 void r700WaitForIdle(context_t
*context
)
71 BATCH_LOCALS(&context
->radeon
);
72 radeon_print(RADEON_RENDER
| RADEON_STATE
, RADEON_TRACE
, "%s\n", __func__
);
73 BEGIN_BATCH_NO_AUTOSTATE(3);
75 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG
, 1));
76 R600_OUT_BATCH(mmWAIT_UNTIL
- ASIC_CONFIG_BASE_INDEX
);
77 R600_OUT_BATCH(WAIT_3D_IDLE_bit
);
83 void r700WaitForIdleClean(context_t
*context
)
85 BATCH_LOCALS(&context
->radeon
);
86 radeon_print(RADEON_RENDER
| RADEON_STATE
, RADEON_TRACE
, "%s\n", __func__
);
87 BEGIN_BATCH_NO_AUTOSTATE(5);
89 R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE
, 0));
90 R600_OUT_BATCH(CACHE_FLUSH_AND_INV_EVENT
);
92 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG
, 1));
93 R600_OUT_BATCH(mmWAIT_UNTIL
- ASIC_CONFIG_BASE_INDEX
);
94 R600_OUT_BATCH(WAIT_3D_IDLE_bit
| WAIT_3D_IDLECLEAN_bit
);
100 void r700Start3D(context_t
*context
)
102 BATCH_LOCALS(&context
->radeon
);
103 radeon_print(RADEON_RENDER
| RADEON_STATE
, RADEON_TRACE
, "%s\n", __func__
);
104 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
)
106 BEGIN_BATCH_NO_AUTOSTATE(2);
107 R600_OUT_BATCH(CP_PACKET3(R600_IT_START_3D_CMDBUF
, 0));
112 BEGIN_BATCH_NO_AUTOSTATE(3);
113 R600_OUT_BATCH(CP_PACKET3(R600_IT_CONTEXT_CONTROL
, 1));
114 R600_OUT_BATCH(0x80000000);
115 R600_OUT_BATCH(0x80000000);
120 r700WaitForIdleClean(context
);
123 GLboolean
r700SyncSurf(context_t
*context
,
124 struct radeon_bo
*pbo
,
125 uint32_t read_domain
,
126 uint32_t write_domain
,
129 BATCH_LOCALS(&context
->radeon
);
130 radeon_print(RADEON_RENDER
| RADEON_STATE
, RADEON_TRACE
, "%s\n", __func__
);
131 uint32_t cp_coher_size
;
136 if (pbo
->size
== 0xffffffff)
137 cp_coher_size
= 0xffffffff;
139 cp_coher_size
= ((pbo
->size
+ 255) >> 8);
141 BEGIN_BATCH_NO_AUTOSTATE(5 + 2);
142 R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_SYNC
, 3));
143 R600_OUT_BATCH(sync_type
);
144 R600_OUT_BATCH(cp_coher_size
);
147 R600_OUT_BATCH_RELOC(0,
150 read_domain
, write_domain
, 0);
157 static unsigned int r700PrimitiveType(int prim
)
159 switch (prim
& PRIM_MODE_MASK
)
162 return DI_PT_POINTLIST
;
165 return DI_PT_LINELIST
;
168 return DI_PT_LINESTRIP
;
171 return DI_PT_LINELOOP
;
174 return DI_PT_TRILIST
;
176 case GL_TRIANGLE_STRIP
:
177 return DI_PT_TRISTRIP
;
179 case GL_TRIANGLE_FAN
:
183 return DI_PT_QUADLIST
;
186 return DI_PT_QUADSTRIP
;
189 return DI_PT_POLYGON
;
198 static int r700NumVerts(int num_verts
, int prim
)
202 switch (prim
& PRIM_MODE_MASK
) {
207 verts_off
= num_verts
% 2;
211 verts_off
= num_verts
;
215 verts_off
= num_verts
;
218 verts_off
= num_verts
% 3;
220 case GL_TRIANGLE_STRIP
:
222 verts_off
= num_verts
;
224 case GL_TRIANGLE_FAN
:
226 verts_off
= num_verts
;
229 verts_off
= num_verts
% 4;
233 verts_off
= num_verts
;
235 verts_off
= num_verts
% 2;
239 verts_off
= num_verts
;
247 return num_verts
- verts_off
;
250 static void r700RunRenderPrimitive(GLcontext
* ctx
, int start
, int end
, int prim
)
252 context_t
*context
= R700_CONTEXT(ctx
);
253 BATCH_LOCALS(&context
->radeon
);
254 int type
, i
, total_emit
;
256 uint32_t vgt_draw_initiator
= 0;
257 uint32_t vgt_index_type
= 0;
258 uint32_t vgt_primitive_type
= 0;
259 uint32_t vgt_num_indices
= 0;
260 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
261 struct vertex_buffer
*vb
= &tnl
->vb
;
263 type
= r700PrimitiveType(prim
);
264 num_indices
= r700NumVerts(end
- start
, prim
);
266 radeon_print(RADEON_RENDER
, RADEON_TRACE
,
267 "%s type %x num_indices %d\n",
268 __func__
, type
, num_indices
);
270 if (type
< 0 || num_indices
<= 0)
273 total_emit
= 3 /* VGT_PRIMITIVE_TYPE */
274 + 2 /* VGT_INDEX_TYPE */
275 + 2 /* NUM_INSTANCES */
276 + num_indices
+ 3; /* DRAW_INDEX_IMMD */
278 BEGIN_BATCH_NO_AUTOSTATE(total_emit
);
280 SETfield(vgt_primitive_type
, type
,
281 VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift
, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask
);
282 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG
, 1));
283 R600_OUT_BATCH(mmVGT_PRIMITIVE_TYPE
- ASIC_CONFIG_BASE_INDEX
);
284 R600_OUT_BATCH(vgt_primitive_type
);
287 SETfield(vgt_index_type
, DI_INDEX_SIZE_32_BIT
, INDEX_TYPE_shift
, INDEX_TYPE_mask
);
288 R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE
, 0));
289 R600_OUT_BATCH(vgt_index_type
);
292 R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES
, 0));
296 vgt_num_indices
= num_indices
;
297 SETfield(vgt_draw_initiator
, DI_SRC_SEL_IMMEDIATE
, SOURCE_SELECT_shift
, SOURCE_SELECT_mask
);
298 SETfield(vgt_draw_initiator
, DI_MAJOR_MODE_0
, MAJOR_MODE_shift
, MAJOR_MODE_mask
);
300 R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD
, (num_indices
+ 1)));
301 R600_OUT_BATCH(vgt_num_indices
);
302 R600_OUT_BATCH(vgt_draw_initiator
);
304 for (i
= start
; i
< (start
+ num_indices
); i
++) {
306 R600_OUT_BATCH(vb
->Elts
[i
]);
315 /* start 3d, idle, cb/db flush */
316 #define PRE_EMIT_STATE_BUFSZ 10 + 5 + 14
318 static GLuint
r700PredictRenderSize(GLcontext
* ctx
)
320 context_t
*context
= R700_CONTEXT(ctx
);
321 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
322 struct r700_vertex_program
*vpc
323 = (struct r700_vertex_program
*)ctx
->VertexProgram
._Current
;
324 struct vertex_buffer
*vb
= &tnl
->vb
;
328 /* pre calculate aos count so state prediction works */
329 context
->radeon
.tcl
.aos_count
= _mesa_bitcount(vpc
->mesa_program
.Base
.InputsRead
);
331 dwords
= PRE_EMIT_STATE_BUFSZ
;
332 for (i
= 0; i
< vb
->PrimitiveCount
; i
++)
333 dwords
+= vb
->Primitive
[i
].count
+ 10;
334 state_size
= radeonCountStateEmitSize(&context
->radeon
);
335 flushed
= rcommonEnsureCmdBufSpace(&context
->radeon
,
336 dwords
+ state_size
, __FUNCTION__
);
339 dwords
+= radeonCountStateEmitSize(&context
->radeon
);
341 dwords
+= state_size
;
343 radeon_print(RADEON_RENDER
, RADEON_VERBOSE
,
344 "%s: total prediction size is %d.\n", __FUNCTION__
, dwords
);
348 static GLboolean
r700RunRender(GLcontext
* ctx
,
349 struct tnl_pipeline_stage
*stage
)
351 context_t
*context
= R700_CONTEXT(ctx
);
352 radeonContextPtr radeon
= &context
->radeon
;
353 unsigned int i
, id
= 0;
354 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
355 struct vertex_buffer
*vb
= &tnl
->vb
;
356 struct radeon_renderbuffer
*rrb
;
358 radeon_print(RADEON_RENDER
, RADEON_NORMAL
, "%s: cs begin at %d\n",
359 __func__
, context
->radeon
.cmdbuf
.cs
->cdw
);
361 /* always emit CB base to prevent
362 * lock ups on some chips.
364 R600_STATECHANGE(context
, cb_target
);
365 /* mark vtx as dirty since it changes per-draw */
366 R600_STATECHANGE(context
, vtx
);
368 r700UpdateShaders(ctx
);
369 r700SetScissor(context
);
370 r700SetupVertexProgram(ctx
);
371 r700SetupFragmentProgram(ctx
);
372 r600UpdateTextureState(ctx
);
374 GLuint emit_end
= r700PredictRenderSize(ctx
)
375 + context
->radeon
.cmdbuf
.cs
->cdw
;
376 r700SetupStreams(ctx
);
378 radeonEmitState(radeon
);
380 radeon_debug_add_indent();
381 /* richard test code */
382 for (i
= 0; i
< vb
->PrimitiveCount
; i
++) {
383 GLuint prim
= _tnl_translate_prim(&vb
->Primitive
[i
]);
384 GLuint start
= vb
->Primitive
[i
].start
;
385 GLuint end
= vb
->Primitive
[i
].start
+ vb
->Primitive
[i
].count
;
386 r700RunRenderPrimitive(ctx
, start
, end
, prim
);
388 radeon_debug_remove_indent();
390 /* Flush render op cached for last several quads. */
391 r700WaitForIdleClean(context
);
393 rrb
= radeon_get_colorbuffer(&context
->radeon
);
395 r700SyncSurf(context
, rrb
->bo
, 0, RADEON_GEM_DOMAIN_VRAM
,
396 CB_ACTION_ENA_bit
| (1 << (id
+ 6)));
398 rrb
= radeon_get_depthbuffer(&context
->radeon
);
400 r700SyncSurf(context
, rrb
->bo
, 0, RADEON_GEM_DOMAIN_VRAM
,
401 DB_ACTION_ENA_bit
| DB_DEST_BASE_ENA_bit
);
403 radeonReleaseArrays(ctx
, ~0);
405 radeon_print(RADEON_RENDER
, RADEON_TRACE
, "%s: cs end at %d\n",
406 __func__
, context
->radeon
.cmdbuf
.cs
->cdw
);
408 if ( emit_end
< context
->radeon
.cmdbuf
.cs
->cdw
)
409 WARN_ONCE("Rendering was %d commands larger than predicted size."
410 " We might overflow command buffer.\n", context
->radeon
.cmdbuf
.cs
->cdw
- emit_end
);
415 static GLboolean
r700RunNonTCLRender(GLcontext
* ctx
,
416 struct tnl_pipeline_stage
*stage
) /* -------------------- */
418 GLboolean bRet
= GL_TRUE
;
423 static GLboolean
r700RunTCLRender(GLcontext
* ctx
, /*----------------------*/
424 struct tnl_pipeline_stage
*stage
)
426 GLboolean bRet
= GL_FALSE
;
428 /* TODO : sw fallback */
431 * Ensure all enabled and complete textures are uploaded along with any buffers being used.
433 if(!r600ValidateBuffers(ctx
))
438 bRet
= r700RunRender(ctx
, stage
);
441 //GL_FALSE will stop to do other pipe stage in _tnl_run_pipeline
442 //The render here DOES finish the whole pipe, so GL_FALSE should be returned for success.
445 const struct tnl_pipeline_stage _r700_render_stage
= {
446 "r700 Hardware Rasterization",
454 const struct tnl_pipeline_stage _r700_tcl_stage
= {
455 "r700 Hardware Transform, Clipping and Lighting",
463 const struct tnl_pipeline_stage
*r700_pipeline
[] =
466 &_tnl_vertex_transform_stage
,
467 &_tnl_normal_transform_stage
,
468 &_tnl_lighting_stage
,
469 &_tnl_fog_coordinate_stage
,
471 &_tnl_texture_transform_stage
,
472 &_tnl_vertex_program_stage
,