Merge branch 'glsl-to-tgsi'
[mesa.git] / src / mesa / drivers / dri / r600 / r700_shaderinst.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27
28 #include "main/mtypes.h"
29
30 #include "radeon_debug.h"
31 #include "r700_shaderinst.h"
32
33 void Init_R700ControlFlowGenericClause(R700ControlFlowGenericClause* pInst)
34 {
35 pInst->m_Word0.val = 0x00000000;
36 pInst->m_Word1.val = 0x00000000;
37
38 pInst->m_pLinkedVTXInstruction = 0;
39 pInst->m_pLinkedTEXInstruction = 0;
40
41 pInst->useCount = 0;
42
43 pInst->m_ShaderInstType = SIT_CF_GENERIC;
44 }
45
46 void Init_R700ControlFlowALUClause(R700ControlFlowALUClause* pInst)
47 {
48 pInst->m_Word0.val = 0x00000000;
49 pInst->m_Word1.val = 0x00000000;
50
51 pInst->m_pLinkedALUInstruction = 0;
52
53 pInst->useCount = 0;
54
55 pInst->m_ShaderInstType = SIT_CF_ALU;
56 }
57
58 void Init_R700ControlFlowSXClause(R700ControlFlowSXClause* pInst)
59 {
60 pInst->m_Word0.val = 0x00000000;
61 pInst->m_Word1.val = 0x00000000;
62 pInst->m_Word1_SWIZ.val = 0x00000000;
63
64 pInst->useCount = 0;
65
66 pInst->m_ShaderInstType = SIT_CF_ALL_EXP_SX;
67 }
68
69 void Init_R700ControlFlowSMXClause(R700ControlFlowSMXClause* pInst)
70 {
71 pInst->m_Word0.val = 0x00000000;
72 pInst->m_Word1.val = 0x00000000;
73 pInst->m_Word1_BUF.val = 0x00000000;
74
75 pInst->useCount = 0;
76
77 pInst->m_ShaderInstType = SIT_CF_ALL_EXP_SMX;
78 }
79
80 void Init_R700ALUInstruction(R700ALUInstruction* pInst)
81 {
82 pInst->m_Word0.val = 0x00000000;
83 pInst->m_Word1.val = 0x00000000;
84 pInst->m_Word1_OP2.val = 0x00000000;
85 pInst->m_Word1_OP3.val = 0x00000000;
86
87 pInst->m_pLinkedALUClause = 0;
88
89 pInst->useCount = 0;
90
91 pInst->m_ShaderInstType = SIT_ALU;
92 }
93
94 void Init_R700ALUInstructionHalfLiteral(R700ALUInstructionHalfLiteral* pInst, GLfloat x, GLfloat y)
95 {
96 pInst->m_Word0.val = 0x00000000;
97 pInst->m_Word1.val = 0x00000000;
98 pInst->m_Word1_OP2.val = 0x00000000;
99 pInst->m_Word1_OP3.val = 0x00000000;
100
101 pInst->m_pLinkedALUClause = 0;
102
103 pInst->m_fLiteralX = x;
104 pInst->m_fLiteralY = y;
105
106 pInst->useCount = 0;
107
108 pInst->m_ShaderInstType = SIT_ALU_HALF_LIT;
109 }
110
111 void Init_R700ALUInstructionFullLiteral(R700ALUInstructionFullLiteral* pInst, GLfloat x, GLfloat y, GLfloat z, GLfloat w)
112 {
113 pInst->m_Word0.val = 0x00000000;
114 pInst->m_Word1.val = 0x00000000;
115 pInst->m_Word1_OP2.val = 0x00000000;
116 pInst->m_Word1_OP3.val = 0x00000000;
117
118 pInst->m_pLinkedALUClause = 0;
119
120 pInst->m_fLiteralX = x;
121 pInst->m_fLiteralY = y;
122 pInst->m_fLiteralZ = z;
123 pInst->m_fLiteralW = w;
124
125 pInst->useCount = 0;
126
127 pInst->m_ShaderInstType = SIT_ALU_FALL_LIT;
128 }
129
130 void Init_R700TextureInstruction(R700TextureInstruction* pInst)
131 {
132 pInst->m_Word0.val = 0x00000000;
133 pInst->m_Word1.val = 0x00000000;
134 pInst->m_Word2.val = 0x00000000;
135
136 pInst->m_pLinkedGenericClause = 0;
137
138 pInst->useCount = 0;
139
140 pInst->m_ShaderInstType = SIT_TEX;
141 }
142
143 void Init_R700VertexSemanticFetch(R700VertexSemanticFetch* pInst)
144 {
145 pInst->m_Word0.val = 0x00000000;
146 pInst->m_Word1.val = 0x00000000;
147 pInst->m_Word1_SEM.val = 0x00000000;
148 pInst->m_Word2.val = 0x00000000;
149
150 pInst->m_pLinkedGenericClause = 0;
151
152 pInst->useCount = 0;
153
154 pInst->m_ShaderInstType = SIT_VTX_SEM;
155 }
156
157 void Init_R700VertexGenericFetch(R700VertexGenericFetch* pInst)
158 {
159 pInst->m_Word0.val = 0x00000000;
160 pInst->m_Word1.val = 0x00000000;
161 pInst->m_Word1_GPR.val = 0x00000000;
162 pInst->m_Word2.val = 0x00000000;
163
164 pInst->m_pLinkedGenericClause = 0;
165
166 pInst->useCount = 0;
167
168 pInst->m_ShaderInstType = SIT_VTX_GENERIC;
169 }
170
171 unsigned int GetInstructionSize(ShaderInstType instType)
172 {
173 switch(instType)
174 {
175 case SIT_ALU_HALF_LIT:
176 case SIT_TEX:
177 case SIT_VTX:
178 case SIT_VTX_GENERIC:
179 case SIT_VTX_SEM:
180 return 4;
181 case SIT_ALU_FALL_LIT:
182 return 6;
183 default:
184 break;
185 }
186
187 return 2;
188 }
189
190 unsigned int GetCFMaxInstructions(ShaderInstType instType)
191 {
192 switch (instType)
193 {
194 case SIT_CF_ALL_EXP:
195 case SIT_CF_ALL_EXP_SX:
196 case SIT_CF_ALL_EXP_SMX:
197 return 0x10;
198 case SIT_CF_GENERIC:
199 return 0x8; //For tex and vtx
200 case SIT_CF_ALU:
201 return 0x80;
202 default:
203 break;
204 }
205 return 0x10;
206 }
207
208 GLboolean LinkVertexInstruction(R700ControlFlowGenericClause *pCFGeneric,
209 R700VertexInstruction *pVTXInstruction)
210 {
211 if (pCFGeneric->m_pLinkedTEXInstruction != 0)
212 {
213 radeon_error("This instruction is already linked to a texture instruction.\n");
214 return GL_FALSE;
215 }
216
217 pCFGeneric->m_pLinkedVTXInstruction = pVTXInstruction;
218 pVTXInstruction->m_pLinkedGenericClause = pCFGeneric;
219
220 return GL_TRUE;
221 }
222
223
224