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1d6d398f63ee8a922ce157df6ebf4c4695ca0610
[mesa.git] / src / mesa / drivers / dri / r600 / r700_state.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/context.h"
34 #include "main/dd.h"
35 #include "main/simple_list.h"
36
37 #include "tnl/tnl.h"
38 #include "tnl/t_pipeline.h"
39 #include "tnl/t_vp_build.h"
40 #include "swrast/swrast.h"
41 #include "swrast_setup/swrast_setup.h"
42 #include "main/api_arrayelt.h"
43 #include "main/state.h"
44 #include "main/framebuffer.h"
45
46 #include "shader/prog_parameter.h"
47 #include "shader/prog_statevars.h"
48 #include "vbo/vbo.h"
49 #include "main/texformat.h"
50
51 #include "r600_context.h"
52
53 #include "r700_state.h"
54
55 #include "r700_fragprog.h"
56 #include "r700_vertprog.h"
57
58
59 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state);
60
61 void r700SetDefaultStates(context_t *context) //--------------------
62 {
63
64 }
65
66 void r700UpdateShaders (GLcontext * ctx) //----------------------------------
67 {
68 context_t *context = R700_CONTEXT(ctx);
69
70 GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
71 GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
72
73 struct r700_vertex_program *vp;
74 int i;
75
76 if (context->radeon.NewGLState)
77 {
78 context->radeon.NewGLState = 0;
79
80 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++)
81 {
82 /* mat states from state var not array for sw */
83 dummy_attrib[i].stride = 0;
84
85 temp_attrib[i] = TNL_CONTEXT(ctx)->vb.AttribPtr[i];
86 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = &(dummy_attrib[i]);
87 }
88
89 _tnl_UpdateFixedFunctionProgram(ctx);
90
91 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++)
92 {
93 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = temp_attrib[i];
94 }
95
96 r700SelectVertexShader(ctx);
97 vp = (struct r700_vertex_program *)ctx->VertexProgram._Current;
98
99 if (vp->translated == GL_FALSE)
100 {
101 // TODO
102 //fprintf(stderr, "Failing back to sw-tcl\n");
103 //hw_tcl_on = future_hw_tcl_on = 0;
104 //r300ResetHwState(rmesa);
105 //
106 r700UpdateStateParameters(ctx, _NEW_PROGRAM);
107 return;
108 }
109 }
110
111 r700UpdateStateParameters(ctx, _NEW_PROGRAM);
112 }
113
114 /*
115 * To correctly position primitives:
116 */
117 void r700UpdateViewportOffset(GLcontext * ctx) //------------------
118 {
119
120 //radeonUpdateScissor(ctx);
121
122 return;
123 }
124
125 /**
126 * Tell the card where to render (offset, pitch).
127 * Effected by glDrawBuffer, etc
128 */
129 void r700UpdateDrawBuffer(GLcontext * ctx) /* TODO */ //---------------------
130 {
131 #if 0 /* to be enabled */
132 context_t *context = R700_CONTEXT(ctx);
133
134 switch (ctx->DrawBuffer->_ColorDrawBufferIndexes[0])
135 {
136 case BUFFER_FRONT_LEFT:
137 context->target.rt = context->screen->frontBuffer;
138 break;
139 case BUFFER_BACK_LEFT:
140 context->target.rt = context->screen->backBuffer;
141 break;
142 default:
143 memset (&context->target.rt, sizeof(context->target.rt), 0);
144 }
145 #endif /* to be enabled */
146 }
147
148 static void r700FetchStateParameter(GLcontext * ctx,
149 const gl_state_index state[STATE_LENGTH],
150 GLfloat * value)
151 {
152 context_t *context = R700_CONTEXT(ctx);
153
154 /* TODO */
155 }
156
157 void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state) //--------------------
158 {
159 struct r700_fragment_program *fp;
160 struct gl_program_parameter_list *paramList;
161 GLuint i;
162
163 if (!(new_state & (_NEW_BUFFERS | _NEW_PROGRAM)))
164 return;
165
166 fp = (struct r700_fragment_program *)ctx->FragmentProgram._Current;
167 if (!fp)
168 {
169 return;
170 }
171
172 paramList = fp->mesa_program.Base.Parameters;
173
174 if (!paramList)
175 {
176 return;
177 }
178
179 for (i = 0; i < paramList->NumParameters; i++)
180 {
181 if (paramList->Parameters[i].Type == PROGRAM_STATE_VAR)
182 {
183 r700FetchStateParameter(ctx,
184 paramList->Parameters[i].
185 StateIndexes,
186 paramList->ParameterValues[i]);
187 }
188 }
189 }
190
191 /**
192 * Called by Mesa after an internal state update.
193 */
194 static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //-------------------
195 {
196 context_t *context = R700_CONTEXT(ctx);
197
198 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
199
200 _swrast_InvalidateState(ctx, new_state);
201 _swsetup_InvalidateState(ctx, new_state);
202 _vbo_InvalidateState(ctx, new_state);
203 _tnl_InvalidateState(ctx, new_state);
204 _ae_invalidate_state(ctx, new_state);
205
206 if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL))
207 {
208 _mesa_update_framebuffer(ctx);
209 /* this updates the DrawBuffer's Width/Height if it's a FBO */
210 _mesa_update_draw_buffer_bounds(ctx);
211
212 r700UpdateDrawBuffer(ctx);
213 }
214
215 r700UpdateStateParameters(ctx, new_state);
216
217 if(GL_TRUE == r700->bEnablePerspective)
218 {
219 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
220 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
221 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
222
223 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
224
225 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
226 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
227 }
228 else
229 {
230 /* For orthogonal case. */
231 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
232 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
233
234 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
235
236 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
237 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
238 }
239
240 context->radeon.NewGLState |= new_state;
241 }
242
243 static void r700SetDepthState(GLcontext * ctx)
244 {
245 context_t *context = R700_CONTEXT(ctx);
246
247 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
248
249 if (ctx->Depth.Test)
250 {
251 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
252 if (ctx->Depth.Mask)
253 {
254 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
255 }
256 else
257 {
258 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
259 }
260
261 switch (ctx->Depth.Func)
262 {
263 case GL_NEVER:
264 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NEVER,
265 ZFUNC_shift, ZFUNC_mask);
266 break;
267 case GL_LESS:
268 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LESS,
269 ZFUNC_shift, ZFUNC_mask);
270 break;
271 case GL_EQUAL:
272 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_EQUAL,
273 ZFUNC_shift, ZFUNC_mask);
274 break;
275 case GL_LEQUAL:
276 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LEQUAL,
277 ZFUNC_shift, ZFUNC_mask);
278 break;
279 case GL_GREATER:
280 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GREATER,
281 ZFUNC_shift, ZFUNC_mask);
282 break;
283 case GL_NOTEQUAL:
284 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NOTEQUAL,
285 ZFUNC_shift, ZFUNC_mask);
286 break;
287 case GL_GEQUAL:
288 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GEQUAL,
289 ZFUNC_shift, ZFUNC_mask);
290 break;
291 case GL_ALWAYS:
292 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
293 ZFUNC_shift, ZFUNC_mask);
294 break;
295 default:
296 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
297 ZFUNC_shift, ZFUNC_mask);
298 break;
299 }
300 }
301 else
302 {
303 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
304 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
305 }
306 }
307
308 static void r700AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref) //---------------
309 {
310 }
311
312
313 static void r700BlendColor(GLcontext * ctx, const GLfloat cf[4]) //----------------
314 {
315 }
316
317 static void r700BlendEquationSeparate(GLcontext * ctx,
318 GLenum modeRGB, GLenum modeA) //-----------------
319 {
320 }
321
322 static void r700BlendFuncSeparate(GLcontext * ctx,
323 GLenum sfactorRGB, GLenum dfactorRGB,
324 GLenum sfactorA, GLenum dfactorA) //------------------------
325 {
326 }
327
328 /**
329 * Translate LogicOp enums into hardware representation.
330 * Both use a very logical bit-wise layout, but unfortunately the order
331 * of bits is reversed.
332 */
333 static GLuint translate_logicop(GLenum logicop)
334 {
335 GLuint bits = logicop - GL_CLEAR;
336 bits = ((bits & 1) << 3) | ((bits & 2) << 1) | ((bits & 4) >> 1) | ((bits & 8) >> 3);
337 return bits;
338 }
339
340 /**
341 * Used internally to update the r300->hw hardware state to match the
342 * current OpenGL state.
343 */
344 static void r700SetLogicOpState(GLcontext *ctx)
345 {
346 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
347
348 if (RGBA_LOGICOP_ENABLED(ctx))
349 SETfield(r700->CB_COLOR_CONTROL.u32All,
350 translate_logicop(ctx->Color.LogicOp), ROP3_shift, ROP3_mask);
351 else
352 SETfield(r700->CB_COLOR_CONTROL.u32All, 0xCC, ROP3_shift, ROP3_mask);
353 }
354
355 /**
356 * Called by Mesa when an application program changes the LogicOp state
357 * via glLogicOp.
358 */
359 static void r700LogicOpcode(GLcontext *ctx, GLenum logicop)
360 {
361 if (RGBA_LOGICOP_ENABLED(ctx))
362 r700SetLogicOpState(ctx);
363 }
364
365 static void r700UpdateCulling(GLcontext * ctx)
366 {
367 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
368
369 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
370 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
371 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
372
373 if (ctx->Polygon.CullFlag)
374 {
375 switch (ctx->Polygon.CullFaceMode)
376 {
377 case GL_FRONT:
378 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
379 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
380 break;
381 case GL_BACK:
382 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
383 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
384 break;
385 case GL_FRONT_AND_BACK:
386 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
387 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
388 break;
389 default:
390 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
391 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
392 break;
393 }
394 }
395
396 switch (ctx->Polygon.FrontFace)
397 {
398 case GL_CW:
399 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
400 break;
401 case GL_CCW:
402 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
403 break;
404 default:
405 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); /* default: ccw */
406 break;
407 }
408 }
409
410 static void r700UpdateLineStipple(GLcontext * ctx)
411 {
412 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
413 if (ctx->Line.StippleFlag)
414 {
415 SETbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
416 }
417 else
418 {
419 CLEARbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
420 }
421 }
422
423 static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //------------------
424 {
425 context_t *context = R700_CONTEXT(ctx);
426
427 switch (cap) {
428 case GL_TEXTURE_1D:
429 case GL_TEXTURE_2D:
430 case GL_TEXTURE_3D:
431 /* empty */
432 break;
433 case GL_FOG:
434 /* empty */
435 break;
436 case GL_ALPHA_TEST:
437 //r700SetAlphaState(ctx);
438 break;
439 case GL_COLOR_LOGIC_OP:
440 r700SetLogicOpState(ctx);
441 /* fall-through, because logic op overrides blending */
442 case GL_BLEND:
443 //r700SetBlendState(ctx);
444 break;
445 case GL_CLIP_PLANE0:
446 case GL_CLIP_PLANE1:
447 case GL_CLIP_PLANE2:
448 case GL_CLIP_PLANE3:
449 case GL_CLIP_PLANE4:
450 case GL_CLIP_PLANE5:
451 r700SetClipPlaneState(ctx, cap, state);
452 break;
453 case GL_DEPTH_TEST:
454 r700SetDepthState(ctx);
455 break;
456 case GL_STENCIL_TEST:
457 //r700SetStencilState(ctx, state);
458 break;
459 case GL_CULL_FACE:
460 r700UpdateCulling(ctx);
461 break;
462 case GL_POLYGON_OFFSET_POINT:
463 case GL_POLYGON_OFFSET_LINE:
464 case GL_POLYGON_OFFSET_FILL:
465 //r700SetPolygonOffsetState(ctx, state);
466 break;
467 case GL_SCISSOR_TEST:
468 radeon_firevertices(&context->radeon);
469 context->radeon.state.scissor.enabled = state;
470 radeonUpdateScissor(ctx);
471 break;
472 case GL_LINE_STIPPLE:
473 r700UpdateLineStipple(ctx);
474 break;
475 default:
476 break;
477 }
478
479 }
480
481 /**
482 * Handle glColorMask()
483 */
484 static void r700ColorMask(GLcontext * ctx,
485 GLboolean r, GLboolean g, GLboolean b, GLboolean a) //------------------
486 {
487 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
488 unsigned int mask = ((r ? 1 : 0) |
489 (g ? 2 : 0) |
490 (b ? 4 : 0) |
491 (a ? 8 : 0));
492
493 if (mask != r700->CB_SHADER_MASK.u32All)
494 SETfield(r700->CB_SHADER_MASK.u32All, mask, OUTPUT0_ENABLE_shift, OUTPUT0_ENABLE_mask);
495 }
496
497 /**
498 * Change the depth testing function.
499 *
500 * \note Mesa already filters redundant calls to this function.
501 */
502 static void r700DepthFunc(GLcontext * ctx, GLenum func) //--------------------
503 {
504 r700SetDepthState(ctx);
505 }
506
507 /**
508 * Enable/Disable depth writing.
509 *
510 * \note Mesa already filters redundant calls to this function.
511 */
512 static void r700DepthMask(GLcontext * ctx, GLboolean mask) //------------------
513 {
514 r700SetDepthState(ctx);
515 }
516
517 /**
518 * Change the culling mode.
519 *
520 * \note Mesa already filters redundant calls to this function.
521 */
522 static void r700CullFace(GLcontext * ctx, GLenum mode) //-----------------
523 {
524 r700UpdateCulling(ctx);
525 }
526
527 /* =============================================================
528 * Fog
529 */
530 static void r700Fogfv(GLcontext * ctx, GLenum pname, const GLfloat * param) //--------------
531 {
532 }
533
534 /**
535 * Change the polygon orientation.
536 *
537 * \note Mesa already filters redundant calls to this function.
538 */
539 static void r700FrontFace(GLcontext * ctx, GLenum mode) //------------------
540 {
541 r700UpdateCulling(ctx);
542 }
543
544 static void r700ShadeModel(GLcontext * ctx, GLenum mode) //--------------------
545 {
546 context_t *context = R700_CONTEXT(ctx);
547 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
548
549 /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */
550 switch (mode) {
551 case GL_FLAT:
552 SETbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
553 break;
554 case GL_SMOOTH:
555 CLEARbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
556 break;
557 default:
558 return;
559 }
560 }
561
562 static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * param) //---------------
563 {
564 }
565
566 static void r700StencilFuncSeparate(GLcontext * ctx, GLenum face,
567 GLenum func, GLint ref, GLuint mask) //---------------------
568 {
569 }
570
571
572 static void r700StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) //--------------
573 {
574 }
575
576 static void r700StencilOpSeparate(GLcontext * ctx, GLenum face,
577 GLenum fail, GLenum zfail, GLenum zpass) //--------------------
578 {
579 }
580
581 static void r700UpdateWindow(GLcontext * ctx, int id) //--------------------
582 {
583
584 context_t *context = R700_CONTEXT(ctx);
585 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
586 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
587 GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
588 GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
589 const GLfloat *v = ctx->Viewport._WindowMap.m;
590 const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
591 const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
592 GLfloat y_scale, y_bias;
593
594 if (render_to_fbo) {
595 y_scale = 1.0;
596 y_bias = 0;
597 } else {
598 y_scale = -1.0;
599 y_bias = yoffset;
600 }
601
602 GLfloat sx = v[MAT_SX];
603 GLfloat tx = v[MAT_TX] + xoffset;
604 GLfloat sy = v[MAT_SY] * y_scale;
605 GLfloat ty = (v[MAT_TY] * y_scale) + y_bias;
606 GLfloat sz = v[MAT_SZ] * depthScale;
607 GLfloat tz = v[MAT_TZ] * depthScale;
608
609 /* TODO : Need DMA flush as well. */
610
611 r700->viewport[id].PA_CL_VPORT_XSCALE.f32All = sx;
612 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
613
614 r700->viewport[id].PA_CL_VPORT_YSCALE.f32All = sy;
615 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
616
617 r700->viewport[id].PA_CL_VPORT_ZSCALE.f32All = sz;
618 r700->viewport[id].PA_CL_VPORT_ZOFFSET.f32All = tz;
619
620 r700->viewport[id].enabled = GL_TRUE;
621
622 r700SetScissor(context);
623 }
624
625
626 static void r700Viewport(GLcontext * ctx,
627 GLint x,
628 GLint y,
629 GLsizei width,
630 GLsizei height) //--------------------
631 {
632 r700UpdateWindow(ctx, 0);
633
634 radeon_viewport(ctx, x, y, width, height);
635 }
636
637 static void r700DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) //-------------
638 {
639 r700UpdateWindow(ctx, 0);
640 }
641
642 static void r700PointSize(GLcontext * ctx, GLfloat size) //-------------------
643 {
644 }
645
646 static void r700LineWidth(GLcontext * ctx, GLfloat widthf) //---------------
647 {
648 context_t *context = R700_CONTEXT(ctx);
649 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
650 uint32_t lineWidth = (uint32_t)((widthf * 0.5) * (1 << 4));
651 if (lineWidth > 0xFFFF)
652 lineWidth = 0xFFFF;
653 SETfield(r700->PA_SU_LINE_CNTL.u32All,(uint16_t)lineWidth,
654 PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
655 }
656
657 static void r700LineStipple(GLcontext *ctx, GLint factor, GLushort pattern)
658 {
659 context_t *context = R700_CONTEXT(ctx);
660 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
661
662 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, pattern, LINE_PATTERN_shift, LINE_PATTERN_mask);
663 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, (factor-1), REPEAT_COUNT_shift, REPEAT_COUNT_mask);
664 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, 1, AUTO_RESET_CNTL_shift, AUTO_RESET_CNTL_mask);
665 }
666
667 static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) //--------------
668 {
669 }
670
671
672 static void r700PolygonMode(GLcontext * ctx, GLenum face, GLenum mode) //------------------
673 {
674 }
675
676 static void r700RenderMode(GLcontext * ctx, GLenum mode) //---------------------
677 {
678 }
679
680 static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
681 {
682 context_t *context = R700_CONTEXT(ctx);
683 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
684 GLint p;
685 GLint *ip;
686
687 p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
688 ip = (GLint *)ctx->Transform._ClipUserPlane[p];
689
690 r700->ucp[p].PA_CL_UCP_0_X.u32All = ip[0];
691 r700->ucp[p].PA_CL_UCP_0_Y.u32All = ip[1];
692 r700->ucp[p].PA_CL_UCP_0_Z.u32All = ip[2];
693 r700->ucp[p].PA_CL_UCP_0_W.u32All = ip[3];
694 }
695
696 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state)
697 {
698 context_t *context = R700_CONTEXT(ctx);
699 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
700 GLuint p;
701
702 p = cap - GL_CLIP_PLANE0;
703 if (state) {
704 r700->PA_CL_CLIP_CNTL.u32All |= (UCP_ENA_0_bit << p);
705 r700->ucp[p].enabled = GL_TRUE;
706 r700ClipPlane(ctx, cap, NULL);
707 } else {
708 r700->PA_CL_CLIP_CNTL.u32All &= ~(UCP_ENA_0_bit << p);
709 r700->ucp[p].enabled = GL_FALSE;
710 }
711 }
712
713 void r700SetScissor(context_t *context) //---------------
714 {
715 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
716 unsigned x1, y1, x2, y2;
717 int id = 0;
718 struct radeon_renderbuffer *rrb;
719
720 rrb = radeon_get_colorbuffer(&context->radeon);
721 if (!rrb || !rrb->bo) {
722 return;
723 }
724 if (context->radeon.state.scissor.enabled) {
725 x1 = context->radeon.state.scissor.rect.x1;
726 y1 = context->radeon.state.scissor.rect.y1;
727 x2 = context->radeon.state.scissor.rect.x2 - 1;
728 y2 = context->radeon.state.scissor.rect.y2 - 1;
729 } else {
730 x1 = rrb->dPriv->x;
731 y1 = rrb->dPriv->y;
732 x2 = rrb->dPriv->x + rrb->dPriv->w;
733 y2 = rrb->dPriv->y + rrb->dPriv->h;
734 }
735
736 /* window */
737 SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
738 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, x1,
739 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask);
740 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, y1,
741 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask);
742
743 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, x2,
744 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask);
745 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, y2,
746 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask);
747
748
749 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, x1,
750 PA_SC_CLIPRECT_0_TL__TL_X_shift, PA_SC_CLIPRECT_0_TL__TL_X_mask);
751 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, y1,
752 PA_SC_CLIPRECT_0_TL__TL_Y_shift, PA_SC_CLIPRECT_0_TL__TL_Y_mask);
753 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, x2,
754 PA_SC_CLIPRECT_0_BR__BR_X_shift, PA_SC_CLIPRECT_0_BR__BR_X_mask);
755 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, y2,
756 PA_SC_CLIPRECT_0_BR__BR_Y_shift, PA_SC_CLIPRECT_0_BR__BR_Y_mask);
757
758 r700->PA_SC_CLIPRECT_1_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
759 r700->PA_SC_CLIPRECT_1_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
760 r700->PA_SC_CLIPRECT_2_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
761 r700->PA_SC_CLIPRECT_2_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
762 r700->PA_SC_CLIPRECT_3_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
763 r700->PA_SC_CLIPRECT_3_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
764
765 /* more....2d clip */
766 SETbit(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
767 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, x1,
768 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask);
769 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, y1,
770 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask);
771 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, x2,
772 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask);
773 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, y2,
774 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask);
775
776 SETbit(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
777 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, x1,
778 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask);
779 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, y1,
780 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask);
781 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, x2,
782 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask);
783 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, y2,
784 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask);
785
786 r700->viewport[id].PA_SC_VPORT_ZMIN_0.u32All = 0;
787 r700->viewport[id].PA_SC_VPORT_ZMAX_0.u32All = 0x3F800000;
788 r700->viewport[id].enabled = GL_TRUE;
789 }
790
791 void r700SetRenderTarget(context_t *context, int id)
792 {
793 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
794
795 struct radeon_renderbuffer *rrb;
796 unsigned int nPitchInPixel;
797
798 /* screen/window/view */
799 SETfield(r700->CB_TARGET_MASK.u32All, 0xF, (4 * id), TARGET0_ENABLE_mask);
800
801 rrb = radeon_get_colorbuffer(&context->radeon);
802 if (!rrb || !rrb->bo) {
803 fprintf(stderr, "no rrb\n");
804 return;
805 }
806
807 /* color buffer */
808 r700->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset;
809
810 nPitchInPixel = rrb->pitch/rrb->cpp;
811 SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1,
812 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
813 SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
814 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
815 r700->render_target[id].CB_COLOR0_BASE.u32All = 0;
816 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
817 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL,
818 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
819 if(4 == rrb->cpp)
820 {
821 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_8_8_8_8,
822 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
823 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT, COMP_SWAP_shift, COMP_SWAP_mask);
824 }
825 else
826 {
827 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_5_6_5,
828 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
829 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT_REV,
830 COMP_SWAP_shift, COMP_SWAP_mask);
831 }
832 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
833 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit);
834 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
835
836 CLEARfield(r700->render_target[id].CB_BLEND0_CONTROL.u32All, COLOR_SRCBLEND_mask); /* no dst blend */
837 CLEARfield(r700->render_target[id].CB_BLEND0_CONTROL.u32All, ALPHA_SRCBLEND_mask); /* no dst blend */
838
839 r700->render_target[id].enabled = GL_TRUE;
840 }
841
842 void r700SetDepthTarget(context_t *context)
843 {
844 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
845
846 struct radeon_renderbuffer *rrb;
847 unsigned int nPitchInPixel;
848
849 /* depth buf */
850 r700->DB_DEPTH_SIZE.u32All = 0;
851 r700->DB_DEPTH_BASE.u32All = 0;
852 r700->DB_DEPTH_INFO.u32All = 0;
853
854 r700->DB_DEPTH_CLEAR.u32All = 0x3F800000;
855 r700->DB_DEPTH_VIEW.u32All = 0;
856 r700->DB_RENDER_CONTROL.u32All = 0;
857 SETbit(r700->DB_RENDER_CONTROL.u32All, STENCIL_COMPRESS_DISABLE_bit);
858 SETbit(r700->DB_RENDER_CONTROL.u32All, DEPTH_COMPRESS_DISABLE_bit);
859 r700->DB_RENDER_OVERRIDE.u32All = 0;
860 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
861 SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit);
862 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
863 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
864 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
865
866 r700->DB_ALPHA_TO_MASK.u32All = 0;
867 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask);
868 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET1_shift, ALPHA_TO_MASK_OFFSET1_mask);
869 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET2_shift, ALPHA_TO_MASK_OFFSET2_mask);
870 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET3_shift, ALPHA_TO_MASK_OFFSET3_mask);
871
872 rrb = radeon_get_depthbuffer(&context->radeon);
873 if (!rrb)
874 return;
875
876 nPitchInPixel = rrb->pitch/rrb->cpp;
877
878 SETfield(r700->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1,
879 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
880 SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
881 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */
882
883 if(4 == rrb->cpp)
884 {
885 switch (GL_CONTEXT(context)->Visual.depthBits)
886 {
887 case 16:
888 case 24:
889 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_8_24,
890 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
891 break;
892 default:
893 fprintf(stderr, "Error: Unsupported depth %d... exiting\n",
894 GL_CONTEXT(context)->Visual.depthBits);
895 _mesa_exit(-1);
896 }
897 }
898 else
899 {
900 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16,
901 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
902 }
903 SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_2D_TILED_THIN1,
904 DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask);
905 /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */
906 }
907
908 static void r700InitSQConfig(GLcontext * ctx)
909 {
910 context_t *context = R700_CONTEXT(ctx);
911 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
912 int ps_prio;
913 int vs_prio;
914 int gs_prio;
915 int es_prio;
916 int num_ps_gprs;
917 int num_vs_gprs;
918 int num_gs_gprs;
919 int num_es_gprs;
920 int num_temp_gprs;
921 int num_ps_threads;
922 int num_vs_threads;
923 int num_gs_threads;
924 int num_es_threads;
925 int num_ps_stack_entries;
926 int num_vs_stack_entries;
927 int num_gs_stack_entries;
928 int num_es_stack_entries;
929
930 // SQ
931 ps_prio = 0;
932 vs_prio = 1;
933 gs_prio = 2;
934 es_prio = 3;
935 switch (context->radeon.radeonScreen->chip_family) {
936 case CHIP_FAMILY_R600:
937 num_ps_gprs = 192;
938 num_vs_gprs = 56;
939 num_temp_gprs = 4;
940 num_gs_gprs = 0;
941 num_es_gprs = 0;
942 num_ps_threads = 136;
943 num_vs_threads = 48;
944 num_gs_threads = 4;
945 num_es_threads = 4;
946 num_ps_stack_entries = 128;
947 num_vs_stack_entries = 128;
948 num_gs_stack_entries = 0;
949 num_es_stack_entries = 0;
950 break;
951 case CHIP_FAMILY_RV630:
952 case CHIP_FAMILY_RV635:
953 num_ps_gprs = 84;
954 num_vs_gprs = 36;
955 num_temp_gprs = 4;
956 num_gs_gprs = 0;
957 num_es_gprs = 0;
958 num_ps_threads = 144;
959 num_vs_threads = 40;
960 num_gs_threads = 4;
961 num_es_threads = 4;
962 num_ps_stack_entries = 40;
963 num_vs_stack_entries = 40;
964 num_gs_stack_entries = 32;
965 num_es_stack_entries = 16;
966 break;
967 case CHIP_FAMILY_RV610:
968 case CHIP_FAMILY_RV620:
969 case CHIP_FAMILY_RS780:
970 default:
971 num_ps_gprs = 84;
972 num_vs_gprs = 36;
973 num_temp_gprs = 4;
974 num_gs_gprs = 0;
975 num_es_gprs = 0;
976 num_ps_threads = 136;
977 num_vs_threads = 48;
978 num_gs_threads = 4;
979 num_es_threads = 4;
980 num_ps_stack_entries = 40;
981 num_vs_stack_entries = 40;
982 num_gs_stack_entries = 32;
983 num_es_stack_entries = 16;
984 break;
985 case CHIP_FAMILY_RV670:
986 num_ps_gprs = 144;
987 num_vs_gprs = 40;
988 num_temp_gprs = 4;
989 num_gs_gprs = 0;
990 num_es_gprs = 0;
991 num_ps_threads = 136;
992 num_vs_threads = 48;
993 num_gs_threads = 4;
994 num_es_threads = 4;
995 num_ps_stack_entries = 40;
996 num_vs_stack_entries = 40;
997 num_gs_stack_entries = 32;
998 num_es_stack_entries = 16;
999 break;
1000 case CHIP_FAMILY_RV770:
1001 num_ps_gprs = 192;
1002 num_vs_gprs = 56;
1003 num_temp_gprs = 4;
1004 num_gs_gprs = 0;
1005 num_es_gprs = 0;
1006 num_ps_threads = 188;
1007 num_vs_threads = 60;
1008 num_gs_threads = 0;
1009 num_es_threads = 0;
1010 num_ps_stack_entries = 256;
1011 num_vs_stack_entries = 256;
1012 num_gs_stack_entries = 0;
1013 num_es_stack_entries = 0;
1014 break;
1015 case CHIP_FAMILY_RV730:
1016 case CHIP_FAMILY_RV740:
1017 num_ps_gprs = 84;
1018 num_vs_gprs = 36;
1019 num_temp_gprs = 4;
1020 num_gs_gprs = 0;
1021 num_es_gprs = 0;
1022 num_ps_threads = 188;
1023 num_vs_threads = 60;
1024 num_gs_threads = 0;
1025 num_es_threads = 0;
1026 num_ps_stack_entries = 128;
1027 num_vs_stack_entries = 128;
1028 num_gs_stack_entries = 0;
1029 num_es_stack_entries = 0;
1030 break;
1031 case CHIP_FAMILY_RV710:
1032 num_ps_gprs = 192;
1033 num_vs_gprs = 56;
1034 num_temp_gprs = 4;
1035 num_gs_gprs = 0;
1036 num_es_gprs = 0;
1037 num_ps_threads = 144;
1038 num_vs_threads = 48;
1039 num_gs_threads = 0;
1040 num_es_threads = 0;
1041 num_ps_stack_entries = 128;
1042 num_vs_stack_entries = 128;
1043 num_gs_stack_entries = 0;
1044 num_es_stack_entries = 0;
1045 break;
1046 }
1047
1048 r700->sq_config.SQ_CONFIG.u32All = 0;
1049 if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
1050 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
1051 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
1052 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
1053 CLEARbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1054 else
1055 SETbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1056 SETbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit);
1057 SETbit(r700->sq_config.SQ_CONFIG.u32All, ALU_INST_PREFER_VECTOR_bit);
1058 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, PS_PRIO_shift, PS_PRIO_mask);
1059 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, VS_PRIO_shift, VS_PRIO_mask);
1060 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, GS_PRIO_shift, GS_PRIO_mask);
1061 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, ES_PRIO_shift, ES_PRIO_mask);
1062
1063 r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All = 0;
1064 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_ps_gprs, NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
1065 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_vs_gprs, NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
1066 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_temp_gprs,
1067 NUM_CLAUSE_TEMP_GPRS_shift, NUM_CLAUSE_TEMP_GPRS_mask);
1068
1069 r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All = 0;
1070 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_gs_gprs, NUM_GS_GPRS_shift, NUM_GS_GPRS_mask);
1071 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_es_gprs, NUM_ES_GPRS_shift, NUM_ES_GPRS_mask);
1072
1073 r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All = 0;
1074 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_ps_threads,
1075 NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
1076 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_vs_threads,
1077 NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
1078 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_gs_threads,
1079 NUM_GS_THREADS_shift, NUM_GS_THREADS_mask);
1080 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_es_threads,
1081 NUM_ES_THREADS_shift, NUM_ES_THREADS_mask);
1082
1083 r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All = 0;
1084 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_ps_stack_entries,
1085 NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
1086 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_vs_stack_entries,
1087 NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
1088
1089 r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All = 0;
1090 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_gs_stack_entries,
1091 NUM_GS_STACK_ENTRIES_shift, NUM_GS_STACK_ENTRIES_mask);
1092 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_es_stack_entries,
1093 NUM_ES_STACK_ENTRIES_shift, NUM_ES_STACK_ENTRIES_mask);
1094
1095 }
1096
1097 /**
1098 * Calculate initial hardware state and register state functions.
1099 * Assumes that the command buffer and state atoms have been
1100 * initialized already.
1101 */
1102 void r700InitState(GLcontext * ctx) //-------------------
1103 {
1104 context_t *context = R700_CONTEXT(ctx);
1105
1106 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1107
1108 r700->TA_CNTL_AUX.u32All = 0;
1109 SETfield(r700->TA_CNTL_AUX.u32All, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask);
1110 r700->VC_ENHANCE.u32All = 0;
1111 r700->DB_WATERMARKS.u32All = 0;
1112 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_FREE_shift, DEPTH_FREE_mask);
1113 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_FLUSH_shift, DEPTH_FLUSH_mask);
1114 SETfield(r700->DB_WATERMARKS.u32All, 0, FORCE_SUMMARIZE_shift, FORCE_SUMMARIZE_mask);
1115 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_PENDING_FREE_shift, DEPTH_PENDING_FREE_mask);
1116 r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All = 0;
1117 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1118 SETfield(r700->TA_CNTL_AUX.u32All, 3, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1119 r700->DB_DEBUG.u32All = 0x82000000;
1120 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1121 } else {
1122 SETfield(r700->TA_CNTL_AUX.u32All, 2, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1123 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1124 SETbit(r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All, VS_PC_LIMIT_ENABLE_bit);
1125 }
1126
1127 /* Turn off vgt reuse */
1128 r700->VGT_REUSE_OFF.u32All = 0;
1129 SETbit(r700->VGT_REUSE_OFF.u32All, REUSE_OFF_bit);
1130
1131 /* Specify offsetting and clamp values for vertices */
1132 r700->VGT_MAX_VTX_INDX.u32All = 0xFFFFFF;
1133 r700->VGT_MIN_VTX_INDX.u32All = 0;
1134 r700->VGT_INDX_OFFSET.u32All = 0;
1135
1136 /* Specify the number of instances */
1137 r700->VGT_DMA_NUM_INSTANCES.u32All = 1;
1138
1139 /* not alpha blend */
1140 CLEARfield(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_FUNC_mask);
1141 CLEARbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
1142
1143 /* default shader connections. */
1144 r700->SPI_VS_OUT_ID_0.u32All = 0x03020100;
1145 r700->SPI_VS_OUT_ID_1.u32All = 0x07060504;
1146
1147 r700->SPI_PS_INPUT_CNTL_0.u32All = 0x00000800;
1148 r700->SPI_PS_INPUT_CNTL_1.u32All = 0x00000801;
1149 r700->SPI_PS_INPUT_CNTL_2.u32All = 0x00000802;
1150
1151 r700->SPI_THREAD_GROUPING.u32All = 0;
1152 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
1153 SETfield(r700->SPI_THREAD_GROUPING.u32All, 1, PS_GROUPING_shift, PS_GROUPING_mask);
1154
1155 r700SetLogicOpState(ctx);
1156 CLEARbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit);
1157
1158 r700->DB_SHADER_CONTROL.u32All = 0;
1159 SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
1160
1161 /* Set up the culling control register */
1162 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1163 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1164 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1165 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1166
1167 /* screen */
1168 r700->PA_SC_SCREEN_SCISSOR_TL.u32All = 0x0;
1169
1170 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All,
1171 ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->width,
1172 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask);
1173 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All,
1174 ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->height,
1175 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask);
1176
1177 /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
1178 r700->PA_SC_CLIPRECT_RULE.u32All = 0;
1179 SETfield(r700->PA_SC_CLIPRECT_RULE.u32All, CLIP_RULE_mask, CLIP_RULE_shift, CLIP_RULE_mask);
1180
1181 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1182 r700->PA_SC_EDGERULE.u32All = 0;
1183 else
1184 r700->PA_SC_EDGERULE.u32All = 0xAAAAAAAA;
1185
1186 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1187 r700->PA_SC_MODE_CNTL.u32All = 0;
1188 SETbit(r700->PA_SC_MODE_CNTL.u32All, WALK_ORDER_ENABLE_bit);
1189 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1190 } else {
1191 r700->PA_SC_MODE_CNTL.u32All = 0x00500000;
1192 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_REZ_ENABLE_bit);
1193 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1194 }
1195
1196 /* Do scale XY and Z by 1/W0. */
1197 r700->bEnablePerspective = GL_TRUE;
1198 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
1199 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
1200 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
1201
1202 /* Enable viewport scaling for all three axis */
1203 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_SCALE_ENA_bit);
1204 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_OFFSET_ENA_bit);
1205 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_SCALE_ENA_bit);
1206 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_OFFSET_ENA_bit);
1207 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_SCALE_ENA_bit);
1208 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_OFFSET_ENA_bit);
1209
1210 /* Set up point sizes and min/max values */
1211 SETfield(r700->PA_SU_POINT_SIZE.u32All, 0x8,
1212 PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask);
1213 SETfield(r700->PA_SU_POINT_SIZE.u32All, 0x8,
1214 PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask);
1215 CLEARfield(r700->PA_SU_POINT_MINMAX.u32All, MIN_SIZE_mask);
1216 SETfield(r700->PA_SU_POINT_MINMAX.u32All, 0x8000, MAX_SIZE_shift, MAX_SIZE_mask);
1217
1218 /* Set up line control */
1219 SETfield(r700->PA_SU_LINE_CNTL.u32All, 0x8,
1220 PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
1221
1222 r700->PA_SC_LINE_CNTL.u32All = 0;
1223 CLEARbit(r700->PA_SC_LINE_CNTL.u32All, EXPAND_LINE_WIDTH_bit);
1224 SETbit(r700->PA_SC_LINE_CNTL.u32All, LAST_PIXEL_bit);
1225
1226 /* Set up vertex control */
1227 r700->PA_SU_VTX_CNTL.u32All = 0;
1228 CLEARfield(r700->PA_SU_VTX_CNTL.u32All, QUANT_MODE_mask);
1229 SETbit(r700->PA_SU_VTX_CNTL.u32All, PIX_CENTER_bit);
1230 SETfield(r700->PA_SU_VTX_CNTL.u32All, X_ROUND_TO_EVEN,
1231 PA_SU_VTX_CNTL__ROUND_MODE_shift, PA_SU_VTX_CNTL__ROUND_MODE_mask);
1232
1233 /* to 1.0 = no guard band */
1234 r700->PA_CL_GB_VERT_CLIP_ADJ.u32All = 0x3F800000; /* 1.0 */
1235 r700->PA_CL_GB_VERT_DISC_ADJ.u32All = 0x3F800000;
1236 r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All = 0x3F800000;
1237 r700->PA_CL_GB_HORZ_DISC_ADJ.u32All = 0x3F800000;
1238
1239 /* CB */
1240 r700->CB_CLEAR_RED_R6XX.f32All = 1.0; //r6xx only
1241 r700->CB_CLEAR_GREEN_R6XX.f32All = 0.0; //r6xx only
1242 r700->CB_CLEAR_BLUE_R6XX.f32All = 1.0; //r6xx only
1243 r700->CB_CLEAR_ALPHA_R6XX.f32All = 1.0; //r6xx only
1244 r700->CB_FOG_RED_R6XX.u32All = 0; //r6xx only
1245 r700->CB_FOG_GREEN_R6XX.u32All = 0; //r6xx only
1246 r700->CB_FOG_BLUE_R6XX.u32All = 0; //r6xx only
1247
1248 r700->CB_BLEND_RED.u32All = 0;
1249 r700->CB_BLEND_GREEN.u32All = 0;
1250 r700->CB_BLEND_BLUE.u32All = 0;
1251 r700->CB_BLEND_ALPHA.u32All = 0;
1252
1253 r700->CB_BLEND_CONTROL.u32All = 0;
1254
1255 /* Disable color compares */
1256 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1257 CLRCMP_FCN_SRC_shift, CLRCMP_FCN_SRC_mask);
1258 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1259 CLRCMP_FCN_DST_shift, CLRCMP_FCN_DST_mask);
1260 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_SEL_SRC,
1261 CLRCMP_FCN_SEL_shift, CLRCMP_FCN_SEL_mask);
1262
1263 /* Zero out source */
1264 r700->CB_CLRCMP_SRC.u32All = 0x00000000;
1265
1266 /* Put a compare color in for error checking */
1267 r700->CB_CLRCMP_DST.u32All = 0x000000FF;
1268
1269 /* Set up color compare mask */
1270 r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF;
1271
1272 /* default color mask */
1273 SETfield(r700->CB_SHADER_MASK.u32All, 0xF, OUTPUT0_ENABLE_shift, OUTPUT0_ENABLE_mask);
1274
1275 /* Enable all samples for multi-sample anti-aliasing */
1276 r700->PA_SC_AA_MASK.u32All = 0xFFFFFFFF;
1277 /* Turn off AA */
1278 r700->PA_SC_AA_CONFIG.u32All = 0;
1279
1280 r700->SX_MISC.u32All = 0;
1281
1282 r700InitSQConfig(ctx);
1283 }
1284
1285 void r700InitStateFuncs(struct dd_function_table *functions) //-----------------
1286 {
1287 functions->UpdateState = r700InvalidateState;
1288 functions->AlphaFunc = r700AlphaFunc;
1289 functions->BlendColor = r700BlendColor;
1290 functions->BlendEquationSeparate = r700BlendEquationSeparate;
1291 functions->BlendFuncSeparate = r700BlendFuncSeparate;
1292 functions->Enable = r700Enable;
1293 functions->ColorMask = r700ColorMask;
1294 functions->DepthFunc = r700DepthFunc;
1295 functions->DepthMask = r700DepthMask;
1296 functions->CullFace = r700CullFace;
1297 functions->Fogfv = r700Fogfv;
1298 functions->FrontFace = r700FrontFace;
1299 functions->ShadeModel = r700ShadeModel;
1300 functions->LogicOpcode = r700LogicOpcode;
1301
1302 /* ARB_point_parameters */
1303 functions->PointParameterfv = r700PointParameter;
1304
1305 /* Stencil related */
1306 functions->StencilFuncSeparate = r700StencilFuncSeparate;
1307 functions->StencilMaskSeparate = r700StencilMaskSeparate;
1308 functions->StencilOpSeparate = r700StencilOpSeparate;
1309
1310 /* Viewport related */
1311 functions->Viewport = r700Viewport;
1312 functions->DepthRange = r700DepthRange;
1313 functions->PointSize = r700PointSize;
1314 functions->LineWidth = r700LineWidth;
1315 functions->LineStipple = r700LineStipple;
1316
1317 functions->PolygonOffset = r700PolygonOffset;
1318 functions->PolygonMode = r700PolygonMode;
1319
1320 functions->RenderMode = r700RenderMode;
1321
1322 functions->ClipPlane = r700ClipPlane;
1323
1324 functions->Scissor = radeonScissor;
1325
1326 functions->DrawBuffer = radeonDrawBuffer;
1327 functions->ReadBuffer = radeonReadBuffer;
1328
1329 }
1330