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[mesa.git] / src / mesa / drivers / dri / r600 / r700_state.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/context.h"
34 #include "main/dd.h"
35 #include "main/simple_list.h"
36
37 #include "tnl/tnl.h"
38 #include "tnl/t_pipeline.h"
39 #include "tnl/t_vp_build.h"
40 #include "swrast/swrast.h"
41 #include "swrast_setup/swrast_setup.h"
42 #include "main/api_arrayelt.h"
43 #include "main/state.h"
44 #include "main/framebuffer.h"
45
46 #include "shader/prog_parameter.h"
47 #include "shader/prog_statevars.h"
48 #include "vbo/vbo.h"
49
50 #include "r600_context.h"
51
52 #include "r700_state.h"
53
54 #include "r700_fragprog.h"
55 #include "r700_vertprog.h"
56
57 void r600UpdateTextureState(GLcontext * ctx);
58 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state);
59 static void r700UpdatePolygonMode(GLcontext * ctx);
60 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state);
61 static void r700SetStencilState(GLcontext * ctx, GLboolean state);
62
63 void r700UpdateShaders(GLcontext * ctx)
64 {
65 context_t *context = R700_CONTEXT(ctx);
66
67 /* should only happenen once, just after context is created */
68 /* TODO: shouldn't we fallback to sw here? */
69 if (!ctx->FragmentProgram._Current) {
70 _mesa_fprintf(stderr, "No ctx->FragmentProgram._Current!!\n");
71 return;
72 }
73
74 r700SelectFragmentShader(ctx);
75
76 r700SelectVertexShader(ctx);
77 r700UpdateStateParameters(ctx, _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS);
78 context->radeon.NewGLState = 0;
79 }
80
81 /*
82 * To correctly position primitives:
83 */
84 void r700UpdateViewportOffset(GLcontext * ctx) //------------------
85 {
86 context_t *context = R700_CONTEXT(ctx);
87 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
88 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
89 GLfloat xoffset = (GLfloat) dPriv->x;
90 GLfloat yoffset = (GLfloat) dPriv->y + dPriv->h;
91 const GLfloat *v = ctx->Viewport._WindowMap.m;
92 int id = 0;
93
94 GLfloat tx = v[MAT_TX] + xoffset;
95 GLfloat ty = (-v[MAT_TY]) + yoffset;
96
97 if (r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All != tx ||
98 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All != ty) {
99 /* Note: this should also modify whatever data the context reset
100 * code uses...
101 */
102 R600_STATECHANGE(context, vpt);
103 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
104 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
105 }
106
107 radeonUpdateScissor(ctx);
108 }
109
110 void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state) //--------------------
111 {
112 struct r700_fragment_program *fp =
113 (struct r700_fragment_program *)ctx->FragmentProgram._Current;
114 struct gl_program_parameter_list *paramList;
115
116 if (!(new_state & (_NEW_BUFFERS | _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS)))
117 return;
118
119 if (!ctx->FragmentProgram._Current || !fp)
120 return;
121
122 paramList = ctx->FragmentProgram._Current->Base.Parameters;
123
124 if (!paramList)
125 return;
126
127 _mesa_load_state_parameters(ctx, paramList);
128
129 }
130
131 /**
132 * Called by Mesa after an internal state update.
133 */
134 static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //-------------------
135 {
136 context_t *context = R700_CONTEXT(ctx);
137
138 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
139
140 _swrast_InvalidateState(ctx, new_state);
141 _swsetup_InvalidateState(ctx, new_state);
142 _vbo_InvalidateState(ctx, new_state);
143 _tnl_InvalidateState(ctx, new_state);
144 _ae_invalidate_state(ctx, new_state);
145
146 if (new_state & _NEW_BUFFERS) {
147 _mesa_update_framebuffer(ctx);
148 /* this updates the DrawBuffer's Width/Height if it's a FBO */
149 _mesa_update_draw_buffer_bounds(ctx);
150
151 R600_STATECHANGE(context, cb_target);
152 R600_STATECHANGE(context, db_target);
153 }
154
155 if (new_state & (_NEW_LIGHT)) {
156 R600_STATECHANGE(context, su);
157 if (ctx->Light.ProvokingVertex == GL_LAST_VERTEX_CONVENTION)
158 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
159 else
160 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
161 }
162
163 r700UpdateStateParameters(ctx, new_state);
164
165 R600_STATECHANGE(context, cl);
166 R600_STATECHANGE(context, spi);
167
168 if(GL_TRUE == r700->bEnablePerspective)
169 {
170 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
171 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
172 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
173
174 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
175
176 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
177 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
178 }
179 else
180 {
181 /* For orthogonal case. */
182 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
183 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
184
185 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
186
187 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
188 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
189 }
190
191 context->radeon.NewGLState |= new_state;
192 }
193
194 static void r700SetDBRenderState(GLcontext * ctx)
195 {
196 context_t *context = R700_CONTEXT(ctx);
197 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
198 struct r700_fragment_program *fp = (struct r700_fragment_program *)
199 (ctx->FragmentProgram._Current);
200
201 R600_STATECHANGE(context, db);
202
203 SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
204 SETfield(r700->DB_SHADER_CONTROL.u32All, EARLY_Z_THEN_LATE_Z, Z_ORDER_shift, Z_ORDER_mask);
205 /* XXX not sure if this is required */
206 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
207 SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit);
208 /* XXX need to enable htile for hiz/s */
209 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
210 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
211 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
212
213 if (context->radeon.query.current)
214 {
215 SETbit(r700->DB_RENDER_OVERRIDE.u32All, NOOP_CULL_DISABLE_bit);
216 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
217 {
218 SETbit(r700->DB_RENDER_CONTROL.u32All, PERFECT_ZPASS_COUNTS_bit);
219 }
220 }
221 else
222 {
223 CLEARbit(r700->DB_RENDER_OVERRIDE.u32All, NOOP_CULL_DISABLE_bit);
224 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
225 {
226 CLEARbit(r700->DB_RENDER_CONTROL.u32All, PERFECT_ZPASS_COUNTS_bit);
227 }
228 }
229
230 if (fp)
231 {
232 if (fp->r700Shader.killIsUsed)
233 {
234 SETbit(r700->DB_SHADER_CONTROL.u32All, KILL_ENABLE_bit);
235 }
236 else
237 {
238 CLEARbit(r700->DB_SHADER_CONTROL.u32All, KILL_ENABLE_bit);
239 }
240
241 if (fp->r700Shader.depthIsExported)
242 {
243 SETbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit);
244 }
245 else
246 {
247 CLEARbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit);
248 }
249 }
250 }
251
252 void r700UpdateShaderStates(GLcontext * ctx)
253 {
254 r700SetDBRenderState(ctx);
255 r600UpdateTextureState(ctx);
256 }
257
258 static void r700SetDepthState(GLcontext * ctx)
259 {
260 context_t *context = R700_CONTEXT(ctx);
261 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
262
263 R600_STATECHANGE(context, db);
264
265 if (ctx->Depth.Test)
266 {
267 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
268 if (ctx->Depth.Mask)
269 {
270 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
271 }
272 else
273 {
274 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
275 }
276
277 switch (ctx->Depth.Func)
278 {
279 case GL_NEVER:
280 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NEVER,
281 ZFUNC_shift, ZFUNC_mask);
282 break;
283 case GL_LESS:
284 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LESS,
285 ZFUNC_shift, ZFUNC_mask);
286 break;
287 case GL_EQUAL:
288 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_EQUAL,
289 ZFUNC_shift, ZFUNC_mask);
290 break;
291 case GL_LEQUAL:
292 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LEQUAL,
293 ZFUNC_shift, ZFUNC_mask);
294 break;
295 case GL_GREATER:
296 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GREATER,
297 ZFUNC_shift, ZFUNC_mask);
298 break;
299 case GL_NOTEQUAL:
300 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NOTEQUAL,
301 ZFUNC_shift, ZFUNC_mask);
302 break;
303 case GL_GEQUAL:
304 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GEQUAL,
305 ZFUNC_shift, ZFUNC_mask);
306 break;
307 case GL_ALWAYS:
308 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
309 ZFUNC_shift, ZFUNC_mask);
310 break;
311 default:
312 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
313 ZFUNC_shift, ZFUNC_mask);
314 break;
315 }
316 }
317 else
318 {
319 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
320 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
321 }
322 }
323
324 static void r700SetAlphaState(GLcontext * ctx)
325 {
326 context_t *context = R700_CONTEXT(ctx);
327 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
328 uint32_t alpha_func = REF_ALWAYS;
329 GLboolean really_enabled = ctx->Color.AlphaEnabled;
330
331 R600_STATECHANGE(context, sx);
332
333 switch (ctx->Color.AlphaFunc) {
334 case GL_NEVER:
335 alpha_func = REF_NEVER;
336 break;
337 case GL_LESS:
338 alpha_func = REF_LESS;
339 break;
340 case GL_EQUAL:
341 alpha_func = REF_EQUAL;
342 break;
343 case GL_LEQUAL:
344 alpha_func = REF_LEQUAL;
345 break;
346 case GL_GREATER:
347 alpha_func = REF_GREATER;
348 break;
349 case GL_NOTEQUAL:
350 alpha_func = REF_NOTEQUAL;
351 break;
352 case GL_GEQUAL:
353 alpha_func = REF_GEQUAL;
354 break;
355 case GL_ALWAYS:
356 /*alpha_func = REF_ALWAYS; */
357 really_enabled = GL_FALSE;
358 break;
359 }
360
361 if (really_enabled) {
362 SETfield(r700->SX_ALPHA_TEST_CONTROL.u32All, alpha_func,
363 ALPHA_FUNC_shift, ALPHA_FUNC_mask);
364 SETbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
365 r700->SX_ALPHA_REF.f32All = ctx->Color.AlphaRef;
366 } else {
367 CLEARbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
368 }
369
370 }
371
372 static void r700AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref) //---------------
373 {
374 (void)func;
375 (void)ref;
376 r700SetAlphaState(ctx);
377 }
378
379
380 static void r700BlendColor(GLcontext * ctx, const GLfloat cf[4]) //----------------
381 {
382 context_t *context = R700_CONTEXT(ctx);
383 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
384
385 R600_STATECHANGE(context, blnd_clr);
386
387 r700->CB_BLEND_RED.f32All = cf[0];
388 r700->CB_BLEND_GREEN.f32All = cf[1];
389 r700->CB_BLEND_BLUE.f32All = cf[2];
390 r700->CB_BLEND_ALPHA.f32All = cf[3];
391 }
392
393 static int blend_factor(GLenum factor, GLboolean is_src)
394 {
395 switch (factor) {
396 case GL_ZERO:
397 return BLEND_ZERO;
398 break;
399 case GL_ONE:
400 return BLEND_ONE;
401 break;
402 case GL_DST_COLOR:
403 return BLEND_DST_COLOR;
404 break;
405 case GL_ONE_MINUS_DST_COLOR:
406 return BLEND_ONE_MINUS_DST_COLOR;
407 break;
408 case GL_SRC_COLOR:
409 return BLEND_SRC_COLOR;
410 break;
411 case GL_ONE_MINUS_SRC_COLOR:
412 return BLEND_ONE_MINUS_SRC_COLOR;
413 break;
414 case GL_SRC_ALPHA:
415 return BLEND_SRC_ALPHA;
416 break;
417 case GL_ONE_MINUS_SRC_ALPHA:
418 return BLEND_ONE_MINUS_SRC_ALPHA;
419 break;
420 case GL_DST_ALPHA:
421 return BLEND_DST_ALPHA;
422 break;
423 case GL_ONE_MINUS_DST_ALPHA:
424 return BLEND_ONE_MINUS_DST_ALPHA;
425 break;
426 case GL_SRC_ALPHA_SATURATE:
427 return (is_src) ? BLEND_SRC_ALPHA_SATURATE : BLEND_ZERO;
428 break;
429 case GL_CONSTANT_COLOR:
430 return BLEND_CONSTANT_COLOR;
431 break;
432 case GL_ONE_MINUS_CONSTANT_COLOR:
433 return BLEND_ONE_MINUS_CONSTANT_COLOR;
434 break;
435 case GL_CONSTANT_ALPHA:
436 return BLEND_CONSTANT_ALPHA;
437 break;
438 case GL_ONE_MINUS_CONSTANT_ALPHA:
439 return BLEND_ONE_MINUS_CONSTANT_ALPHA;
440 break;
441 default:
442 fprintf(stderr, "unknown blend factor %x\n", factor);
443 return (is_src) ? BLEND_ONE : BLEND_ZERO;
444 break;
445 }
446 }
447
448 static void r700SetBlendState(GLcontext * ctx)
449 {
450 context_t *context = R700_CONTEXT(ctx);
451 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
452 int id = 0;
453 uint32_t blend_reg = 0, eqn, eqnA;
454
455 R600_STATECHANGE(context, blnd);
456
457 if (RGBA_LOGICOP_ENABLED(ctx) || !ctx->Color.BlendEnabled) {
458 SETfield(blend_reg,
459 BLEND_ONE, COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
460 SETfield(blend_reg,
461 BLEND_ZERO, COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
462 SETfield(blend_reg,
463 COMB_DST_PLUS_SRC, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
464 SETfield(blend_reg,
465 BLEND_ONE, ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
466 SETfield(blend_reg,
467 BLEND_ZERO, ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
468 SETfield(blend_reg,
469 COMB_DST_PLUS_SRC, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
470 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
471 r700->CB_BLEND_CONTROL.u32All = blend_reg;
472 else
473 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
474 return;
475 }
476
477 SETfield(blend_reg,
478 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
479 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
480 SETfield(blend_reg,
481 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
482 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
483
484 switch (ctx->Color.BlendEquationRGB) {
485 case GL_FUNC_ADD:
486 eqn = COMB_DST_PLUS_SRC;
487 break;
488 case GL_FUNC_SUBTRACT:
489 eqn = COMB_SRC_MINUS_DST;
490 break;
491 case GL_FUNC_REVERSE_SUBTRACT:
492 eqn = COMB_DST_MINUS_SRC;
493 break;
494 case GL_MIN:
495 eqn = COMB_MIN_DST_SRC;
496 SETfield(blend_reg,
497 BLEND_ONE,
498 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
499 SETfield(blend_reg,
500 BLEND_ONE,
501 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
502 break;
503 case GL_MAX:
504 eqn = COMB_MAX_DST_SRC;
505 SETfield(blend_reg,
506 BLEND_ONE,
507 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
508 SETfield(blend_reg,
509 BLEND_ONE,
510 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
511 break;
512
513 default:
514 fprintf(stderr,
515 "[%s:%u] Invalid RGB blend equation (0x%04x).\n",
516 __FUNCTION__, __LINE__, ctx->Color.BlendEquationRGB);
517 return;
518 }
519 SETfield(blend_reg,
520 eqn, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
521
522 SETfield(blend_reg,
523 blend_factor(ctx->Color.BlendSrcA, GL_TRUE),
524 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
525 SETfield(blend_reg,
526 blend_factor(ctx->Color.BlendDstA, GL_FALSE),
527 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
528
529 switch (ctx->Color.BlendEquationA) {
530 case GL_FUNC_ADD:
531 eqnA = COMB_DST_PLUS_SRC;
532 break;
533 case GL_FUNC_SUBTRACT:
534 eqnA = COMB_SRC_MINUS_DST;
535 break;
536 case GL_FUNC_REVERSE_SUBTRACT:
537 eqnA = COMB_DST_MINUS_SRC;
538 break;
539 case GL_MIN:
540 eqnA = COMB_MIN_DST_SRC;
541 SETfield(blend_reg,
542 BLEND_ONE,
543 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
544 SETfield(blend_reg,
545 BLEND_ONE,
546 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
547 break;
548 case GL_MAX:
549 eqnA = COMB_MAX_DST_SRC;
550 SETfield(blend_reg,
551 BLEND_ONE,
552 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
553 SETfield(blend_reg,
554 BLEND_ONE,
555 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
556 break;
557 default:
558 fprintf(stderr,
559 "[%s:%u] Invalid A blend equation (0x%04x).\n",
560 __FUNCTION__, __LINE__, ctx->Color.BlendEquationA);
561 return;
562 }
563
564 SETfield(blend_reg,
565 eqnA, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
566
567 SETbit(blend_reg, SEPARATE_ALPHA_BLEND_bit);
568
569 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
570 r700->CB_BLEND_CONTROL.u32All = blend_reg;
571 else {
572 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
573 SETbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit);
574 }
575 SETfield(r700->CB_COLOR_CONTROL.u32All, (1 << id),
576 TARGET_BLEND_ENABLE_shift, TARGET_BLEND_ENABLE_mask);
577
578 }
579
580 static void r700BlendEquationSeparate(GLcontext * ctx,
581 GLenum modeRGB, GLenum modeA) //-----------------
582 {
583 r700SetBlendState(ctx);
584 }
585
586 static void r700BlendFuncSeparate(GLcontext * ctx,
587 GLenum sfactorRGB, GLenum dfactorRGB,
588 GLenum sfactorA, GLenum dfactorA) //------------------------
589 {
590 r700SetBlendState(ctx);
591 }
592
593 /**
594 * Translate LogicOp enums into hardware representation.
595 */
596 static GLuint translate_logicop(GLenum logicop)
597 {
598 switch (logicop) {
599 case GL_CLEAR:
600 return 0x00;
601 case GL_SET:
602 return 0xff;
603 case GL_COPY:
604 return 0xcc;
605 case GL_COPY_INVERTED:
606 return 0x33;
607 case GL_NOOP:
608 return 0xaa;
609 case GL_INVERT:
610 return 0x55;
611 case GL_AND:
612 return 0x88;
613 case GL_NAND:
614 return 0x77;
615 case GL_OR:
616 return 0xee;
617 case GL_NOR:
618 return 0x11;
619 case GL_XOR:
620 return 0x66;
621 case GL_EQUIV:
622 return 0xaa;
623 case GL_AND_REVERSE:
624 return 0x44;
625 case GL_AND_INVERTED:
626 return 0x22;
627 case GL_OR_REVERSE:
628 return 0xdd;
629 case GL_OR_INVERTED:
630 return 0xbb;
631 default:
632 fprintf(stderr, "unknown blend logic operation %x\n", logicop);
633 return 0xcc;
634 }
635 }
636
637 /**
638 * Used internally to update the r300->hw hardware state to match the
639 * current OpenGL state.
640 */
641 static void r700SetLogicOpState(GLcontext *ctx)
642 {
643 context_t *context = R700_CONTEXT(ctx);
644 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
645
646 R600_STATECHANGE(context, blnd);
647
648 if (RGBA_LOGICOP_ENABLED(ctx))
649 SETfield(r700->CB_COLOR_CONTROL.u32All,
650 translate_logicop(ctx->Color.LogicOp), ROP3_shift, ROP3_mask);
651 else
652 SETfield(r700->CB_COLOR_CONTROL.u32All, 0xCC, ROP3_shift, ROP3_mask);
653 }
654
655 /**
656 * Called by Mesa when an application program changes the LogicOp state
657 * via glLogicOp.
658 */
659 static void r700LogicOpcode(GLcontext *ctx, GLenum logicop)
660 {
661 if (RGBA_LOGICOP_ENABLED(ctx))
662 r700SetLogicOpState(ctx);
663 }
664
665 static void r700UpdateCulling(GLcontext * ctx)
666 {
667 context_t *context = R700_CONTEXT(ctx);
668 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
669
670 R600_STATECHANGE(context, su);
671
672 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
673 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
674 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
675
676 if (ctx->Polygon.CullFlag)
677 {
678 switch (ctx->Polygon.CullFaceMode)
679 {
680 case GL_FRONT:
681 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
682 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
683 break;
684 case GL_BACK:
685 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
686 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
687 break;
688 case GL_FRONT_AND_BACK:
689 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
690 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
691 break;
692 default:
693 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
694 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
695 break;
696 }
697 }
698
699 switch (ctx->Polygon.FrontFace)
700 {
701 case GL_CW:
702 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
703 break;
704 case GL_CCW:
705 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
706 break;
707 default:
708 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); /* default: ccw */
709 break;
710 }
711 }
712
713 static void r700UpdateLineStipple(GLcontext * ctx)
714 {
715 context_t *context = R700_CONTEXT(ctx);
716 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
717
718 R600_STATECHANGE(context, sc);
719
720 if (ctx->Line.StippleFlag)
721 {
722 SETbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
723 }
724 else
725 {
726 CLEARbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
727 }
728 }
729
730 static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //------------------
731 {
732 context_t *context = R700_CONTEXT(ctx);
733
734 switch (cap) {
735 case GL_TEXTURE_1D:
736 case GL_TEXTURE_2D:
737 case GL_TEXTURE_3D:
738 /* empty */
739 break;
740 case GL_FOG:
741 /* empty */
742 break;
743 case GL_ALPHA_TEST:
744 r700SetAlphaState(ctx);
745 break;
746 case GL_COLOR_LOGIC_OP:
747 r700SetLogicOpState(ctx);
748 /* fall-through, because logic op overrides blending */
749 case GL_BLEND:
750 r700SetBlendState(ctx);
751 break;
752 case GL_CLIP_PLANE0:
753 case GL_CLIP_PLANE1:
754 case GL_CLIP_PLANE2:
755 case GL_CLIP_PLANE3:
756 case GL_CLIP_PLANE4:
757 case GL_CLIP_PLANE5:
758 r700SetClipPlaneState(ctx, cap, state);
759 break;
760 case GL_DEPTH_TEST:
761 r700SetDepthState(ctx);
762 break;
763 case GL_STENCIL_TEST:
764 r700SetStencilState(ctx, state);
765 break;
766 case GL_CULL_FACE:
767 r700UpdateCulling(ctx);
768 break;
769 case GL_POLYGON_OFFSET_POINT:
770 case GL_POLYGON_OFFSET_LINE:
771 case GL_POLYGON_OFFSET_FILL:
772 r700SetPolygonOffsetState(ctx, state);
773 break;
774 case GL_SCISSOR_TEST:
775 radeon_firevertices(&context->radeon);
776 context->radeon.state.scissor.enabled = state;
777 radeonUpdateScissor(ctx);
778 break;
779 case GL_LINE_STIPPLE:
780 r700UpdateLineStipple(ctx);
781 break;
782 default:
783 break;
784 }
785
786 }
787
788 /**
789 * Handle glColorMask()
790 */
791 static void r700ColorMask(GLcontext * ctx,
792 GLboolean r, GLboolean g, GLboolean b, GLboolean a) //------------------
793 {
794 context_t *context = R700_CONTEXT(ctx);
795 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
796 unsigned int mask = ((r ? 1 : 0) |
797 (g ? 2 : 0) |
798 (b ? 4 : 0) |
799 (a ? 8 : 0));
800
801 if (mask != r700->CB_TARGET_MASK.u32All) {
802 R600_STATECHANGE(context, cb);
803 SETfield(r700->CB_TARGET_MASK.u32All, mask, TARGET0_ENABLE_shift, TARGET0_ENABLE_mask);
804 }
805 }
806
807 /**
808 * Change the depth testing function.
809 *
810 * \note Mesa already filters redundant calls to this function.
811 */
812 static void r700DepthFunc(GLcontext * ctx, GLenum func) //--------------------
813 {
814 r700SetDepthState(ctx);
815 }
816
817 /**
818 * Enable/Disable depth writing.
819 *
820 * \note Mesa already filters redundant calls to this function.
821 */
822 static void r700DepthMask(GLcontext * ctx, GLboolean mask) //------------------
823 {
824 r700SetDepthState(ctx);
825 }
826
827 /**
828 * Change the culling mode.
829 *
830 * \note Mesa already filters redundant calls to this function.
831 */
832 static void r700CullFace(GLcontext * ctx, GLenum mode) //-----------------
833 {
834 r700UpdateCulling(ctx);
835 }
836
837 /* =============================================================
838 * Fog
839 */
840 static void r700Fogfv(GLcontext * ctx, GLenum pname, const GLfloat * param) //--------------
841 {
842 }
843
844 /**
845 * Change the polygon orientation.
846 *
847 * \note Mesa already filters redundant calls to this function.
848 */
849 static void r700FrontFace(GLcontext * ctx, GLenum mode) //------------------
850 {
851 r700UpdateCulling(ctx);
852 r700UpdatePolygonMode(ctx);
853 }
854
855 static void r700ShadeModel(GLcontext * ctx, GLenum mode) //--------------------
856 {
857 context_t *context = R700_CONTEXT(ctx);
858 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
859
860 R600_STATECHANGE(context, spi);
861
862 /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */
863 switch (mode) {
864 case GL_FLAT:
865 SETbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
866 break;
867 case GL_SMOOTH:
868 CLEARbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
869 break;
870 default:
871 return;
872 }
873 }
874
875 /* =============================================================
876 * Point state
877 */
878 static void r700PointSize(GLcontext * ctx, GLfloat size)
879 {
880 context_t *context = R700_CONTEXT(ctx);
881 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
882
883 R600_STATECHANGE(context, su);
884
885 /* We need to clamp to user defined range here, because
886 * the HW clamping happens only for per vertex point size. */
887 size = CLAMP(size, ctx->Point.MinSize, ctx->Point.MaxSize);
888
889 /* same size limits for AA, non-AA points */
890 size = CLAMP(size, ctx->Const.MinPointSize, ctx->Const.MaxPointSize);
891
892 /* format is 12.4 fixed point */
893 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 8.0),
894 PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask);
895 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 8.0),
896 PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask);
897
898 }
899
900 static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * param) //---------------
901 {
902 context_t *context = R700_CONTEXT(ctx);
903 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
904
905 R600_STATECHANGE(context, su);
906
907 /* format is 12.4 fixed point */
908 switch (pname) {
909 case GL_POINT_SIZE_MIN:
910 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MinSize * 8.0),
911 MIN_SIZE_shift, MIN_SIZE_mask);
912 break;
913 case GL_POINT_SIZE_MAX:
914 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MaxSize * 8.0),
915 MAX_SIZE_shift, MAX_SIZE_mask);
916 break;
917 case GL_POINT_DISTANCE_ATTENUATION:
918 break;
919 case GL_POINT_FADE_THRESHOLD_SIZE:
920 break;
921 default:
922 break;
923 }
924 }
925
926 static int translate_stencil_func(int func)
927 {
928 switch (func) {
929 case GL_NEVER:
930 return REF_NEVER;
931 case GL_LESS:
932 return REF_LESS;
933 case GL_EQUAL:
934 return REF_EQUAL;
935 case GL_LEQUAL:
936 return REF_LEQUAL;
937 case GL_GREATER:
938 return REF_GREATER;
939 case GL_NOTEQUAL:
940 return REF_NOTEQUAL;
941 case GL_GEQUAL:
942 return REF_GEQUAL;
943 case GL_ALWAYS:
944 return REF_ALWAYS;
945 }
946 return 0;
947 }
948
949 static int translate_stencil_op(int op)
950 {
951 switch (op) {
952 case GL_KEEP:
953 return STENCIL_KEEP;
954 case GL_ZERO:
955 return STENCIL_ZERO;
956 case GL_REPLACE:
957 return STENCIL_REPLACE;
958 case GL_INCR:
959 return STENCIL_INCR_CLAMP;
960 case GL_DECR:
961 return STENCIL_DECR_CLAMP;
962 case GL_INCR_WRAP_EXT:
963 return STENCIL_INCR_WRAP;
964 case GL_DECR_WRAP_EXT:
965 return STENCIL_DECR_WRAP;
966 case GL_INVERT:
967 return STENCIL_INVERT;
968 default:
969 WARN_ONCE("Do not know how to translate stencil op");
970 return STENCIL_KEEP;
971 }
972 return 0;
973 }
974
975 static void r700SetStencilState(GLcontext * ctx, GLboolean state)
976 {
977 context_t *context = R700_CONTEXT(ctx);
978 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
979 GLboolean hw_stencil = GL_FALSE;
980
981 if (ctx->DrawBuffer) {
982 struct radeon_renderbuffer *rrbStencil
983 = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
984 hw_stencil = (rrbStencil && rrbStencil->bo);
985 }
986
987 if (hw_stencil) {
988 R600_STATECHANGE(context, db);
989 if (state) {
990 SETbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
991 SETbit(r700->DB_DEPTH_CONTROL.u32All, BACKFACE_ENABLE_bit);
992 } else
993 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
994 }
995 }
996
997 static void r700StencilFuncSeparate(GLcontext * ctx, GLenum face,
998 GLenum func, GLint ref, GLuint mask) //---------------------
999 {
1000 context_t *context = R700_CONTEXT(ctx);
1001 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1002 const unsigned back = ctx->Stencil._BackFace;
1003
1004 R600_STATECHANGE(context, stencil);
1005 R600_STATECHANGE(context, db);
1006
1007 //front
1008 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.Ref[0],
1009 STENCILREF_shift, STENCILREF_mask);
1010 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.ValueMask[0],
1011 STENCILMASK_shift, STENCILMASK_mask);
1012
1013 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[0]),
1014 STENCILFUNC_shift, STENCILFUNC_mask);
1015
1016 //back
1017 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.Ref[back],
1018 STENCILREF_BF_shift, STENCILREF_BF_mask);
1019 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.ValueMask[back],
1020 STENCILMASK_BF_shift, STENCILMASK_BF_mask);
1021
1022 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[back]),
1023 STENCILFUNC_BF_shift, STENCILFUNC_BF_mask);
1024
1025 }
1026
1027 static void r700StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) //--------------
1028 {
1029 context_t *context = R700_CONTEXT(ctx);
1030 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1031 const unsigned back = ctx->Stencil._BackFace;
1032
1033 R600_STATECHANGE(context, stencil);
1034
1035 // front
1036 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.WriteMask[0],
1037 STENCILWRITEMASK_shift, STENCILWRITEMASK_mask);
1038
1039 // back
1040 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.WriteMask[back],
1041 STENCILWRITEMASK_BF_shift, STENCILWRITEMASK_BF_mask);
1042
1043 }
1044
1045 static void r700StencilOpSeparate(GLcontext * ctx, GLenum face,
1046 GLenum fail, GLenum zfail, GLenum zpass) //--------------------
1047 {
1048 context_t *context = R700_CONTEXT(ctx);
1049 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1050 const unsigned back = ctx->Stencil._BackFace;
1051
1052 R600_STATECHANGE(context, db);
1053
1054 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[0]),
1055 STENCILFAIL_shift, STENCILFAIL_mask);
1056 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[0]),
1057 STENCILZFAIL_shift, STENCILZFAIL_mask);
1058 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[0]),
1059 STENCILZPASS_shift, STENCILZPASS_mask);
1060
1061 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[back]),
1062 STENCILFAIL_BF_shift, STENCILFAIL_BF_mask);
1063 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[back]),
1064 STENCILZFAIL_BF_shift, STENCILZFAIL_BF_mask);
1065 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[back]),
1066 STENCILZPASS_BF_shift, STENCILZPASS_BF_mask);
1067 }
1068
1069 static void r700UpdateWindow(GLcontext * ctx, int id) //--------------------
1070 {
1071 context_t *context = R700_CONTEXT(ctx);
1072 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1073 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
1074 GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
1075 GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
1076 const GLfloat *v = ctx->Viewport._WindowMap.m;
1077 const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
1078 const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
1079 GLfloat y_scale, y_bias;
1080
1081 if (render_to_fbo) {
1082 y_scale = 1.0;
1083 y_bias = 0;
1084 } else {
1085 y_scale = -1.0;
1086 y_bias = yoffset;
1087 }
1088
1089 GLfloat sx = v[MAT_SX];
1090 GLfloat tx = v[MAT_TX] + xoffset;
1091 GLfloat sy = v[MAT_SY] * y_scale;
1092 GLfloat ty = (v[MAT_TY] * y_scale) + y_bias;
1093 GLfloat sz = v[MAT_SZ] * depthScale;
1094 GLfloat tz = v[MAT_TZ] * depthScale;
1095
1096 R600_STATECHANGE(context, vpt);
1097 R600_STATECHANGE(context, cl);
1098
1099 r700->viewport[id].PA_CL_VPORT_XSCALE.f32All = sx;
1100 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
1101
1102 r700->viewport[id].PA_CL_VPORT_YSCALE.f32All = sy;
1103 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
1104
1105 r700->viewport[id].PA_CL_VPORT_ZSCALE.f32All = sz;
1106 r700->viewport[id].PA_CL_VPORT_ZOFFSET.f32All = tz;
1107
1108 if (ctx->Transform.DepthClamp) {
1109 r700->viewport[id].PA_SC_VPORT_ZMIN_0.f32All = MIN2(ctx->Viewport.Near, ctx->Viewport.Far);
1110 r700->viewport[id].PA_SC_VPORT_ZMAX_0.f32All = MAX2(ctx->Viewport.Near, ctx->Viewport.Far);
1111 SETbit(r700->PA_CL_CLIP_CNTL.u32All, ZCLIP_NEAR_DISABLE_bit);
1112 SETbit(r700->PA_CL_CLIP_CNTL.u32All, ZCLIP_FAR_DISABLE_bit);
1113 } else {
1114 r700->viewport[id].PA_SC_VPORT_ZMIN_0.f32All = 0.0;
1115 r700->viewport[id].PA_SC_VPORT_ZMAX_0.f32All = 1.0;
1116 CLEARbit(r700->PA_CL_CLIP_CNTL.u32All, ZCLIP_NEAR_DISABLE_bit);
1117 CLEARbit(r700->PA_CL_CLIP_CNTL.u32All, ZCLIP_FAR_DISABLE_bit);
1118 }
1119
1120 r700->viewport[id].enabled = GL_TRUE;
1121
1122 r700SetScissor(context);
1123 }
1124
1125
1126 static void r700Viewport(GLcontext * ctx,
1127 GLint x,
1128 GLint y,
1129 GLsizei width,
1130 GLsizei height) //--------------------
1131 {
1132 r700UpdateWindow(ctx, 0);
1133
1134 radeon_viewport(ctx, x, y, width, height);
1135 }
1136
1137 static void r700DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) //-------------
1138 {
1139 r700UpdateWindow(ctx, 0);
1140 }
1141
1142 static void r700LineWidth(GLcontext * ctx, GLfloat widthf) //---------------
1143 {
1144 context_t *context = R700_CONTEXT(ctx);
1145 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1146 uint32_t lineWidth = (uint32_t)((widthf * 0.5) * (1 << 4));
1147
1148 R600_STATECHANGE(context, su);
1149
1150 if (lineWidth > 0xFFFF)
1151 lineWidth = 0xFFFF;
1152 SETfield(r700->PA_SU_LINE_CNTL.u32All,(uint16_t)lineWidth,
1153 PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
1154 }
1155
1156 static void r700LineStipple(GLcontext *ctx, GLint factor, GLushort pattern)
1157 {
1158 context_t *context = R700_CONTEXT(ctx);
1159 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1160
1161 R600_STATECHANGE(context, sc);
1162
1163 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, pattern, LINE_PATTERN_shift, LINE_PATTERN_mask);
1164 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, (factor-1), REPEAT_COUNT_shift, REPEAT_COUNT_mask);
1165 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, 1, AUTO_RESET_CNTL_shift, AUTO_RESET_CNTL_mask);
1166 }
1167
1168 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state)
1169 {
1170 context_t *context = R700_CONTEXT(ctx);
1171 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1172
1173 R600_STATECHANGE(context, su);
1174
1175 if (state) {
1176 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1177 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1178 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1179 } else {
1180 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1181 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1182 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1183 }
1184 }
1185
1186 static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) //--------------
1187 {
1188 context_t *context = R700_CONTEXT(ctx);
1189 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1190 GLfloat constant = units;
1191 GLchar depth = 0;
1192
1193 R600_STATECHANGE(context, poly);
1194
1195 switch (ctx->Visual.depthBits) {
1196 case 16:
1197 constant *= 4.0;
1198 depth = -16;
1199 break;
1200 case 24:
1201 constant *= 2.0;
1202 depth = -24;
1203 break;
1204 }
1205
1206 factor *= 12.0;
1207 SETfield(r700->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All, depth,
1208 POLY_OFFSET_NEG_NUM_DB_BITS_shift, POLY_OFFSET_NEG_NUM_DB_BITS_mask);
1209 //r700->PA_SU_POLY_OFFSET_CLAMP.f32All = constant; //???
1210 r700->PA_SU_POLY_OFFSET_FRONT_SCALE.f32All = factor;
1211 r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.f32All = constant;
1212 r700->PA_SU_POLY_OFFSET_BACK_SCALE.f32All = factor;
1213 r700->PA_SU_POLY_OFFSET_BACK_OFFSET.f32All = constant;
1214 }
1215
1216 static void r700UpdatePolygonMode(GLcontext * ctx)
1217 {
1218 context_t *context = R700_CONTEXT(ctx);
1219 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1220
1221 R600_STATECHANGE(context, su);
1222
1223 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DISABLE_POLY_MODE, POLY_MODE_shift, POLY_MODE_mask);
1224
1225 /* Only do something if a polygon mode is wanted, default is GL_FILL */
1226 if (ctx->Polygon.FrontMode != GL_FILL ||
1227 ctx->Polygon.BackMode != GL_FILL) {
1228 GLenum f, b;
1229
1230 /* Handle GL_CW (clock wise and GL_CCW (counter clock wise)
1231 * correctly by selecting the correct front and back face
1232 */
1233 if (ctx->Polygon.FrontFace == GL_CCW) {
1234 f = ctx->Polygon.FrontMode;
1235 b = ctx->Polygon.BackMode;
1236 } else {
1237 f = ctx->Polygon.BackMode;
1238 b = ctx->Polygon.FrontMode;
1239 }
1240
1241 /* Enable polygon mode */
1242 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DUAL_MODE, POLY_MODE_shift, POLY_MODE_mask);
1243
1244 switch (f) {
1245 case GL_LINE:
1246 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1247 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1248 break;
1249 case GL_POINT:
1250 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1251 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1252 break;
1253 case GL_FILL:
1254 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1255 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1256 break;
1257 }
1258
1259 switch (b) {
1260 case GL_LINE:
1261 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1262 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1263 break;
1264 case GL_POINT:
1265 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1266 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1267 break;
1268 case GL_FILL:
1269 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1270 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1271 break;
1272 }
1273 }
1274 }
1275
1276 static void r700PolygonMode(GLcontext * ctx, GLenum face, GLenum mode) //------------------
1277 {
1278 (void)face;
1279 (void)mode;
1280
1281 r700UpdatePolygonMode(ctx);
1282 }
1283
1284 static void r700RenderMode(GLcontext * ctx, GLenum mode) //---------------------
1285 {
1286 }
1287
1288 static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
1289 {
1290 context_t *context = R700_CONTEXT(ctx);
1291 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1292 GLint p;
1293 GLint *ip;
1294
1295 p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
1296 ip = (GLint *)ctx->Transform._ClipUserPlane[p];
1297
1298 R600_STATECHANGE(context, ucp);
1299
1300 r700->ucp[p].PA_CL_UCP_0_X.u32All = ip[0];
1301 r700->ucp[p].PA_CL_UCP_0_Y.u32All = ip[1];
1302 r700->ucp[p].PA_CL_UCP_0_Z.u32All = ip[2];
1303 r700->ucp[p].PA_CL_UCP_0_W.u32All = ip[3];
1304 }
1305
1306 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state)
1307 {
1308 context_t *context = R700_CONTEXT(ctx);
1309 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1310 GLuint p;
1311
1312 p = cap - GL_CLIP_PLANE0;
1313
1314 R600_STATECHANGE(context, cl);
1315
1316 if (state) {
1317 r700->PA_CL_CLIP_CNTL.u32All |= (UCP_ENA_0_bit << p);
1318 r700->ucp[p].enabled = GL_TRUE;
1319 r700ClipPlane(ctx, cap, NULL);
1320 } else {
1321 r700->PA_CL_CLIP_CNTL.u32All &= ~(UCP_ENA_0_bit << p);
1322 r700->ucp[p].enabled = GL_FALSE;
1323 }
1324 }
1325
1326 void r700SetScissor(context_t *context) //---------------
1327 {
1328 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1329 unsigned x1, y1, x2, y2;
1330 int id = 0;
1331 struct radeon_renderbuffer *rrb;
1332
1333 rrb = radeon_get_colorbuffer(&context->radeon);
1334 if (!rrb || !rrb->bo) {
1335 return;
1336 }
1337 if (context->radeon.state.scissor.enabled) {
1338 x1 = context->radeon.state.scissor.rect.x1;
1339 y1 = context->radeon.state.scissor.rect.y1;
1340 x2 = context->radeon.state.scissor.rect.x2;
1341 y2 = context->radeon.state.scissor.rect.y2;
1342 /* r600 has exclusive BR scissors */
1343 if (context->radeon.radeonScreen->kernel_mm) {
1344 x2++;
1345 y2++;
1346 }
1347 } else {
1348 if (context->radeon.radeonScreen->driScreen->dri2.enabled) {
1349 x1 = 0;
1350 y1 = 0;
1351 x2 = rrb->base.Width;
1352 y2 = rrb->base.Height;
1353 } else {
1354 x1 = rrb->dPriv->x;
1355 y1 = rrb->dPriv->y;
1356 x2 = rrb->dPriv->x + rrb->dPriv->w;
1357 y2 = rrb->dPriv->y + rrb->dPriv->h;
1358 }
1359 }
1360
1361 R600_STATECHANGE(context, scissor);
1362
1363 /* screen */
1364 SETbit(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1365 SETfield(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, x1,
1366 PA_SC_SCREEN_SCISSOR_TL__TL_X_shift, PA_SC_SCREEN_SCISSOR_TL__TL_X_mask);
1367 SETfield(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, y1,
1368 PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift, PA_SC_SCREEN_SCISSOR_TL__TL_Y_mask);
1369
1370 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, x2,
1371 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask);
1372 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, y2,
1373 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask);
1374
1375 /* window */
1376 SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1377 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, x1,
1378 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask);
1379 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, y1,
1380 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask);
1381
1382 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, x2,
1383 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask);
1384 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, y2,
1385 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask);
1386
1387
1388 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, x1,
1389 PA_SC_CLIPRECT_0_TL__TL_X_shift, PA_SC_CLIPRECT_0_TL__TL_X_mask);
1390 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, y1,
1391 PA_SC_CLIPRECT_0_TL__TL_Y_shift, PA_SC_CLIPRECT_0_TL__TL_Y_mask);
1392 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, x2,
1393 PA_SC_CLIPRECT_0_BR__BR_X_shift, PA_SC_CLIPRECT_0_BR__BR_X_mask);
1394 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, y2,
1395 PA_SC_CLIPRECT_0_BR__BR_Y_shift, PA_SC_CLIPRECT_0_BR__BR_Y_mask);
1396
1397 r700->PA_SC_CLIPRECT_1_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1398 r700->PA_SC_CLIPRECT_1_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1399 r700->PA_SC_CLIPRECT_2_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1400 r700->PA_SC_CLIPRECT_2_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1401 r700->PA_SC_CLIPRECT_3_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1402 r700->PA_SC_CLIPRECT_3_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1403
1404 /* more....2d clip */
1405 SETbit(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1406 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, x1,
1407 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask);
1408 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, y1,
1409 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask);
1410 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, x2,
1411 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask);
1412 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, y2,
1413 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask);
1414
1415 SETbit(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1416 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, x1,
1417 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask);
1418 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, y1,
1419 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask);
1420 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, x2,
1421 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask);
1422 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, y2,
1423 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask);
1424
1425 r700->viewport[id].enabled = GL_TRUE;
1426 }
1427
1428 static void r700InitSQConfig(GLcontext * ctx)
1429 {
1430 context_t *context = R700_CONTEXT(ctx);
1431 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1432 int ps_prio;
1433 int vs_prio;
1434 int gs_prio;
1435 int es_prio;
1436 int num_ps_gprs;
1437 int num_vs_gprs;
1438 int num_gs_gprs;
1439 int num_es_gprs;
1440 int num_temp_gprs;
1441 int num_ps_threads;
1442 int num_vs_threads;
1443 int num_gs_threads;
1444 int num_es_threads;
1445 int num_ps_stack_entries;
1446 int num_vs_stack_entries;
1447 int num_gs_stack_entries;
1448 int num_es_stack_entries;
1449
1450 R600_STATECHANGE(context, sq);
1451
1452 // SQ
1453 ps_prio = 0;
1454 vs_prio = 1;
1455 gs_prio = 2;
1456 es_prio = 3;
1457 switch (context->radeon.radeonScreen->chip_family) {
1458 case CHIP_FAMILY_R600:
1459 num_ps_gprs = 192;
1460 num_vs_gprs = 56;
1461 num_temp_gprs = 4;
1462 num_gs_gprs = 0;
1463 num_es_gprs = 0;
1464 num_ps_threads = 136;
1465 num_vs_threads = 48;
1466 num_gs_threads = 4;
1467 num_es_threads = 4;
1468 num_ps_stack_entries = 128;
1469 num_vs_stack_entries = 128;
1470 num_gs_stack_entries = 0;
1471 num_es_stack_entries = 0;
1472 break;
1473 case CHIP_FAMILY_RV630:
1474 case CHIP_FAMILY_RV635:
1475 num_ps_gprs = 84;
1476 num_vs_gprs = 36;
1477 num_temp_gprs = 4;
1478 num_gs_gprs = 0;
1479 num_es_gprs = 0;
1480 num_ps_threads = 144;
1481 num_vs_threads = 40;
1482 num_gs_threads = 4;
1483 num_es_threads = 4;
1484 num_ps_stack_entries = 40;
1485 num_vs_stack_entries = 40;
1486 num_gs_stack_entries = 32;
1487 num_es_stack_entries = 16;
1488 break;
1489 case CHIP_FAMILY_RV610:
1490 case CHIP_FAMILY_RV620:
1491 case CHIP_FAMILY_RS780:
1492 case CHIP_FAMILY_RS880:
1493 default:
1494 num_ps_gprs = 84;
1495 num_vs_gprs = 36;
1496 num_temp_gprs = 4;
1497 num_gs_gprs = 0;
1498 num_es_gprs = 0;
1499 num_ps_threads = 136;
1500 num_vs_threads = 48;
1501 num_gs_threads = 4;
1502 num_es_threads = 4;
1503 num_ps_stack_entries = 40;
1504 num_vs_stack_entries = 40;
1505 num_gs_stack_entries = 32;
1506 num_es_stack_entries = 16;
1507 break;
1508 case CHIP_FAMILY_RV670:
1509 num_ps_gprs = 144;
1510 num_vs_gprs = 40;
1511 num_temp_gprs = 4;
1512 num_gs_gprs = 0;
1513 num_es_gprs = 0;
1514 num_ps_threads = 136;
1515 num_vs_threads = 48;
1516 num_gs_threads = 4;
1517 num_es_threads = 4;
1518 num_ps_stack_entries = 40;
1519 num_vs_stack_entries = 40;
1520 num_gs_stack_entries = 32;
1521 num_es_stack_entries = 16;
1522 break;
1523 case CHIP_FAMILY_RV770:
1524 num_ps_gprs = 192;
1525 num_vs_gprs = 56;
1526 num_temp_gprs = 4;
1527 num_gs_gprs = 0;
1528 num_es_gprs = 0;
1529 num_ps_threads = 188;
1530 num_vs_threads = 60;
1531 num_gs_threads = 0;
1532 num_es_threads = 0;
1533 num_ps_stack_entries = 256;
1534 num_vs_stack_entries = 256;
1535 num_gs_stack_entries = 0;
1536 num_es_stack_entries = 0;
1537 break;
1538 case CHIP_FAMILY_RV730:
1539 case CHIP_FAMILY_RV740:
1540 num_ps_gprs = 84;
1541 num_vs_gprs = 36;
1542 num_temp_gprs = 4;
1543 num_gs_gprs = 0;
1544 num_es_gprs = 0;
1545 num_ps_threads = 188;
1546 num_vs_threads = 60;
1547 num_gs_threads = 0;
1548 num_es_threads = 0;
1549 num_ps_stack_entries = 128;
1550 num_vs_stack_entries = 128;
1551 num_gs_stack_entries = 0;
1552 num_es_stack_entries = 0;
1553 break;
1554 case CHIP_FAMILY_RV710:
1555 num_ps_gprs = 192;
1556 num_vs_gprs = 56;
1557 num_temp_gprs = 4;
1558 num_gs_gprs = 0;
1559 num_es_gprs = 0;
1560 num_ps_threads = 144;
1561 num_vs_threads = 48;
1562 num_gs_threads = 0;
1563 num_es_threads = 0;
1564 num_ps_stack_entries = 128;
1565 num_vs_stack_entries = 128;
1566 num_gs_stack_entries = 0;
1567 num_es_stack_entries = 0;
1568 break;
1569 }
1570
1571 r700->sq_config.SQ_CONFIG.u32All = 0;
1572 if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
1573 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
1574 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
1575 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) ||
1576 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
1577 CLEARbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1578 else
1579 SETbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1580 SETbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit);
1581 SETbit(r700->sq_config.SQ_CONFIG.u32All, ALU_INST_PREFER_VECTOR_bit);
1582 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, PS_PRIO_shift, PS_PRIO_mask);
1583 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, VS_PRIO_shift, VS_PRIO_mask);
1584 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, GS_PRIO_shift, GS_PRIO_mask);
1585 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, ES_PRIO_shift, ES_PRIO_mask);
1586
1587 r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All = 0;
1588 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_ps_gprs, NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
1589 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_vs_gprs, NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
1590 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_temp_gprs,
1591 NUM_CLAUSE_TEMP_GPRS_shift, NUM_CLAUSE_TEMP_GPRS_mask);
1592
1593 r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All = 0;
1594 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_gs_gprs, NUM_GS_GPRS_shift, NUM_GS_GPRS_mask);
1595 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_es_gprs, NUM_ES_GPRS_shift, NUM_ES_GPRS_mask);
1596
1597 r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All = 0;
1598 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_ps_threads,
1599 NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
1600 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_vs_threads,
1601 NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
1602 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_gs_threads,
1603 NUM_GS_THREADS_shift, NUM_GS_THREADS_mask);
1604 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_es_threads,
1605 NUM_ES_THREADS_shift, NUM_ES_THREADS_mask);
1606
1607 r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All = 0;
1608 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_ps_stack_entries,
1609 NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
1610 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_vs_stack_entries,
1611 NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
1612
1613 r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All = 0;
1614 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_gs_stack_entries,
1615 NUM_GS_STACK_ENTRIES_shift, NUM_GS_STACK_ENTRIES_mask);
1616 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_es_stack_entries,
1617 NUM_ES_STACK_ENTRIES_shift, NUM_ES_STACK_ENTRIES_mask);
1618
1619 }
1620
1621 /**
1622 * Calculate initial hardware state and register state functions.
1623 * Assumes that the command buffer and state atoms have been
1624 * initialized already.
1625 */
1626 void r700InitState(GLcontext * ctx) //-------------------
1627 {
1628 context_t *context = R700_CONTEXT(ctx);
1629 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1630 int id = 0;
1631
1632 radeon_firevertices(&context->radeon);
1633
1634 r700->TA_CNTL_AUX.u32All = 0;
1635 SETfield(r700->TA_CNTL_AUX.u32All, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask);
1636 r700->VC_ENHANCE.u32All = 0;
1637 r700->DB_WATERMARKS.u32All = 0;
1638 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_FREE_shift, DEPTH_FREE_mask);
1639 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_FLUSH_shift, DEPTH_FLUSH_mask);
1640 SETfield(r700->DB_WATERMARKS.u32All, 0, FORCE_SUMMARIZE_shift, FORCE_SUMMARIZE_mask);
1641 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_PENDING_FREE_shift, DEPTH_PENDING_FREE_mask);
1642 r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All = 0;
1643 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1644 SETfield(r700->TA_CNTL_AUX.u32All, 3, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1645 r700->DB_DEBUG.u32All = 0x82000000;
1646 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1647 } else {
1648 SETfield(r700->TA_CNTL_AUX.u32All, 2, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1649 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1650 SETbit(r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All, VS_PC_LIMIT_ENABLE_bit);
1651 }
1652
1653 /* Turn off vgt reuse */
1654 r700->VGT_REUSE_OFF.u32All = 0;
1655 SETbit(r700->VGT_REUSE_OFF.u32All, REUSE_OFF_bit);
1656
1657 /* Specify offsetting and clamp values for vertices */
1658 r700->VGT_MAX_VTX_INDX.u32All = 0xFFFFFF;
1659 r700->VGT_MIN_VTX_INDX.u32All = 0;
1660 r700->VGT_INDX_OFFSET.u32All = 0;
1661
1662 /* default shader connections. */
1663 r700->SPI_VS_OUT_ID_0.u32All = 0x03020100;
1664 r700->SPI_VS_OUT_ID_1.u32All = 0x07060504;
1665 r700->SPI_VS_OUT_ID_2.u32All = 0x0b0a0908;
1666 r700->SPI_VS_OUT_ID_3.u32All = 0x0f0e0d0c;
1667
1668 r700->SPI_THREAD_GROUPING.u32All = 0;
1669 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
1670 SETfield(r700->SPI_THREAD_GROUPING.u32All, 1, PS_GROUPING_shift, PS_GROUPING_mask);
1671
1672 /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
1673 r700->PA_SC_CLIPRECT_RULE.u32All = 0;
1674 SETfield(r700->PA_SC_CLIPRECT_RULE.u32All, CLIP_RULE_mask, CLIP_RULE_shift, CLIP_RULE_mask);
1675
1676 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1677 r700->PA_SC_EDGERULE.u32All = 0;
1678 else
1679 r700->PA_SC_EDGERULE.u32All = 0xAAAAAAAA;
1680
1681 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1682 r700->PA_SC_MODE_CNTL.u32All = 0;
1683 SETbit(r700->PA_SC_MODE_CNTL.u32All, WALK_ORDER_ENABLE_bit);
1684 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1685 } else {
1686 r700->PA_SC_MODE_CNTL.u32All = 0x00500000;
1687 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_REZ_ENABLE_bit);
1688 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1689 }
1690
1691 /* Do scale XY and Z by 1/W0. */
1692 r700->bEnablePerspective = GL_TRUE;
1693 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
1694 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
1695 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
1696
1697 /* Enable viewport scaling for all three axis */
1698 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_SCALE_ENA_bit);
1699 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_OFFSET_ENA_bit);
1700 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_SCALE_ENA_bit);
1701 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_OFFSET_ENA_bit);
1702 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_SCALE_ENA_bit);
1703 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_OFFSET_ENA_bit);
1704
1705 /* GL uses last vtx for flat shading components */
1706 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
1707
1708 /* Set up vertex control */
1709 r700->PA_SU_VTX_CNTL.u32All = 0;
1710 CLEARfield(r700->PA_SU_VTX_CNTL.u32All, QUANT_MODE_mask);
1711 SETbit(r700->PA_SU_VTX_CNTL.u32All, PIX_CENTER_bit);
1712 SETfield(r700->PA_SU_VTX_CNTL.u32All, X_ROUND_TO_EVEN,
1713 PA_SU_VTX_CNTL__ROUND_MODE_shift, PA_SU_VTX_CNTL__ROUND_MODE_mask);
1714
1715 /* to 1.0 = no guard band */
1716 r700->PA_CL_GB_VERT_CLIP_ADJ.u32All = 0x3F800000; /* 1.0 */
1717 r700->PA_CL_GB_VERT_DISC_ADJ.u32All = 0x3F800000;
1718 r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All = 0x3F800000;
1719 r700->PA_CL_GB_HORZ_DISC_ADJ.u32All = 0x3F800000;
1720
1721 /* Enable all samples for multi-sample anti-aliasing */
1722 r700->PA_SC_AA_MASK.u32All = 0xFFFFFFFF;
1723 /* Turn off AA */
1724 r700->PA_SC_AA_CONFIG.u32All = 0;
1725
1726 r700->SX_MISC.u32All = 0;
1727
1728 r700InitSQConfig(ctx);
1729
1730 r700ColorMask(ctx,
1731 ctx->Color.ColorMask[RCOMP],
1732 ctx->Color.ColorMask[GCOMP],
1733 ctx->Color.ColorMask[BCOMP],
1734 ctx->Color.ColorMask[ACOMP]);
1735
1736 r700Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test);
1737 r700DepthMask(ctx, ctx->Depth.Mask);
1738 r700DepthFunc(ctx, ctx->Depth.Func);
1739 r700->DB_DEPTH_CLEAR.u32All = 0x3F800000;
1740 SETbit(r700->DB_RENDER_CONTROL.u32All, STENCIL_COMPRESS_DISABLE_bit);
1741 SETbit(r700->DB_RENDER_CONTROL.u32All, DEPTH_COMPRESS_DISABLE_bit);
1742 r700SetDBRenderState(ctx);
1743
1744 r700->DB_ALPHA_TO_MASK.u32All = 0;
1745 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask);
1746 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET1_shift, ALPHA_TO_MASK_OFFSET1_mask);
1747 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET2_shift, ALPHA_TO_MASK_OFFSET2_mask);
1748 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET3_shift, ALPHA_TO_MASK_OFFSET3_mask);
1749
1750 /* stencil */
1751 r700Enable(ctx, GL_STENCIL_TEST, ctx->Stencil._Enabled);
1752 r700StencilMaskSeparate(ctx, 0, ctx->Stencil.WriteMask[0]);
1753 r700StencilFuncSeparate(ctx, 0, ctx->Stencil.Function[0],
1754 ctx->Stencil.Ref[0], ctx->Stencil.ValueMask[0]);
1755 r700StencilOpSeparate(ctx, 0, ctx->Stencil.FailFunc[0],
1756 ctx->Stencil.ZFailFunc[0],
1757 ctx->Stencil.ZPassFunc[0]);
1758
1759 r700UpdateCulling(ctx);
1760
1761 r700SetBlendState(ctx);
1762 r700SetLogicOpState(ctx);
1763
1764 r700AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef);
1765 r700Enable(ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled);
1766
1767 r700PointSize(ctx, 1.0);
1768
1769 CLEARfield(r700->PA_SU_POINT_MINMAX.u32All, MIN_SIZE_mask);
1770 SETfield(r700->PA_SU_POINT_MINMAX.u32All, 0x8000, MAX_SIZE_shift, MAX_SIZE_mask);
1771
1772 r700LineWidth(ctx, 1.0);
1773
1774 r700->PA_SC_LINE_CNTL.u32All = 0;
1775 CLEARbit(r700->PA_SC_LINE_CNTL.u32All, EXPAND_LINE_WIDTH_bit);
1776 SETbit(r700->PA_SC_LINE_CNTL.u32All, LAST_PIXEL_bit);
1777
1778 r700ShadeModel(ctx, ctx->Light.ShadeModel);
1779 r700PolygonMode(ctx, GL_FRONT, ctx->Polygon.FrontMode);
1780 r700PolygonMode(ctx, GL_BACK, ctx->Polygon.BackMode);
1781 r700PolygonOffset(ctx, ctx->Polygon.OffsetFactor,
1782 ctx->Polygon.OffsetUnits);
1783 r700Enable(ctx, GL_POLYGON_OFFSET_POINT, ctx->Polygon.OffsetPoint);
1784 r700Enable(ctx, GL_POLYGON_OFFSET_LINE, ctx->Polygon.OffsetLine);
1785 r700Enable(ctx, GL_POLYGON_OFFSET_FILL, ctx->Polygon.OffsetFill);
1786
1787 /* CB */
1788 r700BlendColor(ctx, ctx->Color.BlendColor);
1789
1790 r700->CB_CLEAR_RED_R6XX.f32All = 1.0; //r6xx only
1791 r700->CB_CLEAR_GREEN_R6XX.f32All = 0.0; //r6xx only
1792 r700->CB_CLEAR_BLUE_R6XX.f32All = 1.0; //r6xx only
1793 r700->CB_CLEAR_ALPHA_R6XX.f32All = 1.0; //r6xx only
1794 r700->CB_FOG_RED_R6XX.u32All = 0; //r6xx only
1795 r700->CB_FOG_GREEN_R6XX.u32All = 0; //r6xx only
1796 r700->CB_FOG_BLUE_R6XX.u32All = 0; //r6xx only
1797
1798 /* Disable color compares */
1799 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1800 CLRCMP_FCN_SRC_shift, CLRCMP_FCN_SRC_mask);
1801 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1802 CLRCMP_FCN_DST_shift, CLRCMP_FCN_DST_mask);
1803 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_SEL_SRC,
1804 CLRCMP_FCN_SEL_shift, CLRCMP_FCN_SEL_mask);
1805
1806 /* Zero out source */
1807 r700->CB_CLRCMP_SRC.u32All = 0x00000000;
1808
1809 /* Put a compare color in for error checking */
1810 r700->CB_CLRCMP_DST.u32All = 0x000000FF;
1811
1812 /* Set up color compare mask */
1813 r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF;
1814
1815 /* screen/window/view */
1816 SETfield(r700->CB_SHADER_MASK.u32All, 0xF, (4 * id), OUTPUT0_ENABLE_mask);
1817
1818 context->radeon.hw.all_dirty = GL_TRUE;
1819
1820 }
1821
1822 void r700InitStateFuncs(struct dd_function_table *functions) //-----------------
1823 {
1824 functions->UpdateState = r700InvalidateState;
1825 functions->AlphaFunc = r700AlphaFunc;
1826 functions->BlendColor = r700BlendColor;
1827 functions->BlendEquationSeparate = r700BlendEquationSeparate;
1828 functions->BlendFuncSeparate = r700BlendFuncSeparate;
1829 functions->Enable = r700Enable;
1830 functions->ColorMask = r700ColorMask;
1831 functions->DepthFunc = r700DepthFunc;
1832 functions->DepthMask = r700DepthMask;
1833 functions->CullFace = r700CullFace;
1834 functions->Fogfv = r700Fogfv;
1835 functions->FrontFace = r700FrontFace;
1836 functions->ShadeModel = r700ShadeModel;
1837 functions->LogicOpcode = r700LogicOpcode;
1838
1839 /* ARB_point_parameters */
1840 functions->PointParameterfv = r700PointParameter;
1841
1842 /* Stencil related */
1843 functions->StencilFuncSeparate = r700StencilFuncSeparate;
1844 functions->StencilMaskSeparate = r700StencilMaskSeparate;
1845 functions->StencilOpSeparate = r700StencilOpSeparate;
1846
1847 /* Viewport related */
1848 functions->Viewport = r700Viewport;
1849 functions->DepthRange = r700DepthRange;
1850 functions->PointSize = r700PointSize;
1851 functions->LineWidth = r700LineWidth;
1852 functions->LineStipple = r700LineStipple;
1853
1854 functions->PolygonOffset = r700PolygonOffset;
1855 functions->PolygonMode = r700PolygonMode;
1856
1857 functions->RenderMode = r700RenderMode;
1858
1859 functions->ClipPlane = r700ClipPlane;
1860
1861 functions->Scissor = radeonScissor;
1862
1863 functions->DrawBuffer = radeonDrawBuffer;
1864 functions->ReadBuffer = radeonReadBuffer;
1865
1866 }
1867