projects / mesa.git / blob
? search:


4341f33665126619ac364e41215f651fa1206b23
[mesa.git] / src / mesa / drivers / dri / r600 / r700_state.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/dd.h"
34 #include "main/simple_list.h"
35
36 #include "tnl/tnl.h"
37 #include "tnl/t_pipeline.h"
38 #include "tnl/t_vp_build.h"
39 #include "swrast/swrast.h"
40 #include "swrast_setup/swrast_setup.h"
41 #include "main/api_arrayelt.h"
42 #include "main/state.h"
43 #include "main/framebuffer.h"
44
45 #include "shader/prog_parameter.h"
46 #include "shader/prog_statevars.h"
47 #include "vbo/vbo.h"
48 #include "main/texformat.h"
49
50 #include "r600_context.h"
51
52 #include "r700_chip.h"
53 #include "r700_state.h"
54
55 #if 0 /* to be enabled */
56 #include "r700_fragprog.h"
57 #include "r700_vertprog.h"
58 #endif /* to be enabled */
59
60 void r700SetDefaultStates(context_t *context) //--------------------
61 {
62
63 }
64
65 void r700UpdateShaders (GLcontext * ctx) //----------------------------------
66 {
67 context_t *context = R700_CONTEXT(ctx);
68
69 GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
70 GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
71 #if 0 /* to be enabled */
72 struct r700_vertex_program *vp;
73 int i;
74
75 if (context->NewGLState)
76 {
77 context->NewGLState = 0;
78
79 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++)
80 {
81 /* mat states from state var not array for sw */
82 dummy_attrib[i].stride = 0;
83
84 temp_attrib[i] = TNL_CONTEXT(ctx)->vb.AttribPtr[i];
85 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = &(dummy_attrib[i]);
86 }
87
88 _tnl_UpdateFixedFunctionProgram(ctx);
89
90 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++)
91 {
92 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = temp_attrib[i];
93 }
94
95 r700SelectVertexShader(ctx);
96 vp = (struct r700_vertex_program *)ctx->VertexProgram._Current;
97
98 if (vp->translated == GL_FALSE)
99 {
100 // TODO
101 //fprintf(stderr, "Failing back to sw-tcl\n");
102 //hw_tcl_on = future_hw_tcl_on = 0;
103 //r300ResetHwState(rmesa);
104 //
105 r700UpdateStateParameters(ctx, _NEW_PROGRAM);
106 return;
107 }
108 }
109
110 r700UpdateStateParameters(ctx, _NEW_PROGRAM);
111 #endif /* to be enabled */
112 }
113
114 /*
115 * To correctly position primitives:
116 */
117 void r700UpdateViewportOffset(GLcontext * ctx) //------------------
118 {
119 }
120
121 /**
122 * Tell the card where to render (offset, pitch).
123 * Effected by glDrawBuffer, etc
124 */
125 void r700UpdateDrawBuffer(GLcontext * ctx) /* TODO */ //---------------------
126 {
127 #if 0 /* to be enabled */
128 context_t *context = R700_CONTEXT(ctx);
129
130 switch (ctx->DrawBuffer->_ColorDrawBufferIndexes[0])
131 {
132 case BUFFER_FRONT_LEFT:
133 context->target.rt = context->screen->frontBuffer;
134 break;
135 case BUFFER_BACK_LEFT:
136 context->target.rt = context->screen->backBuffer;
137 break;
138 default:
139 memset (&context->target.rt, sizeof(context->target.rt), 0);
140 }
141 #endif /* to be enabled */
142 }
143
144 static void r700FetchStateParameter(GLcontext * ctx,
145 const gl_state_index state[STATE_LENGTH],
146 GLfloat * value)
147 {
148 context_t *context = R700_CONTEXT(ctx);
149
150 /* TODO */
151 }
152
153 void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state) //--------------------
154 {
155 #if 0 /* to be enabled */
156 struct r700_fragment_program *fp;
157 struct gl_program_parameter_list *paramList;
158 GLuint i;
159
160 if (!(new_state & (_NEW_BUFFERS | _NEW_PROGRAM)))
161 return;
162
163 fp = (struct r700_fragment_program *)ctx->FragmentProgram._Current;
164 if (!fp)
165 {
166 return;
167 }
168
169 paramList = fp->mesa_program.Base.Parameters;
170
171 if (!paramList)
172 {
173 return;
174 }
175
176 for (i = 0; i < paramList->NumParameters; i++)
177 {
178 if (paramList->Parameters[i].Type == PROGRAM_STATE_VAR)
179 {
180 r700FetchStateParameter(ctx,
181 paramList->Parameters[i].
182 StateIndexes,
183 paramList->ParameterValues[i]);
184 }
185 }
186 #endif /* to be enabled */
187 }
188
189 /**
190 * Called by Mesa after an internal state update.
191 */
192 static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //-------------------
193 {
194 #if 0 /* to be enabled */
195 context_t *context = R700_CONTEXT(ctx);
196
197 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj);
198
199 _swrast_InvalidateState(ctx, new_state);
200 _swsetup_InvalidateState(ctx, new_state);
201 _vbo_InvalidateState(ctx, new_state);
202 _tnl_InvalidateState(ctx, new_state);
203 _ae_invalidate_state(ctx, new_state);
204
205 if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL))
206 {
207 r700UpdateDrawBuffer(ctx);
208 }
209
210 r700UpdateStateParameters(ctx, new_state);
211
212 if(GL_TRUE == context->bEnablePerspective)
213 {
214 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
215 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
216 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
217
218 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
219
220 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
221 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
222 }
223 else
224 {
225 /* For orthogonal case. */
226 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
227 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
228
229 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
230
231 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
232 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
233 }
234
235 context->NewGLState |= new_state;
236 #endif /* to be enabled */
237 }
238
239 static void r700SetDepthState(GLcontext * ctx)
240 {
241 context_t *context = R700_CONTEXT(ctx);
242
243 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj);
244
245 if (ctx->Depth.Test)
246 {
247 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
248 if (ctx->Depth.Mask)
249 {
250 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
251 }
252 else
253 {
254 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
255 }
256
257 switch (ctx->Depth.Func)
258 {
259 case GL_NEVER:
260 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NEVER,
261 ZFUNC_shift, ZFUNC_mask);
262 break;
263 case GL_LESS:
264 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LESS,
265 ZFUNC_shift, ZFUNC_mask);
266 break;
267 case GL_EQUAL:
268 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_EQUAL,
269 ZFUNC_shift, ZFUNC_mask);
270 break;
271 case GL_LEQUAL:
272 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LEQUAL,
273 ZFUNC_shift, ZFUNC_mask);
274 break;
275 case GL_GREATER:
276 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GREATER,
277 ZFUNC_shift, ZFUNC_mask);
278 break;
279 case GL_NOTEQUAL:
280 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NOTEQUAL,
281 ZFUNC_shift, ZFUNC_mask);
282 break;
283 case GL_GEQUAL:
284 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GEQUAL,
285 ZFUNC_shift, ZFUNC_mask);
286 break;
287 case GL_ALWAYS:
288 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
289 ZFUNC_shift, ZFUNC_mask);
290 break;
291 default:
292 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
293 ZFUNC_shift, ZFUNC_mask);
294 break;
295 }
296 }
297 else
298 {
299 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
300 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
301 }
302 }
303
304 static void r700AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref) //---------------
305 {
306 }
307
308
309 static void r700BlendColor(GLcontext * ctx, const GLfloat cf[4]) //----------------
310 {
311 }
312
313 static void r700BlendEquationSeparate(GLcontext * ctx,
314 GLenum modeRGB, GLenum modeA) //-----------------
315 {
316 }
317
318 static void r700BlendFuncSeparate(GLcontext * ctx,
319 GLenum sfactorRGB, GLenum dfactorRGB,
320 GLenum sfactorA, GLenum dfactorA) //------------------------
321 {
322 }
323
324 static void r700UpdateCulling(GLcontext * ctx)
325 {
326 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(R700_CONTEXT(ctx)->chipobj.pvChipObj);
327
328 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
329 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
330 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
331
332 if (ctx->Polygon.CullFlag)
333 {
334 switch (ctx->Polygon.CullFaceMode)
335 {
336 case GL_FRONT:
337 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
338 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
339 break;
340 case GL_BACK:
341 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
342 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
343 break;
344 case GL_FRONT_AND_BACK:
345 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
346 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
347 break;
348 default:
349 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
350 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
351 break;
352 }
353 }
354
355 switch (ctx->Polygon.FrontFace)
356 {
357 case GL_CW:
358 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
359 break;
360 case GL_CCW:
361 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
362 break;
363 default:
364 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); /* default: ccw */
365 break;
366 }
367 }
368
369 static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //------------------
370 {
371 switch (cap)
372 {
373 case GL_TEXTURE_1D:
374 case GL_TEXTURE_2D:
375 case GL_TEXTURE_3D:
376 break;
377 case GL_FOG:
378 break;
379 case GL_ALPHA_TEST:
380 break;
381 case GL_COLOR_LOGIC_OP:
382 case GL_BLEND:
383 break;
384 case GL_CLIP_PLANE0:
385 case GL_CLIP_PLANE1:
386 case GL_CLIP_PLANE2:
387 case GL_CLIP_PLANE3:
388 case GL_CLIP_PLANE4:
389 case GL_CLIP_PLANE5:
390 break;
391 case GL_DEPTH_TEST:
392 r700SetDepthState(ctx);
393 break;
394 case GL_STENCIL_TEST:
395 break;
396 case GL_CULL_FACE:
397 r700UpdateCulling(ctx);
398 break;
399 case GL_POLYGON_OFFSET_POINT:
400 case GL_POLYGON_OFFSET_LINE:
401 case GL_POLYGON_OFFSET_FILL:
402 break;
403 default:
404 break;
405 }
406 }
407
408 /**
409 * Handle glColorMask()
410 */
411 static void r700ColorMask(GLcontext * ctx,
412 GLboolean r, GLboolean g, GLboolean b, GLboolean a) //------------------
413 {
414 }
415
416 /**
417 * Change the depth testing function.
418 *
419 * \note Mesa already filters redundant calls to this function.
420 */
421 static void r700DepthFunc(GLcontext * ctx, GLenum func) //--------------------
422 {
423 r700SetDepthState(ctx);
424 }
425
426 /**
427 * Enable/Disable depth writing.
428 *
429 * \note Mesa already filters redundant calls to this function.
430 */
431 static void r700DepthMask(GLcontext * ctx, GLboolean mask) //------------------
432 {
433 r700SetDepthState(ctx);
434 }
435
436 /**
437 * Change the culling mode.
438 *
439 * \note Mesa already filters redundant calls to this function.
440 */
441 static void r700CullFace(GLcontext * ctx, GLenum mode) //-----------------
442 {
443 r700UpdateCulling(ctx);
444 }
445
446 /* =============================================================
447 * Fog
448 */
449 static void r700Fogfv(GLcontext * ctx, GLenum pname, const GLfloat * param) //--------------
450 {
451 }
452
453 /**
454 * Change the polygon orientation.
455 *
456 * \note Mesa already filters redundant calls to this function.
457 */
458 static void r700FrontFace(GLcontext * ctx, GLenum mode) //------------------
459 {
460 r700UpdateCulling(ctx);
461 }
462
463 static void r700ShadeModel(GLcontext * ctx, GLenum mode) //--------------------
464 {
465 }
466
467 static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * param) //---------------
468 {
469 }
470
471 static void r700StencilFuncSeparate(GLcontext * ctx, GLenum face,
472 GLenum func, GLint ref, GLuint mask) //---------------------
473 {
474 }
475
476
477 static void r700StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) //--------------
478 {
479 }
480
481 static void r700StencilOpSeparate(GLcontext * ctx, GLenum face,
482 GLenum fail, GLenum zfail, GLenum zpass) //--------------------
483 {
484 }
485
486 #define SUBPIXEL_X 0.125
487 #define SUBPIXEL_Y 0.125
488
489 static void r700Viewport(GLcontext * ctx,
490 GLint x,
491 GLint y,
492 GLsizei width,
493 GLsizei height) //--------------------
494 {
495 #if 0 /* to be enabled */
496 context_t *context = R700_CONTEXT(ctx);
497
498 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj);
499
500 context->vport_x = x;
501 context->vport_y = y;
502 context->vport_width = width;
503 context->vport_height= height;
504
505 __DRIdrawablePrivate *dPriv = context->currentDraw;
506
507 GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
508 GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
509
510 const GLfloat *v = ctx->Viewport._WindowMap.m;
511
512 GLfloat sx, tx, sy, ty, sz, tz;
513 GLfloat scale;
514
515 switch (ctx->Visual.depthBits)
516 {
517 case 16:
518 scale = 1.0 / (GLfloat) 0xffff;
519 break;
520 case 24:
521 scale = 1.0 / (GLfloat) 0xffffff;
522 break;
523 default:
524 fprintf(stderr, "Error: Unsupported depth %d... exiting\n",
525 ctx->Visual.depthBits);
526 _mesa_exit(-1);
527 }
528
529 sx = v[MAT_SX];
530 tx = v[MAT_TX] + xoffset + SUBPIXEL_X;
531 sy = -v[MAT_SY];
532 ty = (-v[MAT_TY]) + yoffset + SUBPIXEL_Y;
533 sz = v[MAT_SZ] * scale;
534 tz = v[MAT_TZ] * scale;
535
536 /* TODO : Need DMA flush as well. */
537
538 if(context->cmdbuf.count_used > 0)
539 {
540 (context->chipobj.FlushCmdBuffer)(context);
541 }
542
543 r700->PA_CL_VPORT_XSCALE.u32All = *((unsigned int*)(&sx));
544 r700->PA_CL_VPORT_XOFFSET.u32All = *((unsigned int*)(&tx));
545
546 r700->PA_CL_VPORT_YSCALE.u32All = *((unsigned int*)(&sy));
547 r700->PA_CL_VPORT_YOFFSET.u32All = *((unsigned int*)(&ty));
548
549 r700->PA_CL_VPORT_ZSCALE.u32All = *((unsigned int*)(&sz));
550 r700->PA_CL_VPORT_ZOFFSET.u32All = *((unsigned int*)(&tz));
551 #endif /* to be enabled */
552 }
553
554
555 static void r700DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) //-------------
556 {
557 }
558
559 static void r700PointSize(GLcontext * ctx, GLfloat size) //-------------------
560 {
561 }
562
563 static void r700LineWidth(GLcontext * ctx, GLfloat widthf) //---------------
564 {
565 }
566
567 static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) //--------------
568 {
569 }
570
571
572 static void r700PolygonMode(GLcontext * ctx, GLenum face, GLenum mode) //------------------
573 {
574 }
575
576 static void r700RenderMode(GLcontext * ctx, GLenum mode) //---------------------
577 {
578 }
579
580 static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq ) //-----------------
581 {
582 }
583
584 static void r700Scissor(GLcontext* ctx, GLint x, GLint y, GLsizei w, GLsizei h) //---------------
585 {
586 if (ctx->Scissor.Enabled)
587 {
588 /* We don't pipeline cliprect changes */
589 /* r700Flush(ctx); */
590
591 //__DRIdrawablePrivate *dPriv = radeon->dri.drawable;
592 //int x1 = dPriv->x + ctx->Scissor.X;
593 //int y1 = dPriv->y + dPriv->h - (ctx->Scissor.Y + ctx->Scissor.Height);
594
595 //radeon->state.scissor.rect.x1 = x1;
596 //radeon->state.scissor.rect.y1 = y1;
597 //radeon->state.scissor.rect.x2 = x1 + ctx->Scissor.Width;
598 //radeon->state.scissor.rect.y2 = y1 + ctx->Scissor.Height;
599 /* radeonRecalcScissorRects(radeon); */
600 }
601 }
602
603
604 /**
605 * Calculate initial hardware state and register state functions.
606 * Assumes that the command buffer and state atoms have been
607 * initialized already.
608 */
609 void r700InitState(GLcontext * ctx) //-------------------
610 {
611 #if 0 /* to be enabled */
612 context_t *context = R700_CONTEXT(ctx);
613
614 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj);
615
616 if(context->ctx->Visual.doubleBufferMode && context->sarea->pfCurrentPage == 0)
617 {
618 context->target.rt = context->screen->backBuffer;
619 }
620 else
621 {
622 context->target.rt = context->screen->frontBuffer;
623 }
624
625 SETfield(r700->CB_TARGET_MASK.u32All, 0xF, TARGET0_ENABLE_shift, TARGET0_ENABLE_mask);
626 SETfield(r700->CB_SHADER_MASK.u32All, 0xF, OUTPUT0_ENABLE_shift, OUTPUT0_ENABLE_mask);
627
628 /* screen */
629 r700->PA_SC_SCREEN_SCISSOR_TL.u32All = 0x0;
630 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, context->screen->width,
631 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask);
632 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, context->screen->height,
633 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask);
634
635 /* window */
636 SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
637 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, context->currentDraw->x,
638 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask);
639 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, context->currentDraw->y,
640 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask);
641
642 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, context->currentDraw->x + context->currentDraw->w,
643 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask);
644 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, context->currentDraw->y + context->currentDraw->h,
645 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask);
646
647 /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
648 r700->PA_SC_CLIPRECT_RULE.u32All = 0x0000FFFF;
649
650 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, context->currentDraw->x,
651 PA_SC_CLIPRECT_0_TL__TL_X_shift, PA_SC_CLIPRECT_0_TL__TL_X_mask);
652 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, context->currentDraw->y,
653 PA_SC_CLIPRECT_0_TL__TL_Y_shift, PA_SC_CLIPRECT_0_TL__TL_Y_mask);
654 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, context->currentDraw->x + context->currentDraw->w,
655 PA_SC_CLIPRECT_0_BR__BR_X_shift, PA_SC_CLIPRECT_0_BR__BR_X_mask);
656 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, context->currentDraw->y + context->currentDraw->h,
657 PA_SC_CLIPRECT_0_BR__BR_Y_shift, PA_SC_CLIPRECT_0_BR__BR_Y_mask);
658
659 r700->PA_SC_CLIPRECT_1_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
660 r700->PA_SC_CLIPRECT_1_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
661 r700->PA_SC_CLIPRECT_2_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
662 r700->PA_SC_CLIPRECT_2_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
663 r700->PA_SC_CLIPRECT_3_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
664 r700->PA_SC_CLIPRECT_3_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
665
666 /* more....2d clip */
667 SETbit(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
668 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, context->currentDraw->x,
669 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask);
670 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, context->currentDraw->y,
671 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask);
672 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, context->currentDraw->x + context->currentDraw->w,
673 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask);
674 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, context->currentDraw->y + context->currentDraw->h,
675 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask);
676
677 SETbit(r700->PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
678 SETfield(r700->PA_SC_VPORT_SCISSOR_0_TL.u32All, context->currentDraw->x,
679 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask);
680 SETfield(r700->PA_SC_VPORT_SCISSOR_0_TL.u32All, context->currentDraw->y,
681 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask);
682 SETfield(r700->PA_SC_VPORT_SCISSOR_0_BR.u32All, context->currentDraw->x + context->currentDraw->w,
683 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask);
684 SETfield(r700->PA_SC_VPORT_SCISSOR_0_BR.u32All, context->currentDraw->y + context->currentDraw->h,
685 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask);
686
687 SETbit(r700->PA_SC_VPORT_SCISSOR_1_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
688 SETfield(r700->PA_SC_VPORT_SCISSOR_1_TL.u32All, context->currentDraw->x,
689 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask);
690 SETfield(r700->PA_SC_VPORT_SCISSOR_1_TL.u32All, context->currentDraw->y,
691 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask);
692 SETfield(r700->PA_SC_VPORT_SCISSOR_1_BR.u32All, context->currentDraw->x + context->currentDraw->w,
693 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask);
694 SETfield(r700->PA_SC_VPORT_SCISSOR_1_BR.u32All, context->currentDraw->y + context->currentDraw->h,
695 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask);
696
697 /* setup viewport */
698 r700Viewport(ctx,
699 0,
700 0,
701 context->currentDraw->w,
702 context->currentDraw->h);
703
704 /* Turn off vgt reuse */
705 r700->VGT_REUSE_OFF.u32All = 0;
706 SETbit(r700->VGT_REUSE_OFF.u32All, REUSE_OFF_bit);
707
708 /* Specify offsetting and clamp values for vertices */
709 r700->VGT_MAX_VTX_INDX.u32All = 0xFFFFFF;
710 r700->VGT_MIN_VTX_INDX.u32All = 0;
711 r700->VGT_INDX_OFFSET.u32All = 0;
712
713 /* Specify the number of instances */
714 r700->VGT_DMA_NUM_INSTANCES.u32All = 1;
715
716 /* not alpha blend */
717 CLEARfield(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_FUNC_mask);
718 CLEARbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
719
720 /* defualt shader connections. */
721 r700->SPI_VS_OUT_ID_0.u32All = 0x03020100;
722 r700->SPI_VS_OUT_ID_1.u32All = 0x07060504;
723
724 r700->SPI_PS_INPUT_CNTL_0.u32All = 0x00000800;
725 r700->SPI_PS_INPUT_CNTL_1.u32All = 0x00000801;
726 r700->SPI_PS_INPUT_CNTL_2.u32All = 0x00000802;
727
728 SETfield(r700->CB_COLOR_CONTROL.u32All, 0xCC, ROP3_shift, ROP3_mask);
729 CLEARbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit);
730 CLEARfield(r700->CB_BLEND0_CONTROL.u32All, COLOR_SRCBLEND_mask); /* no dst blend */
731 CLEARfield(r700->CB_BLEND0_CONTROL.u32All, ALPHA_SRCBLEND_mask); /* no dst blend */
732
733 r700->DB_SHADER_CONTROL.u32All = 0;
734 SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
735
736 /* Set up the culling control register */
737 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
738 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
739 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
740 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
741
742 /* Do scale XY and Z by 1/W0. */
743 context->bEnablePerspective = GL_TRUE;
744 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
745 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
746 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
747
748 /* Enable viewport scaling for all three axis */
749 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_SCALE_ENA_bit);
750 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_OFFSET_ENA_bit);
751 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_SCALE_ENA_bit);
752 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_OFFSET_ENA_bit);
753 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_SCALE_ENA_bit);
754 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_OFFSET_ENA_bit);
755
756 /* Set up point sizes and min/max values */
757 SETfield(r700->PA_SU_POINT_SIZE.u32All, 0x8,
758 PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask);
759 SETfield(r700->PA_SU_POINT_SIZE.u32All, 0x8,
760 PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask);
761 CLEARfield(r700->PA_SU_POINT_MINMAX.u32All, MIN_SIZE_mask);
762 SETfield(r700->PA_SU_POINT_MINMAX.u32All, 0x8000, MAX_SIZE_shift, MAX_SIZE_mask);
763
764 /* Set up line control */
765 SETfield(r700->PA_SU_LINE_CNTL.u32All, 0x8,
766 PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
767
768 r700->PA_SC_LINE_CNTL.u32All = 0;
769 CLEARbit(r700->PA_SC_LINE_CNTL.u32All, EXPAND_LINE_WIDTH_bit);
770 SETbit(r700->PA_SC_LINE_CNTL.u32All, LAST_PIXEL_bit);
771
772 /* Set up vertex control */
773 r700->PA_SU_VTX_CNTL.u32All = 0;
774 CLEARfield(r700->PA_SU_VTX_CNTL.u32All, QUANT_MODE_mask);
775 SETbit(r700->PA_SU_VTX_CNTL.u32All, PIX_CENTER_bit);
776 SETfield(r700->PA_SU_VTX_CNTL.u32All, X_ROUND_TO_EVEN,
777 PA_SU_VTX_CNTL__ROUND_MODE_shift, PA_SU_VTX_CNTL__ROUND_MODE_mask);
778
779 /* to 1.0 = no guard band */
780 r700->PA_CL_GB_VERT_CLIP_ADJ.u32All = 0x3F800000; /* 1.0 */
781 r700->PA_CL_GB_VERT_DISC_ADJ.u32All = 0x3F800000;
782 r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All = 0x3F800000;
783 r700->PA_CL_GB_HORZ_DISC_ADJ.u32All = 0x3F800000;
784
785 /* Disble color compares */
786 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
787 CLRCMP_FCN_SRC_shift, CLRCMP_FCN_SRC_mask);
788 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
789 CLRCMP_FCN_DST_shift, CLRCMP_FCN_DST_mask);
790 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_SEL_SRC,
791 CLRCMP_FCN_SEL_shift, CLRCMP_FCN_SEL_mask);
792
793 /* Zero out source */
794 r700->CB_CLRCMP_SRC.u32All = 0x00000000;
795
796 /* Put a compare color in for error checking */
797 r700->CB_CLRCMP_DST.u32All = 0x000000FF;
798
799 /* Set up color compare mask */
800 r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF;
801
802 /* Enable all samples for multi-sample anti-aliasing */
803 r700->PA_SC_AA_MASK.u32All = 0xFFFFFFFF;
804 /* Turn off AA */
805 r700->PA_SC_AA_CONFIG.u32All = 0;
806
807 SETfield(r700->VGT_OUT_DEALLOC_CNTL.u32All, 16, DEALLOC_DIST_shift, DEALLOC_DIST_mask);
808 SETfield(r700->VGT_VERTEX_REUSE_BLOCK_CNTL.u32All, 14, VTX_REUSE_DEPTH_shift, VTX_REUSE_DEPTH_mask);
809
810 r700->SX_MISC.u32All = 0;
811
812 /* depth buf */
813 r700->DB_DEPTH_SIZE.u32All = 0;
814 SETfield(r700->DB_DEPTH_SIZE.u32All, (context->screen->depthBuffer.pitch/8)-1,
815 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
816 SETfield(r700->DB_DEPTH_SIZE.u32All, ( (context->screen->depthBuffer.size / context->screen->cpp)/64 )-1,
817 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */
818 r700->DB_DEPTH_BASE.u32All = context->screen->depthBuffer.gpu >> 8;
819 r700->DB_DEPTH_INFO.u32All = 0;
820 if(4 == context->screen->cpp) /* TODO : in scrren create, gives z its own format alloc. */
821 {
822 switch (ctx->Visual.depthBits)
823 {
824 case 16:
825 case 24:
826 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_8_24,
827 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
828 break;
829 default:
830 fprintf(stderr, "Error: Unsupported depth %d... exiting\n",
831 ctx->Visual.depthBits);
832 _mesa_exit(-1);
833 }
834 }
835 else
836 {
837 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16,
838 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
839 }
840 SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_2D_TILED_THIN1,
841 DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask);
842 /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */
843 r700->DB_DEPTH_CONTROL.u32All = 0;
844 r700->DB_DEPTH_CLEAR.u32All = 0x3F800000;
845 r700->DB_DEPTH_VIEW.u32All = 0;
846 r700->DB_RENDER_CONTROL.u32All = 0;
847 r700->DB_RENDER_OVERRIDE.u32All = 0;
848 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
849 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
850 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
851
852 /* color buffer */
853 SETfield(r700->CB_COLOR0_SIZE.u32All, (context->screen->frontBuffer.pitch/8)-1,
854 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
855 SETfield(r700->CB_COLOR0_SIZE.u32All, ( (context->screen->frontBuffer.size / context->screen->cpp)/64 )-1,
856 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
857 r700->CB_COLOR0_BASE.u32All = context->screen->frontBuffer.gpu >> 8;
858 SETfield(r700->CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
859 SETfield(r700->CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL,
860 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
861 if(4 == context->screen->cpp)
862 {
863 SETfield(r700->CB_COLOR0_INFO.u32All, COLOR_8_8_8_8,
864 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
865 SETfield(r700->CB_COLOR0_INFO.u32All, SWAP_ALT, COMP_SWAP_shift, COMP_SWAP_mask);
866 }
867 else
868 {
869 SETfield(r700->CB_COLOR0_INFO.u32All, COLOR_5_6_5,
870 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
871 SETfield(r700->CB_COLOR0_INFO.u32All, SWAP_ALT_REV,
872 COMP_SWAP_shift, COMP_SWAP_mask);
873 }
874 SETbit(r700->CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
875 SETbit(r700->CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit);
876 SETfield(r700->CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
877 r700->CB_COLOR0_VIEW.u32All = 0;
878 r700->CB_COLOR0_TILE.u32All = 0;
879 r700->CB_COLOR0_FRAG.u32All = 0;
880 r700->CB_COLOR0_MASK.u32All = 0;
881
882 r700->PA_SC_VPORT_ZMAX_0.u32All = 0x3F800000;
883 #endif /* to be enabled */
884 }
885
886 void r700InitStateFuncs(struct dd_function_table *functions) //-----------------
887 {
888 functions->UpdateState = r700InvalidateState;
889 functions->AlphaFunc = r700AlphaFunc;
890 functions->BlendColor = r700BlendColor;
891 functions->BlendEquationSeparate = r700BlendEquationSeparate;
892 functions->BlendFuncSeparate = r700BlendFuncSeparate;
893 functions->Enable = r700Enable;
894 functions->ColorMask = r700ColorMask;
895 functions->DepthFunc = r700DepthFunc;
896 functions->DepthMask = r700DepthMask;
897 functions->CullFace = r700CullFace;
898 functions->Fogfv = r700Fogfv;
899 functions->FrontFace = r700FrontFace;
900 functions->ShadeModel = r700ShadeModel;
901
902 /* ARB_point_parameters */
903 functions->PointParameterfv = r700PointParameter;
904
905 /* Stencil related */
906 functions->StencilFuncSeparate = r700StencilFuncSeparate;
907 functions->StencilMaskSeparate = r700StencilMaskSeparate;
908 functions->StencilOpSeparate = r700StencilOpSeparate;
909
910 /* Viewport related */
911 functions->Viewport = r700Viewport;
912 functions->DepthRange = r700DepthRange;
913 functions->PointSize = r700PointSize;
914 functions->LineWidth = r700LineWidth;
915
916 functions->PolygonOffset = r700PolygonOffset;
917 functions->PolygonMode = r700PolygonMode;
918
919 functions->RenderMode = r700RenderMode;
920
921 functions->ClipPlane = r700ClipPlane;
922
923 functions->Scissor = r700Scissor;
924 }
925