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r600: disable flat shade fix in 506bacb8e40b0a170a4b620113506925d2333735
[mesa.git] / src / mesa / drivers / dri / r600 / r700_state.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/context.h"
34 #include "main/dd.h"
35 #include "main/simple_list.h"
36
37 #include "tnl/tnl.h"
38 #include "tnl/t_pipeline.h"
39 #include "tnl/t_vp_build.h"
40 #include "swrast/swrast.h"
41 #include "swrast_setup/swrast_setup.h"
42 #include "main/api_arrayelt.h"
43 #include "main/state.h"
44 #include "main/framebuffer.h"
45
46 #include "shader/prog_parameter.h"
47 #include "shader/prog_statevars.h"
48 #include "vbo/vbo.h"
49 #include "main/texformat.h"
50
51 #include "r600_context.h"
52
53 #include "r700_state.h"
54
55 #include "r700_fragprog.h"
56 #include "r700_vertprog.h"
57
58
59 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state);
60 static void r700UpdatePolygonMode(GLcontext * ctx);
61 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state);
62 static void r700SetStencilState(GLcontext * ctx, GLboolean state);
63
64 void r700SetDefaultStates(context_t *context) //--------------------
65 {
66
67 }
68
69 void r700UpdateShaders (GLcontext * ctx) //----------------------------------
70 {
71 context_t *context = R700_CONTEXT(ctx);
72
73 GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
74 GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
75
76 struct r700_vertex_program *vp;
77 int i;
78
79 if (context->radeon.NewGLState)
80 {
81 context->radeon.NewGLState = 0;
82
83 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++)
84 {
85 /* mat states from state var not array for sw */
86 dummy_attrib[i].stride = 0;
87
88 temp_attrib[i] = TNL_CONTEXT(ctx)->vb.AttribPtr[i];
89 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = &(dummy_attrib[i]);
90 }
91
92 _tnl_UpdateFixedFunctionProgram(ctx);
93
94 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++)
95 {
96 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = temp_attrib[i];
97 }
98
99 r700SelectVertexShader(ctx);
100 vp = (struct r700_vertex_program *)ctx->VertexProgram._Current;
101
102 if (vp->translated == GL_FALSE)
103 {
104 // TODO
105 //fprintf(stderr, "Failing back to sw-tcl\n");
106 //hw_tcl_on = future_hw_tcl_on = 0;
107 //r300ResetHwState(rmesa);
108 //
109 r700UpdateStateParameters(ctx, _NEW_PROGRAM);
110 return;
111 }
112 }
113
114 r700UpdateStateParameters(ctx, _NEW_PROGRAM);
115 }
116
117 /*
118 * To correctly position primitives:
119 */
120 void r700UpdateViewportOffset(GLcontext * ctx) //------------------
121 {
122 context_t *context = R700_CONTEXT(ctx);
123 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
124 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
125 GLfloat xoffset = (GLfloat) dPriv->x;
126 GLfloat yoffset = (GLfloat) dPriv->y + dPriv->h;
127 const GLfloat *v = ctx->Viewport._WindowMap.m;
128 int id = 0;
129
130 GLfloat tx = v[MAT_TX] + xoffset;
131 GLfloat ty = (-v[MAT_TY]) + yoffset;
132
133 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
134 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
135
136 radeonUpdateScissor(ctx);
137 }
138
139 /**
140 * Tell the card where to render (offset, pitch).
141 * Effected by glDrawBuffer, etc
142 */
143 void r700UpdateDrawBuffer(GLcontext * ctx) /* TODO */ //---------------------
144 {
145 #if 0 /* to be enabled */
146 context_t *context = R700_CONTEXT(ctx);
147
148 switch (ctx->DrawBuffer->_ColorDrawBufferIndexes[0])
149 {
150 case BUFFER_FRONT_LEFT:
151 context->target.rt = context->screen->frontBuffer;
152 break;
153 case BUFFER_BACK_LEFT:
154 context->target.rt = context->screen->backBuffer;
155 break;
156 default:
157 memset (&context->target.rt, sizeof(context->target.rt), 0);
158 }
159 #endif /* to be enabled */
160 }
161
162 static void r700FetchStateParameter(GLcontext * ctx,
163 const gl_state_index state[STATE_LENGTH],
164 GLfloat * value)
165 {
166 context_t *context = R700_CONTEXT(ctx);
167
168 /* TODO */
169 }
170
171 void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state) //--------------------
172 {
173 struct r700_fragment_program *fp;
174 struct gl_program_parameter_list *paramList;
175 GLuint i;
176
177 if (!(new_state & (_NEW_BUFFERS | _NEW_PROGRAM)))
178 return;
179
180 fp = (struct r700_fragment_program *)ctx->FragmentProgram._Current;
181 if (!fp)
182 {
183 return;
184 }
185
186 paramList = fp->mesa_program.Base.Parameters;
187
188 if (!paramList)
189 {
190 return;
191 }
192
193 for (i = 0; i < paramList->NumParameters; i++)
194 {
195 if (paramList->Parameters[i].Type == PROGRAM_STATE_VAR)
196 {
197 r700FetchStateParameter(ctx,
198 paramList->Parameters[i].
199 StateIndexes,
200 paramList->ParameterValues[i]);
201 }
202 }
203 }
204
205 /**
206 * Called by Mesa after an internal state update.
207 */
208 static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //-------------------
209 {
210 context_t *context = R700_CONTEXT(ctx);
211
212 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
213
214 _swrast_InvalidateState(ctx, new_state);
215 _swsetup_InvalidateState(ctx, new_state);
216 _vbo_InvalidateState(ctx, new_state);
217 _tnl_InvalidateState(ctx, new_state);
218 _ae_invalidate_state(ctx, new_state);
219
220 if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL))
221 {
222 _mesa_update_framebuffer(ctx);
223 /* this updates the DrawBuffer's Width/Height if it's a FBO */
224 _mesa_update_draw_buffer_bounds(ctx);
225
226 r700UpdateDrawBuffer(ctx);
227 }
228
229 r700UpdateStateParameters(ctx, new_state);
230
231 if(GL_TRUE == r700->bEnablePerspective)
232 {
233 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
234 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
235 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
236
237 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
238
239 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
240 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
241 }
242 else
243 {
244 /* For orthogonal case. */
245 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
246 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
247
248 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
249
250 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
251 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
252 }
253
254 context->radeon.NewGLState |= new_state;
255 }
256
257 static void r700SetDepthState(GLcontext * ctx)
258 {
259 context_t *context = R700_CONTEXT(ctx);
260
261 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
262
263 if (ctx->Depth.Test)
264 {
265 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
266 if (ctx->Depth.Mask)
267 {
268 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
269 }
270 else
271 {
272 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
273 }
274
275 switch (ctx->Depth.Func)
276 {
277 case GL_NEVER:
278 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NEVER,
279 ZFUNC_shift, ZFUNC_mask);
280 break;
281 case GL_LESS:
282 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LESS,
283 ZFUNC_shift, ZFUNC_mask);
284 break;
285 case GL_EQUAL:
286 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_EQUAL,
287 ZFUNC_shift, ZFUNC_mask);
288 break;
289 case GL_LEQUAL:
290 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LEQUAL,
291 ZFUNC_shift, ZFUNC_mask);
292 break;
293 case GL_GREATER:
294 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GREATER,
295 ZFUNC_shift, ZFUNC_mask);
296 break;
297 case GL_NOTEQUAL:
298 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NOTEQUAL,
299 ZFUNC_shift, ZFUNC_mask);
300 break;
301 case GL_GEQUAL:
302 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GEQUAL,
303 ZFUNC_shift, ZFUNC_mask);
304 break;
305 case GL_ALWAYS:
306 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
307 ZFUNC_shift, ZFUNC_mask);
308 break;
309 default:
310 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
311 ZFUNC_shift, ZFUNC_mask);
312 break;
313 }
314 }
315 else
316 {
317 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
318 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
319 }
320 }
321
322 static void r700SetAlphaState(GLcontext * ctx)
323 {
324 context_t *context = R700_CONTEXT(ctx);
325 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
326 uint32_t alpha_func = REF_ALWAYS;
327 GLboolean really_enabled = ctx->Color.AlphaEnabled;
328
329 switch (ctx->Color.AlphaFunc) {
330 case GL_NEVER:
331 alpha_func = REF_NEVER;
332 break;
333 case GL_LESS:
334 alpha_func = REF_LESS;
335 break;
336 case GL_EQUAL:
337 alpha_func = REF_EQUAL;
338 break;
339 case GL_LEQUAL:
340 alpha_func = REF_LEQUAL;
341 break;
342 case GL_GREATER:
343 alpha_func = REF_GREATER;
344 break;
345 case GL_NOTEQUAL:
346 alpha_func = REF_NOTEQUAL;
347 break;
348 case GL_GEQUAL:
349 alpha_func = REF_GEQUAL;
350 break;
351 case GL_ALWAYS:
352 /*alpha_func = REF_ALWAYS; */
353 really_enabled = GL_FALSE;
354 break;
355 }
356
357 if (really_enabled) {
358 SETfield(r700->SX_ALPHA_TEST_CONTROL.u32All, alpha_func,
359 ALPHA_FUNC_shift, ALPHA_FUNC_mask);
360 SETbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
361 r700->SX_ALPHA_REF.f32All = ctx->Color.AlphaRef;
362 } else {
363 CLEARbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
364 }
365
366 }
367
368 static void r700AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref) //---------------
369 {
370 (void)func;
371 (void)ref;
372 r700SetAlphaState(ctx);
373 }
374
375
376 static void r700BlendColor(GLcontext * ctx, const GLfloat cf[4]) //----------------
377 {
378 context_t *context = R700_CONTEXT(ctx);
379 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
380
381 r700->CB_BLEND_RED.f32All = cf[0];
382 r700->CB_BLEND_GREEN.f32All = cf[1];
383 r700->CB_BLEND_BLUE.f32All = cf[2];
384 r700->CB_BLEND_ALPHA.f32All = cf[3];
385 }
386
387 static int blend_factor(GLenum factor, GLboolean is_src)
388 {
389 switch (factor) {
390 case GL_ZERO:
391 return BLEND_ZERO;
392 break;
393 case GL_ONE:
394 return BLEND_ONE;
395 break;
396 case GL_DST_COLOR:
397 return BLEND_DST_COLOR;
398 break;
399 case GL_ONE_MINUS_DST_COLOR:
400 return BLEND_ONE_MINUS_DST_COLOR;
401 break;
402 case GL_SRC_COLOR:
403 return BLEND_SRC_COLOR;
404 break;
405 case GL_ONE_MINUS_SRC_COLOR:
406 return BLEND_ONE_MINUS_SRC_COLOR;
407 break;
408 case GL_SRC_ALPHA:
409 return BLEND_SRC_ALPHA;
410 break;
411 case GL_ONE_MINUS_SRC_ALPHA:
412 return BLEND_ONE_MINUS_SRC_ALPHA;
413 break;
414 case GL_DST_ALPHA:
415 return BLEND_DST_ALPHA;
416 break;
417 case GL_ONE_MINUS_DST_ALPHA:
418 return BLEND_ONE_MINUS_DST_ALPHA;
419 break;
420 case GL_SRC_ALPHA_SATURATE:
421 return (is_src) ? BLEND_SRC_ALPHA_SATURATE : BLEND_ZERO;
422 break;
423 case GL_CONSTANT_COLOR:
424 return BLEND_CONSTANT_COLOR;
425 break;
426 case GL_ONE_MINUS_CONSTANT_COLOR:
427 return BLEND_ONE_MINUS_CONSTANT_COLOR;
428 break;
429 case GL_CONSTANT_ALPHA:
430 return BLEND_CONSTANT_ALPHA;
431 break;
432 case GL_ONE_MINUS_CONSTANT_ALPHA:
433 return BLEND_ONE_MINUS_CONSTANT_ALPHA;
434 break;
435 default:
436 fprintf(stderr, "unknown blend factor %x\n", factor);
437 return (is_src) ? BLEND_ONE : BLEND_ZERO;
438 break;
439 }
440 }
441
442 static void r700SetBlendState(GLcontext * ctx)
443 {
444 context_t *context = R700_CONTEXT(ctx);
445 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
446 int id = 0;
447 uint32_t blend_reg = 0, eqn, eqnA;
448
449 if (RGBA_LOGICOP_ENABLED(ctx) || !ctx->Color.BlendEnabled) {
450 SETfield(blend_reg,
451 BLEND_ONE, COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
452 SETfield(blend_reg,
453 BLEND_ZERO, COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
454 SETfield(blend_reg,
455 COMB_DST_PLUS_SRC, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
456 SETfield(blend_reg,
457 BLEND_ONE, ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
458 SETfield(blend_reg,
459 BLEND_ZERO, ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
460 SETfield(blend_reg,
461 COMB_DST_PLUS_SRC, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
462 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
463 r700->CB_BLEND_CONTROL.u32All = blend_reg;
464 else
465 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
466 return;
467 }
468
469 SETfield(blend_reg,
470 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
471 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
472 SETfield(blend_reg,
473 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
474 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
475
476 switch (ctx->Color.BlendEquationRGB) {
477 case GL_FUNC_ADD:
478 eqn = COMB_DST_PLUS_SRC;
479 break;
480 case GL_FUNC_SUBTRACT:
481 eqn = COMB_SRC_MINUS_DST;
482 break;
483 case GL_FUNC_REVERSE_SUBTRACT:
484 eqn = COMB_DST_MINUS_SRC;
485 break;
486 case GL_MIN:
487 eqn = COMB_MIN_DST_SRC;
488 SETfield(blend_reg,
489 BLEND_ONE,
490 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
491 SETfield(blend_reg,
492 BLEND_ONE,
493 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
494 break;
495 case GL_MAX:
496 eqn = COMB_MAX_DST_SRC;
497 SETfield(blend_reg,
498 BLEND_ONE,
499 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
500 SETfield(blend_reg,
501 BLEND_ONE,
502 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
503 break;
504
505 default:
506 fprintf(stderr,
507 "[%s:%u] Invalid RGB blend equation (0x%04x).\n",
508 __FUNCTION__, __LINE__, ctx->Color.BlendEquationRGB);
509 return;
510 }
511 SETfield(blend_reg,
512 eqn, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
513
514 SETfield(blend_reg,
515 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
516 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
517 SETfield(blend_reg,
518 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
519 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
520
521 switch (ctx->Color.BlendEquationA) {
522 case GL_FUNC_ADD:
523 eqnA = COMB_DST_PLUS_SRC;
524 break;
525 case GL_FUNC_SUBTRACT:
526 eqnA = COMB_SRC_MINUS_DST;
527 break;
528 case GL_FUNC_REVERSE_SUBTRACT:
529 eqnA = COMB_DST_MINUS_SRC;
530 break;
531 case GL_MIN:
532 eqnA = COMB_MIN_DST_SRC;
533 SETfield(blend_reg,
534 BLEND_ONE,
535 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
536 SETfield(blend_reg,
537 BLEND_ONE,
538 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
539 break;
540 case GL_MAX:
541 eqnA = COMB_MAX_DST_SRC;
542 SETfield(blend_reg,
543 BLEND_ONE,
544 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
545 SETfield(blend_reg,
546 BLEND_ONE,
547 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
548 break;
549 default:
550 fprintf(stderr,
551 "[%s:%u] Invalid A blend equation (0x%04x).\n",
552 __FUNCTION__, __LINE__, ctx->Color.BlendEquationA);
553 return;
554 }
555
556 SETfield(blend_reg,
557 eqnA, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
558
559 SETbit(blend_reg, SEPARATE_ALPHA_BLEND_bit);
560
561 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
562 r700->CB_BLEND_CONTROL.u32All = blend_reg;
563 else {
564 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
565 SETbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit);
566 }
567 SETfield(r700->CB_COLOR_CONTROL.u32All, (1 << id),
568 TARGET_BLEND_ENABLE_shift, TARGET_BLEND_ENABLE_mask);
569
570 }
571
572 static void r700BlendEquationSeparate(GLcontext * ctx,
573 GLenum modeRGB, GLenum modeA) //-----------------
574 {
575 r700SetBlendState(ctx);
576 }
577
578 static void r700BlendFuncSeparate(GLcontext * ctx,
579 GLenum sfactorRGB, GLenum dfactorRGB,
580 GLenum sfactorA, GLenum dfactorA) //------------------------
581 {
582 r700SetBlendState(ctx);
583 }
584
585 /**
586 * Translate LogicOp enums into hardware representation.
587 * Both use a very logical bit-wise layout, but unfortunately the order
588 * of bits is reversed.
589 */
590 static GLuint translate_logicop(GLenum logicop)
591 {
592 GLuint bits = logicop - GL_CLEAR;
593 bits = ((bits & 1) << 3) | ((bits & 2) << 1) | ((bits & 4) >> 1) | ((bits & 8) >> 3);
594 return bits;
595 }
596
597 /**
598 * Used internally to update the r300->hw hardware state to match the
599 * current OpenGL state.
600 */
601 static void r700SetLogicOpState(GLcontext *ctx)
602 {
603 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
604
605 if (RGBA_LOGICOP_ENABLED(ctx))
606 SETfield(r700->CB_COLOR_CONTROL.u32All,
607 translate_logicop(ctx->Color.LogicOp), ROP3_shift, ROP3_mask);
608 else
609 SETfield(r700->CB_COLOR_CONTROL.u32All, 0xCC, ROP3_shift, ROP3_mask);
610 }
611
612 /**
613 * Called by Mesa when an application program changes the LogicOp state
614 * via glLogicOp.
615 */
616 static void r700LogicOpcode(GLcontext *ctx, GLenum logicop)
617 {
618 if (RGBA_LOGICOP_ENABLED(ctx))
619 r700SetLogicOpState(ctx);
620 }
621
622 static void r700UpdateCulling(GLcontext * ctx)
623 {
624 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
625
626 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
627 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
628 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
629
630 if (ctx->Polygon.CullFlag)
631 {
632 switch (ctx->Polygon.CullFaceMode)
633 {
634 case GL_FRONT:
635 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
636 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
637 break;
638 case GL_BACK:
639 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
640 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
641 break;
642 case GL_FRONT_AND_BACK:
643 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
644 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
645 break;
646 default:
647 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
648 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
649 break;
650 }
651 }
652
653 switch (ctx->Polygon.FrontFace)
654 {
655 case GL_CW:
656 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
657 break;
658 case GL_CCW:
659 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
660 break;
661 default:
662 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); /* default: ccw */
663 break;
664 }
665 }
666
667 static void r700UpdateLineStipple(GLcontext * ctx)
668 {
669 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
670 if (ctx->Line.StippleFlag)
671 {
672 SETbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
673 }
674 else
675 {
676 CLEARbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
677 }
678 }
679
680 static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //------------------
681 {
682 context_t *context = R700_CONTEXT(ctx);
683
684 switch (cap) {
685 case GL_TEXTURE_1D:
686 case GL_TEXTURE_2D:
687 case GL_TEXTURE_3D:
688 /* empty */
689 break;
690 case GL_FOG:
691 /* empty */
692 break;
693 case GL_ALPHA_TEST:
694 r700SetAlphaState(ctx);
695 break;
696 case GL_COLOR_LOGIC_OP:
697 r700SetLogicOpState(ctx);
698 /* fall-through, because logic op overrides blending */
699 case GL_BLEND:
700 r700SetBlendState(ctx);
701 break;
702 case GL_CLIP_PLANE0:
703 case GL_CLIP_PLANE1:
704 case GL_CLIP_PLANE2:
705 case GL_CLIP_PLANE3:
706 case GL_CLIP_PLANE4:
707 case GL_CLIP_PLANE5:
708 r700SetClipPlaneState(ctx, cap, state);
709 break;
710 case GL_DEPTH_TEST:
711 r700SetDepthState(ctx);
712 break;
713 case GL_STENCIL_TEST:
714 r700SetStencilState(ctx, state);
715 break;
716 case GL_CULL_FACE:
717 r700UpdateCulling(ctx);
718 break;
719 case GL_POLYGON_OFFSET_POINT:
720 case GL_POLYGON_OFFSET_LINE:
721 case GL_POLYGON_OFFSET_FILL:
722 r700SetPolygonOffsetState(ctx, state);
723 break;
724 case GL_SCISSOR_TEST:
725 radeon_firevertices(&context->radeon);
726 context->radeon.state.scissor.enabled = state;
727 radeonUpdateScissor(ctx);
728 break;
729 case GL_LINE_STIPPLE:
730 r700UpdateLineStipple(ctx);
731 break;
732 default:
733 break;
734 }
735
736 }
737
738 /**
739 * Handle glColorMask()
740 */
741 static void r700ColorMask(GLcontext * ctx,
742 GLboolean r, GLboolean g, GLboolean b, GLboolean a) //------------------
743 {
744 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
745 unsigned int mask = ((r ? 1 : 0) |
746 (g ? 2 : 0) |
747 (b ? 4 : 0) |
748 (a ? 8 : 0));
749
750 if (mask != r700->CB_SHADER_MASK.u32All)
751 SETfield(r700->CB_SHADER_MASK.u32All, mask, OUTPUT0_ENABLE_shift, OUTPUT0_ENABLE_mask);
752 }
753
754 /**
755 * Change the depth testing function.
756 *
757 * \note Mesa already filters redundant calls to this function.
758 */
759 static void r700DepthFunc(GLcontext * ctx, GLenum func) //--------------------
760 {
761 r700SetDepthState(ctx);
762 }
763
764 /**
765 * Enable/Disable depth writing.
766 *
767 * \note Mesa already filters redundant calls to this function.
768 */
769 static void r700DepthMask(GLcontext * ctx, GLboolean mask) //------------------
770 {
771 r700SetDepthState(ctx);
772 }
773
774 /**
775 * Change the culling mode.
776 *
777 * \note Mesa already filters redundant calls to this function.
778 */
779 static void r700CullFace(GLcontext * ctx, GLenum mode) //-----------------
780 {
781 r700UpdateCulling(ctx);
782 }
783
784 /* =============================================================
785 * Fog
786 */
787 static void r700Fogfv(GLcontext * ctx, GLenum pname, const GLfloat * param) //--------------
788 {
789 }
790
791 /**
792 * Change the polygon orientation.
793 *
794 * \note Mesa already filters redundant calls to this function.
795 */
796 static void r700FrontFace(GLcontext * ctx, GLenum mode) //------------------
797 {
798 r700UpdateCulling(ctx);
799 r700UpdatePolygonMode(ctx);
800 }
801
802 static void r700ShadeModel(GLcontext * ctx, GLenum mode) //--------------------
803 {
804 context_t *context = R700_CONTEXT(ctx);
805 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
806
807 /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */
808 switch (mode) {
809 case GL_FLAT:
810 SETbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
811 //SETbit(r700->SPI_PS_INPUT_CNTL_0.u32All, FLAT_SHADE_bit);
812 break;
813 case GL_SMOOTH:
814 CLEARbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
815 //CLEARbit(r700->SPI_PS_INPUT_CNTL_0.u32All, FLAT_SHADE_bit);
816 break;
817 default:
818 return;
819 }
820 }
821
822 /* =============================================================
823 * Point state
824 */
825 static void r700PointSize(GLcontext * ctx, GLfloat size)
826 {
827 context_t *context = R700_CONTEXT(ctx);
828 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
829
830 /* We need to clamp to user defined range here, because
831 * the HW clamping happens only for per vertex point size. */
832 size = CLAMP(size, ctx->Point.MinSize, ctx->Point.MaxSize);
833
834 /* same size limits for AA, non-AA points */
835 size = CLAMP(size, ctx->Const.MinPointSize, ctx->Const.MaxPointSize);
836
837 /* format is 12.4 fixed point */
838 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 16),
839 PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask);
840 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 16),
841 PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask);
842
843 }
844
845 static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * param) //---------------
846 {
847 context_t *context = R700_CONTEXT(ctx);
848 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
849
850 /* format is 12.4 fixed point */
851 switch (pname) {
852 case GL_POINT_SIZE_MIN:
853 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MinSize * 16.0),
854 MIN_SIZE_shift, MIN_SIZE_mask);
855 break;
856 case GL_POINT_SIZE_MAX:
857 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MaxSize * 16.0),
858 MAX_SIZE_shift, MAX_SIZE_mask);
859 break;
860 case GL_POINT_DISTANCE_ATTENUATION:
861 break;
862 case GL_POINT_FADE_THRESHOLD_SIZE:
863 break;
864 default:
865 break;
866 }
867 }
868
869 static int translate_stencil_func(int func)
870 {
871 switch (func) {
872 case GL_NEVER:
873 return REF_NEVER;
874 case GL_LESS:
875 return REF_LESS;
876 case GL_EQUAL:
877 return REF_EQUAL;
878 case GL_LEQUAL:
879 return REF_LEQUAL;
880 case GL_GREATER:
881 return REF_GREATER;
882 case GL_NOTEQUAL:
883 return REF_NOTEQUAL;
884 case GL_GEQUAL:
885 return REF_GEQUAL;
886 case GL_ALWAYS:
887 return REF_ALWAYS;
888 }
889 return 0;
890 }
891
892 static int translate_stencil_op(int op)
893 {
894 switch (op) {
895 case GL_KEEP:
896 return STENCIL_KEEP;
897 case GL_ZERO:
898 return STENCIL_ZERO;
899 case GL_REPLACE:
900 return STENCIL_REPLACE;
901 case GL_INCR:
902 return STENCIL_INCR_CLAMP;
903 case GL_DECR:
904 return STENCIL_DECR_CLAMP;
905 case GL_INCR_WRAP_EXT:
906 return STENCIL_INCR_WRAP;
907 case GL_DECR_WRAP_EXT:
908 return STENCIL_DECR_WRAP;
909 case GL_INVERT:
910 return STENCIL_INVERT;
911 default:
912 WARN_ONCE("Do not know how to translate stencil op");
913 return STENCIL_KEEP;
914 }
915 return 0;
916 }
917
918 static void r700SetStencilState(GLcontext * ctx, GLboolean state)
919 {
920 context_t *context = R700_CONTEXT(ctx);
921 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
922 GLboolean hw_stencil = GL_FALSE;
923
924 //fixme
925 //r300CatchStencilFallback(ctx);
926
927 if (ctx->DrawBuffer) {
928 struct radeon_renderbuffer *rrbStencil
929 = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
930 hw_stencil = (rrbStencil && rrbStencil->bo);
931 }
932
933 if (hw_stencil) {
934 if (state)
935 SETbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
936 else
937 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
938 }
939 }
940
941 static void r700StencilFuncSeparate(GLcontext * ctx, GLenum face,
942 GLenum func, GLint ref, GLuint mask) //---------------------
943 {
944 context_t *context = R700_CONTEXT(ctx);
945 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
946 const unsigned back = ctx->Stencil._BackFace;
947
948 //fixme
949 //r300CatchStencilFallback(ctx);
950
951 //front
952 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.Ref[0],
953 STENCILREF_shift, STENCILREF_mask);
954 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.ValueMask[0],
955 STENCILMASK_shift, STENCILMASK_mask);
956
957 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[0]),
958 STENCILFUNC_shift, STENCILFUNC_mask);
959
960 //back
961 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.Ref[back],
962 STENCILREF_BF_shift, STENCILREF_BF_mask);
963 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.ValueMask[back],
964 STENCILMASK_BF_shift, STENCILMASK_BF_mask);
965
966 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[back]),
967 STENCILFUNC_BF_shift, STENCILFUNC_BF_mask);
968
969 }
970
971 static void r700StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) //--------------
972 {
973 context_t *context = R700_CONTEXT(ctx);
974 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
975 const unsigned back = ctx->Stencil._BackFace;
976
977 //fixme
978 //r300CatchStencilFallback(ctx);
979
980 // front
981 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.WriteMask[0],
982 STENCILWRITEMASK_shift, STENCILWRITEMASK_mask);
983
984 // back
985 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.WriteMask[back],
986 STENCILWRITEMASK_BF_shift, STENCILWRITEMASK_BF_mask);
987
988 }
989
990 static void r700StencilOpSeparate(GLcontext * ctx, GLenum face,
991 GLenum fail, GLenum zfail, GLenum zpass) //--------------------
992 {
993 context_t *context = R700_CONTEXT(ctx);
994 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
995 const unsigned back = ctx->Stencil._BackFace;
996
997 //fixme
998 //r300CatchStencilFallback(ctx);
999
1000 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[0]),
1001 STENCILFAIL_shift, STENCILFAIL_mask);
1002 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[0]),
1003 STENCILZFAIL_shift, STENCILZFAIL_mask);
1004 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[0]),
1005 STENCILZPASS_shift, STENCILZPASS_mask);
1006
1007 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[back]),
1008 STENCILFAIL_BF_shift, STENCILFAIL_BF_mask);
1009 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[back]),
1010 STENCILZFAIL_BF_shift, STENCILZFAIL_BF_mask);
1011 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[back]),
1012 STENCILZPASS_BF_shift, STENCILZPASS_BF_mask);
1013 }
1014
1015 static void r700UpdateWindow(GLcontext * ctx, int id) //--------------------
1016 {
1017 context_t *context = R700_CONTEXT(ctx);
1018 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1019 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
1020 GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
1021 GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
1022 const GLfloat *v = ctx->Viewport._WindowMap.m;
1023 const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
1024 const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
1025 GLfloat y_scale, y_bias;
1026
1027 if (render_to_fbo) {
1028 y_scale = 1.0;
1029 y_bias = 0;
1030 } else {
1031 y_scale = -1.0;
1032 y_bias = yoffset;
1033 }
1034
1035 GLfloat sx = v[MAT_SX];
1036 GLfloat tx = v[MAT_TX] + xoffset;
1037 GLfloat sy = v[MAT_SY] * y_scale;
1038 GLfloat ty = (v[MAT_TY] * y_scale) + y_bias;
1039 GLfloat sz = v[MAT_SZ] * depthScale;
1040 GLfloat tz = v[MAT_TZ] * depthScale;
1041
1042 /* TODO : Need DMA flush as well. */
1043
1044 r700->viewport[id].PA_CL_VPORT_XSCALE.f32All = sx;
1045 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
1046
1047 r700->viewport[id].PA_CL_VPORT_YSCALE.f32All = sy;
1048 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
1049
1050 r700->viewport[id].PA_CL_VPORT_ZSCALE.f32All = sz;
1051 r700->viewport[id].PA_CL_VPORT_ZOFFSET.f32All = tz;
1052
1053 r700->viewport[id].enabled = GL_TRUE;
1054
1055 r700SetScissor(context);
1056 }
1057
1058
1059 static void r700Viewport(GLcontext * ctx,
1060 GLint x,
1061 GLint y,
1062 GLsizei width,
1063 GLsizei height) //--------------------
1064 {
1065 r700UpdateWindow(ctx, 0);
1066
1067 radeon_viewport(ctx, x, y, width, height);
1068 }
1069
1070 static void r700DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) //-------------
1071 {
1072 r700UpdateWindow(ctx, 0);
1073 }
1074
1075 static void r700LineWidth(GLcontext * ctx, GLfloat widthf) //---------------
1076 {
1077 context_t *context = R700_CONTEXT(ctx);
1078 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1079 uint32_t lineWidth = (uint32_t)((widthf * 0.5) * (1 << 4));
1080 if (lineWidth > 0xFFFF)
1081 lineWidth = 0xFFFF;
1082 SETfield(r700->PA_SU_LINE_CNTL.u32All,(uint16_t)lineWidth,
1083 PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
1084 }
1085
1086 static void r700LineStipple(GLcontext *ctx, GLint factor, GLushort pattern)
1087 {
1088 context_t *context = R700_CONTEXT(ctx);
1089 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1090
1091 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, pattern, LINE_PATTERN_shift, LINE_PATTERN_mask);
1092 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, (factor-1), REPEAT_COUNT_shift, REPEAT_COUNT_mask);
1093 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, 1, AUTO_RESET_CNTL_shift, AUTO_RESET_CNTL_mask);
1094 }
1095
1096 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state)
1097 {
1098 context_t *context = R700_CONTEXT(ctx);
1099 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1100
1101 if (state) {
1102 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1103 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1104 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1105 } else {
1106 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1107 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1108 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1109 }
1110 }
1111
1112 static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) //--------------
1113 {
1114 context_t *context = R700_CONTEXT(ctx);
1115 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1116 GLfloat constant = units;
1117
1118 switch (ctx->Visual.depthBits) {
1119 case 16:
1120 constant *= 4.0;
1121 break;
1122 case 24:
1123 constant *= 2.0;
1124 break;
1125 }
1126
1127 factor *= 12.0;
1128
1129 r700->PA_SU_POLY_OFFSET_FRONT_SCALE.f32All = factor;
1130 r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.f32All = constant;
1131 r700->PA_SU_POLY_OFFSET_BACK_SCALE.f32All = factor;
1132 r700->PA_SU_POLY_OFFSET_BACK_OFFSET.f32All = constant;
1133 }
1134
1135 static void r700UpdatePolygonMode(GLcontext * ctx)
1136 {
1137 context_t *context = R700_CONTEXT(ctx);
1138 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1139
1140 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DISABLE_POLY_MODE, POLY_MODE_shift, POLY_MODE_mask);
1141
1142 /* Only do something if a polygon mode is wanted, default is GL_FILL */
1143 if (ctx->Polygon.FrontMode != GL_FILL ||
1144 ctx->Polygon.BackMode != GL_FILL) {
1145 GLenum f, b;
1146
1147 /* Handle GL_CW (clock wise and GL_CCW (counter clock wise)
1148 * correctly by selecting the correct front and back face
1149 */
1150 if (ctx->Polygon.FrontFace == GL_CCW) {
1151 f = ctx->Polygon.FrontMode;
1152 b = ctx->Polygon.BackMode;
1153 } else {
1154 f = ctx->Polygon.BackMode;
1155 b = ctx->Polygon.FrontMode;
1156 }
1157
1158 /* Enable polygon mode */
1159 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DUAL_MODE, POLY_MODE_shift, POLY_MODE_mask);
1160
1161 switch (f) {
1162 case GL_LINE:
1163 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1164 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1165 break;
1166 case GL_POINT:
1167 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1168 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1169 break;
1170 case GL_FILL:
1171 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1172 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1173 break;
1174 }
1175
1176 switch (b) {
1177 case GL_LINE:
1178 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1179 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1180 break;
1181 case GL_POINT:
1182 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1183 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1184 break;
1185 case GL_FILL:
1186 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1187 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1188 break;
1189 }
1190 }
1191 }
1192
1193 static void r700PolygonMode(GLcontext * ctx, GLenum face, GLenum mode) //------------------
1194 {
1195 (void)face;
1196 (void)mode;
1197
1198 r700UpdatePolygonMode(ctx);
1199 }
1200
1201 static void r700RenderMode(GLcontext * ctx, GLenum mode) //---------------------
1202 {
1203 }
1204
1205 static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
1206 {
1207 context_t *context = R700_CONTEXT(ctx);
1208 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1209 GLint p;
1210 GLint *ip;
1211
1212 p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
1213 ip = (GLint *)ctx->Transform._ClipUserPlane[p];
1214
1215 r700->ucp[p].PA_CL_UCP_0_X.u32All = ip[0];
1216 r700->ucp[p].PA_CL_UCP_0_Y.u32All = ip[1];
1217 r700->ucp[p].PA_CL_UCP_0_Z.u32All = ip[2];
1218 r700->ucp[p].PA_CL_UCP_0_W.u32All = ip[3];
1219 }
1220
1221 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state)
1222 {
1223 context_t *context = R700_CONTEXT(ctx);
1224 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1225 GLuint p;
1226
1227 p = cap - GL_CLIP_PLANE0;
1228 if (state) {
1229 r700->PA_CL_CLIP_CNTL.u32All |= (UCP_ENA_0_bit << p);
1230 r700->ucp[p].enabled = GL_TRUE;
1231 r700ClipPlane(ctx, cap, NULL);
1232 } else {
1233 r700->PA_CL_CLIP_CNTL.u32All &= ~(UCP_ENA_0_bit << p);
1234 r700->ucp[p].enabled = GL_FALSE;
1235 }
1236 }
1237
1238 void r700SetScissor(context_t *context) //---------------
1239 {
1240 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1241 unsigned x1, y1, x2, y2;
1242 int id = 0;
1243 struct radeon_renderbuffer *rrb;
1244
1245 rrb = radeon_get_colorbuffer(&context->radeon);
1246 if (!rrb || !rrb->bo) {
1247 return;
1248 }
1249 if (context->radeon.state.scissor.enabled) {
1250 x1 = context->radeon.state.scissor.rect.x1;
1251 y1 = context->radeon.state.scissor.rect.y1;
1252 x2 = context->radeon.state.scissor.rect.x2 - 1;
1253 y2 = context->radeon.state.scissor.rect.y2 - 1;
1254 } else {
1255 x1 = rrb->dPriv->x;
1256 y1 = rrb->dPriv->y;
1257 x2 = rrb->dPriv->x + rrb->dPriv->w;
1258 y2 = rrb->dPriv->y + rrb->dPriv->h;
1259 }
1260
1261 /* window */
1262 SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1263 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, x1,
1264 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask);
1265 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, y1,
1266 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask);
1267
1268 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, x2,
1269 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask);
1270 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, y2,
1271 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask);
1272
1273
1274 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, x1,
1275 PA_SC_CLIPRECT_0_TL__TL_X_shift, PA_SC_CLIPRECT_0_TL__TL_X_mask);
1276 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, y1,
1277 PA_SC_CLIPRECT_0_TL__TL_Y_shift, PA_SC_CLIPRECT_0_TL__TL_Y_mask);
1278 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, x2,
1279 PA_SC_CLIPRECT_0_BR__BR_X_shift, PA_SC_CLIPRECT_0_BR__BR_X_mask);
1280 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, y2,
1281 PA_SC_CLIPRECT_0_BR__BR_Y_shift, PA_SC_CLIPRECT_0_BR__BR_Y_mask);
1282
1283 r700->PA_SC_CLIPRECT_1_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1284 r700->PA_SC_CLIPRECT_1_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1285 r700->PA_SC_CLIPRECT_2_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1286 r700->PA_SC_CLIPRECT_2_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1287 r700->PA_SC_CLIPRECT_3_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1288 r700->PA_SC_CLIPRECT_3_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1289
1290 /* more....2d clip */
1291 SETbit(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1292 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, x1,
1293 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask);
1294 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, y1,
1295 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask);
1296 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, x2,
1297 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask);
1298 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, y2,
1299 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask);
1300
1301 SETbit(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1302 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, x1,
1303 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask);
1304 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, y1,
1305 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask);
1306 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, x2,
1307 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask);
1308 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, y2,
1309 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask);
1310
1311 r700->viewport[id].PA_SC_VPORT_ZMIN_0.u32All = 0;
1312 r700->viewport[id].PA_SC_VPORT_ZMAX_0.u32All = 0x3F800000;
1313 r700->viewport[id].enabled = GL_TRUE;
1314 }
1315
1316 void r700SetRenderTarget(context_t *context, int id)
1317 {
1318 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1319
1320 struct radeon_renderbuffer *rrb;
1321 unsigned int nPitchInPixel;
1322
1323 /* screen/window/view */
1324 SETfield(r700->CB_TARGET_MASK.u32All, 0xF, (4 * id), TARGET0_ENABLE_mask);
1325
1326 rrb = radeon_get_colorbuffer(&context->radeon);
1327 if (!rrb || !rrb->bo) {
1328 fprintf(stderr, "no rrb\n");
1329 return;
1330 }
1331
1332 /* color buffer */
1333 r700->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset;
1334
1335 nPitchInPixel = rrb->pitch/rrb->cpp;
1336 SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1,
1337 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
1338 SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
1339 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
1340 r700->render_target[id].CB_COLOR0_BASE.u32All = 0;
1341 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
1342 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL,
1343 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
1344 if(4 == rrb->cpp)
1345 {
1346 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_8_8_8_8,
1347 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
1348 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT, COMP_SWAP_shift, COMP_SWAP_mask);
1349 }
1350 else
1351 {
1352 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_5_6_5,
1353 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
1354 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT_REV,
1355 COMP_SWAP_shift, COMP_SWAP_mask);
1356 }
1357 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
1358 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit);
1359 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
1360
1361 r700->render_target[id].enabled = GL_TRUE;
1362 }
1363
1364 void r700SetDepthTarget(context_t *context)
1365 {
1366 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1367
1368 struct radeon_renderbuffer *rrb;
1369 unsigned int nPitchInPixel;
1370
1371 /* depth buf */
1372 r700->DB_DEPTH_SIZE.u32All = 0;
1373 r700->DB_DEPTH_BASE.u32All = 0;
1374 r700->DB_DEPTH_INFO.u32All = 0;
1375
1376 r700->DB_DEPTH_CLEAR.u32All = 0x3F800000;
1377 r700->DB_DEPTH_VIEW.u32All = 0;
1378 r700->DB_RENDER_CONTROL.u32All = 0;
1379 SETbit(r700->DB_RENDER_CONTROL.u32All, STENCIL_COMPRESS_DISABLE_bit);
1380 SETbit(r700->DB_RENDER_CONTROL.u32All, DEPTH_COMPRESS_DISABLE_bit);
1381 r700->DB_RENDER_OVERRIDE.u32All = 0;
1382 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1383 SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit);
1384 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
1385 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
1386 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
1387
1388 r700->DB_ALPHA_TO_MASK.u32All = 0;
1389 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask);
1390 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET1_shift, ALPHA_TO_MASK_OFFSET1_mask);
1391 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET2_shift, ALPHA_TO_MASK_OFFSET2_mask);
1392 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET3_shift, ALPHA_TO_MASK_OFFSET3_mask);
1393
1394 rrb = radeon_get_depthbuffer(&context->radeon);
1395 if (!rrb)
1396 return;
1397
1398 nPitchInPixel = rrb->pitch/rrb->cpp;
1399
1400 SETfield(r700->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1,
1401 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
1402 SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
1403 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */
1404
1405 if(4 == rrb->cpp)
1406 {
1407 switch (GL_CONTEXT(context)->Visual.depthBits)
1408 {
1409 case 16:
1410 case 24:
1411 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_8_24,
1412 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
1413 break;
1414 default:
1415 fprintf(stderr, "Error: Unsupported depth %d... exiting\n",
1416 GL_CONTEXT(context)->Visual.depthBits);
1417 _mesa_exit(-1);
1418 }
1419 }
1420 else
1421 {
1422 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16,
1423 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
1424 }
1425 SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_2D_TILED_THIN1,
1426 DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask);
1427 /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */
1428 }
1429
1430 static void r700InitSQConfig(GLcontext * ctx)
1431 {
1432 context_t *context = R700_CONTEXT(ctx);
1433 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1434 int ps_prio;
1435 int vs_prio;
1436 int gs_prio;
1437 int es_prio;
1438 int num_ps_gprs;
1439 int num_vs_gprs;
1440 int num_gs_gprs;
1441 int num_es_gprs;
1442 int num_temp_gprs;
1443 int num_ps_threads;
1444 int num_vs_threads;
1445 int num_gs_threads;
1446 int num_es_threads;
1447 int num_ps_stack_entries;
1448 int num_vs_stack_entries;
1449 int num_gs_stack_entries;
1450 int num_es_stack_entries;
1451
1452 // SQ
1453 ps_prio = 0;
1454 vs_prio = 1;
1455 gs_prio = 2;
1456 es_prio = 3;
1457 switch (context->radeon.radeonScreen->chip_family) {
1458 case CHIP_FAMILY_R600:
1459 num_ps_gprs = 192;
1460 num_vs_gprs = 56;
1461 num_temp_gprs = 4;
1462 num_gs_gprs = 0;
1463 num_es_gprs = 0;
1464 num_ps_threads = 136;
1465 num_vs_threads = 48;
1466 num_gs_threads = 4;
1467 num_es_threads = 4;
1468 num_ps_stack_entries = 128;
1469 num_vs_stack_entries = 128;
1470 num_gs_stack_entries = 0;
1471 num_es_stack_entries = 0;
1472 break;
1473 case CHIP_FAMILY_RV630:
1474 case CHIP_FAMILY_RV635:
1475 num_ps_gprs = 84;
1476 num_vs_gprs = 36;
1477 num_temp_gprs = 4;
1478 num_gs_gprs = 0;
1479 num_es_gprs = 0;
1480 num_ps_threads = 144;
1481 num_vs_threads = 40;
1482 num_gs_threads = 4;
1483 num_es_threads = 4;
1484 num_ps_stack_entries = 40;
1485 num_vs_stack_entries = 40;
1486 num_gs_stack_entries = 32;
1487 num_es_stack_entries = 16;
1488 break;
1489 case CHIP_FAMILY_RV610:
1490 case CHIP_FAMILY_RV620:
1491 case CHIP_FAMILY_RS780:
1492 default:
1493 num_ps_gprs = 84;
1494 num_vs_gprs = 36;
1495 num_temp_gprs = 4;
1496 num_gs_gprs = 0;
1497 num_es_gprs = 0;
1498 num_ps_threads = 136;
1499 num_vs_threads = 48;
1500 num_gs_threads = 4;
1501 num_es_threads = 4;
1502 num_ps_stack_entries = 40;
1503 num_vs_stack_entries = 40;
1504 num_gs_stack_entries = 32;
1505 num_es_stack_entries = 16;
1506 break;
1507 case CHIP_FAMILY_RV670:
1508 num_ps_gprs = 144;
1509 num_vs_gprs = 40;
1510 num_temp_gprs = 4;
1511 num_gs_gprs = 0;
1512 num_es_gprs = 0;
1513 num_ps_threads = 136;
1514 num_vs_threads = 48;
1515 num_gs_threads = 4;
1516 num_es_threads = 4;
1517 num_ps_stack_entries = 40;
1518 num_vs_stack_entries = 40;
1519 num_gs_stack_entries = 32;
1520 num_es_stack_entries = 16;
1521 break;
1522 case CHIP_FAMILY_RV770:
1523 num_ps_gprs = 192;
1524 num_vs_gprs = 56;
1525 num_temp_gprs = 4;
1526 num_gs_gprs = 0;
1527 num_es_gprs = 0;
1528 num_ps_threads = 188;
1529 num_vs_threads = 60;
1530 num_gs_threads = 0;
1531 num_es_threads = 0;
1532 num_ps_stack_entries = 256;
1533 num_vs_stack_entries = 256;
1534 num_gs_stack_entries = 0;
1535 num_es_stack_entries = 0;
1536 break;
1537 case CHIP_FAMILY_RV730:
1538 case CHIP_FAMILY_RV740:
1539 num_ps_gprs = 84;
1540 num_vs_gprs = 36;
1541 num_temp_gprs = 4;
1542 num_gs_gprs = 0;
1543 num_es_gprs = 0;
1544 num_ps_threads = 188;
1545 num_vs_threads = 60;
1546 num_gs_threads = 0;
1547 num_es_threads = 0;
1548 num_ps_stack_entries = 128;
1549 num_vs_stack_entries = 128;
1550 num_gs_stack_entries = 0;
1551 num_es_stack_entries = 0;
1552 break;
1553 case CHIP_FAMILY_RV710:
1554 num_ps_gprs = 192;
1555 num_vs_gprs = 56;
1556 num_temp_gprs = 4;
1557 num_gs_gprs = 0;
1558 num_es_gprs = 0;
1559 num_ps_threads = 144;
1560 num_vs_threads = 48;
1561 num_gs_threads = 0;
1562 num_es_threads = 0;
1563 num_ps_stack_entries = 128;
1564 num_vs_stack_entries = 128;
1565 num_gs_stack_entries = 0;
1566 num_es_stack_entries = 0;
1567 break;
1568 }
1569
1570 r700->sq_config.SQ_CONFIG.u32All = 0;
1571 if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
1572 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
1573 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
1574 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
1575 CLEARbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1576 else
1577 SETbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1578 SETbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit);
1579 SETbit(r700->sq_config.SQ_CONFIG.u32All, ALU_INST_PREFER_VECTOR_bit);
1580 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, PS_PRIO_shift, PS_PRIO_mask);
1581 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, VS_PRIO_shift, VS_PRIO_mask);
1582 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, GS_PRIO_shift, GS_PRIO_mask);
1583 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, ES_PRIO_shift, ES_PRIO_mask);
1584
1585 r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All = 0;
1586 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_ps_gprs, NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
1587 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_vs_gprs, NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
1588 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_temp_gprs,
1589 NUM_CLAUSE_TEMP_GPRS_shift, NUM_CLAUSE_TEMP_GPRS_mask);
1590
1591 r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All = 0;
1592 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_gs_gprs, NUM_GS_GPRS_shift, NUM_GS_GPRS_mask);
1593 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_es_gprs, NUM_ES_GPRS_shift, NUM_ES_GPRS_mask);
1594
1595 r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All = 0;
1596 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_ps_threads,
1597 NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
1598 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_vs_threads,
1599 NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
1600 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_gs_threads,
1601 NUM_GS_THREADS_shift, NUM_GS_THREADS_mask);
1602 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_es_threads,
1603 NUM_ES_THREADS_shift, NUM_ES_THREADS_mask);
1604
1605 r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All = 0;
1606 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_ps_stack_entries,
1607 NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
1608 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_vs_stack_entries,
1609 NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
1610
1611 r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All = 0;
1612 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_gs_stack_entries,
1613 NUM_GS_STACK_ENTRIES_shift, NUM_GS_STACK_ENTRIES_mask);
1614 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_es_stack_entries,
1615 NUM_ES_STACK_ENTRIES_shift, NUM_ES_STACK_ENTRIES_mask);
1616
1617 }
1618
1619 /**
1620 * Calculate initial hardware state and register state functions.
1621 * Assumes that the command buffer and state atoms have been
1622 * initialized already.
1623 */
1624 void r700InitState(GLcontext * ctx) //-------------------
1625 {
1626 context_t *context = R700_CONTEXT(ctx);
1627
1628 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1629
1630 r700->TA_CNTL_AUX.u32All = 0;
1631 SETfield(r700->TA_CNTL_AUX.u32All, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask);
1632 r700->VC_ENHANCE.u32All = 0;
1633 r700->DB_WATERMARKS.u32All = 0;
1634 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_FREE_shift, DEPTH_FREE_mask);
1635 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_FLUSH_shift, DEPTH_FLUSH_mask);
1636 SETfield(r700->DB_WATERMARKS.u32All, 0, FORCE_SUMMARIZE_shift, FORCE_SUMMARIZE_mask);
1637 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_PENDING_FREE_shift, DEPTH_PENDING_FREE_mask);
1638 r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All = 0;
1639 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1640 SETfield(r700->TA_CNTL_AUX.u32All, 3, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1641 r700->DB_DEBUG.u32All = 0x82000000;
1642 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1643 } else {
1644 SETfield(r700->TA_CNTL_AUX.u32All, 2, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1645 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1646 SETbit(r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All, VS_PC_LIMIT_ENABLE_bit);
1647 }
1648
1649 /* Turn off vgt reuse */
1650 r700->VGT_REUSE_OFF.u32All = 0;
1651 SETbit(r700->VGT_REUSE_OFF.u32All, REUSE_OFF_bit);
1652
1653 /* Specify offsetting and clamp values for vertices */
1654 r700->VGT_MAX_VTX_INDX.u32All = 0xFFFFFF;
1655 r700->VGT_MIN_VTX_INDX.u32All = 0;
1656 r700->VGT_INDX_OFFSET.u32All = 0;
1657
1658 /* default shader connections. */
1659 r700->SPI_VS_OUT_ID_0.u32All = 0x03020100;
1660 r700->SPI_VS_OUT_ID_1.u32All = 0x07060504;
1661
1662 r700->SPI_PS_INPUT_CNTL_0.u32All = 0x00000800;
1663 r700->SPI_PS_INPUT_CNTL_1.u32All = 0x00000801;
1664 r700->SPI_PS_INPUT_CNTL_2.u32All = 0x00000802;
1665
1666 r700->SPI_THREAD_GROUPING.u32All = 0;
1667 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
1668 SETfield(r700->SPI_THREAD_GROUPING.u32All, 1, PS_GROUPING_shift, PS_GROUPING_mask);
1669
1670 /* screen */
1671 r700->PA_SC_SCREEN_SCISSOR_TL.u32All = 0x0;
1672
1673 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All,
1674 ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->width,
1675 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask);
1676 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All,
1677 ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->height,
1678 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask);
1679
1680 /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
1681 r700->PA_SC_CLIPRECT_RULE.u32All = 0;
1682 SETfield(r700->PA_SC_CLIPRECT_RULE.u32All, CLIP_RULE_mask, CLIP_RULE_shift, CLIP_RULE_mask);
1683
1684 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1685 r700->PA_SC_EDGERULE.u32All = 0;
1686 else
1687 r700->PA_SC_EDGERULE.u32All = 0xAAAAAAAA;
1688
1689 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1690 r700->PA_SC_MODE_CNTL.u32All = 0;
1691 SETbit(r700->PA_SC_MODE_CNTL.u32All, WALK_ORDER_ENABLE_bit);
1692 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1693 } else {
1694 r700->PA_SC_MODE_CNTL.u32All = 0x00500000;
1695 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_REZ_ENABLE_bit);
1696 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1697 }
1698
1699 /* Do scale XY and Z by 1/W0. */
1700 r700->bEnablePerspective = GL_TRUE;
1701 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
1702 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
1703 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
1704
1705 /* Enable viewport scaling for all three axis */
1706 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_SCALE_ENA_bit);
1707 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_OFFSET_ENA_bit);
1708 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_SCALE_ENA_bit);
1709 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_OFFSET_ENA_bit);
1710 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_SCALE_ENA_bit);
1711 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_OFFSET_ENA_bit);
1712
1713 /* GL uses last vtx for flat shading components */
1714 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
1715
1716 /* Set up vertex control */
1717 r700->PA_SU_VTX_CNTL.u32All = 0;
1718 CLEARfield(r700->PA_SU_VTX_CNTL.u32All, QUANT_MODE_mask);
1719 SETbit(r700->PA_SU_VTX_CNTL.u32All, PIX_CENTER_bit);
1720 SETfield(r700->PA_SU_VTX_CNTL.u32All, X_ROUND_TO_EVEN,
1721 PA_SU_VTX_CNTL__ROUND_MODE_shift, PA_SU_VTX_CNTL__ROUND_MODE_mask);
1722
1723 /* to 1.0 = no guard band */
1724 r700->PA_CL_GB_VERT_CLIP_ADJ.u32All = 0x3F800000; /* 1.0 */
1725 r700->PA_CL_GB_VERT_DISC_ADJ.u32All = 0x3F800000;
1726 r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All = 0x3F800000;
1727 r700->PA_CL_GB_HORZ_DISC_ADJ.u32All = 0x3F800000;
1728
1729 /* Enable all samples for multi-sample anti-aliasing */
1730 r700->PA_SC_AA_MASK.u32All = 0xFFFFFFFF;
1731 /* Turn off AA */
1732 r700->PA_SC_AA_CONFIG.u32All = 0;
1733
1734 r700->SX_MISC.u32All = 0;
1735
1736 r700InitSQConfig(ctx);
1737
1738 r700ColorMask(ctx,
1739 ctx->Color.ColorMask[RCOMP],
1740 ctx->Color.ColorMask[GCOMP],
1741 ctx->Color.ColorMask[BCOMP],
1742 ctx->Color.ColorMask[ACOMP]);
1743
1744 r700Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test);
1745 r700DepthMask(ctx, ctx->Depth.Mask);
1746 r700DepthFunc(ctx, ctx->Depth.Func);
1747 SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
1748
1749 /* stencil */
1750 r700Enable(ctx, GL_STENCIL_TEST, ctx->Stencil._Enabled);
1751 r700StencilMaskSeparate(ctx, 0, ctx->Stencil.WriteMask[0]);
1752 r700StencilFuncSeparate(ctx, 0, ctx->Stencil.Function[0],
1753 ctx->Stencil.Ref[0], ctx->Stencil.ValueMask[0]);
1754 r700StencilOpSeparate(ctx, 0, ctx->Stencil.FailFunc[0],
1755 ctx->Stencil.ZFailFunc[0],
1756 ctx->Stencil.ZPassFunc[0]);
1757
1758 r700UpdateCulling(ctx);
1759
1760 r700SetBlendState(ctx);
1761 r700SetLogicOpState(ctx);
1762
1763 r700AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef);
1764 r700Enable(ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled);
1765
1766 r700PointSize(ctx, 1.0);
1767
1768 CLEARfield(r700->PA_SU_POINT_MINMAX.u32All, MIN_SIZE_mask);
1769 SETfield(r700->PA_SU_POINT_MINMAX.u32All, 0x8000, MAX_SIZE_shift, MAX_SIZE_mask);
1770
1771 r700LineWidth(ctx, 1.0);
1772
1773 r700->PA_SC_LINE_CNTL.u32All = 0;
1774 CLEARbit(r700->PA_SC_LINE_CNTL.u32All, EXPAND_LINE_WIDTH_bit);
1775 SETbit(r700->PA_SC_LINE_CNTL.u32All, LAST_PIXEL_bit);
1776
1777 r700ShadeModel(ctx, ctx->Light.ShadeModel);
1778 r700PolygonMode(ctx, GL_FRONT, ctx->Polygon.FrontMode);
1779 r700PolygonMode(ctx, GL_BACK, ctx->Polygon.BackMode);
1780 r700PolygonOffset(ctx, ctx->Polygon.OffsetFactor,
1781 ctx->Polygon.OffsetUnits);
1782 r700Enable(ctx, GL_POLYGON_OFFSET_POINT, ctx->Polygon.OffsetPoint);
1783 r700Enable(ctx, GL_POLYGON_OFFSET_LINE, ctx->Polygon.OffsetLine);
1784 r700Enable(ctx, GL_POLYGON_OFFSET_FILL, ctx->Polygon.OffsetFill);
1785
1786 /* CB */
1787 r700BlendColor(ctx, ctx->Color.BlendColor);
1788
1789 r700->CB_CLEAR_RED_R6XX.f32All = 1.0; //r6xx only
1790 r700->CB_CLEAR_GREEN_R6XX.f32All = 0.0; //r6xx only
1791 r700->CB_CLEAR_BLUE_R6XX.f32All = 1.0; //r6xx only
1792 r700->CB_CLEAR_ALPHA_R6XX.f32All = 1.0; //r6xx only
1793 r700->CB_FOG_RED_R6XX.u32All = 0; //r6xx only
1794 r700->CB_FOG_GREEN_R6XX.u32All = 0; //r6xx only
1795 r700->CB_FOG_BLUE_R6XX.u32All = 0; //r6xx only
1796
1797 /* Disable color compares */
1798 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1799 CLRCMP_FCN_SRC_shift, CLRCMP_FCN_SRC_mask);
1800 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1801 CLRCMP_FCN_DST_shift, CLRCMP_FCN_DST_mask);
1802 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_SEL_SRC,
1803 CLRCMP_FCN_SEL_shift, CLRCMP_FCN_SEL_mask);
1804
1805 /* Zero out source */
1806 r700->CB_CLRCMP_SRC.u32All = 0x00000000;
1807
1808 /* Put a compare color in for error checking */
1809 r700->CB_CLRCMP_DST.u32All = 0x000000FF;
1810
1811 /* Set up color compare mask */
1812 r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF;
1813
1814 }
1815
1816 void r700InitStateFuncs(struct dd_function_table *functions) //-----------------
1817 {
1818 functions->UpdateState = r700InvalidateState;
1819 functions->AlphaFunc = r700AlphaFunc;
1820 functions->BlendColor = r700BlendColor;
1821 functions->BlendEquationSeparate = r700BlendEquationSeparate;
1822 functions->BlendFuncSeparate = r700BlendFuncSeparate;
1823 functions->Enable = r700Enable;
1824 functions->ColorMask = r700ColorMask;
1825 functions->DepthFunc = r700DepthFunc;
1826 functions->DepthMask = r700DepthMask;
1827 functions->CullFace = r700CullFace;
1828 functions->Fogfv = r700Fogfv;
1829 functions->FrontFace = r700FrontFace;
1830 functions->ShadeModel = r700ShadeModel;
1831 functions->LogicOpcode = r700LogicOpcode;
1832
1833 /* ARB_point_parameters */
1834 functions->PointParameterfv = r700PointParameter;
1835
1836 /* Stencil related */
1837 functions->StencilFuncSeparate = r700StencilFuncSeparate;
1838 functions->StencilMaskSeparate = r700StencilMaskSeparate;
1839 functions->StencilOpSeparate = r700StencilOpSeparate;
1840
1841 /* Viewport related */
1842 functions->Viewport = r700Viewport;
1843 functions->DepthRange = r700DepthRange;
1844 functions->PointSize = r700PointSize;
1845 functions->LineWidth = r700LineWidth;
1846 functions->LineStipple = r700LineStipple;
1847
1848 functions->PolygonOffset = r700PolygonOffset;
1849 functions->PolygonMode = r700PolygonMode;
1850
1851 functions->RenderMode = r700RenderMode;
1852
1853 functions->ClipPlane = r700ClipPlane;
1854
1855 functions->Scissor = radeonScissor;
1856
1857 functions->DrawBuffer = radeonDrawBuffer;
1858 functions->ReadBuffer = radeonReadBuffer;
1859
1860 }
1861