2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/imports.h"
30 #include "main/enums.h"
31 #include "main/macros.h"
32 #include "main/context.h"
34 #include "main/simple_list.h"
35 #include "main/state.h"
38 #include "tnl/t_pipeline.h"
39 #include "swrast/swrast.h"
40 #include "swrast_setup/swrast_setup.h"
41 #include "main/api_arrayelt.h"
42 #include "main/framebuffer.h"
43 #include "drivers/common/meta.h"
45 #include "program/prog_parameter.h"
46 #include "program/prog_statevars.h"
49 #include "r600_context.h"
51 #include "r700_state.h"
53 #include "r700_fragprog.h"
54 #include "r700_vertprog.h"
56 void r600UpdateTextureState(struct gl_context
* ctx
);
57 static void r700SetClipPlaneState(struct gl_context
* ctx
, GLenum cap
, GLboolean state
);
58 static void r700UpdatePolygonMode(struct gl_context
* ctx
);
59 static void r700SetPolygonOffsetState(struct gl_context
* ctx
, GLboolean state
);
60 static void r700SetStencilState(struct gl_context
* ctx
, GLboolean state
);
61 static void r700UpdateWindow(struct gl_context
* ctx
, int id
);
63 void r700UpdateShaders(struct gl_context
* ctx
)
65 context_t
*context
= R700_CONTEXT(ctx
);
67 /* should only happenen once, just after context is created */
68 /* TODO: shouldn't we fallback to sw here? */
69 if (!ctx
->FragmentProgram
._Current
) {
70 fprintf(stderr
, "No ctx->FragmentProgram._Current!!\n");
74 r700SelectFragmentShader(ctx
);
76 r700SelectVertexShader(ctx
);
77 r700UpdateStateParameters(ctx
, _NEW_PROGRAM
| _NEW_PROGRAM_CONSTANTS
);
78 context
->radeon
.NewGLState
= 0;
82 * To correctly position primitives:
84 void r700UpdateViewportOffset(struct gl_context
* ctx
) //------------------
86 context_t
*context
= R700_CONTEXT(ctx
);
87 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
88 __DRIdrawable
*dPriv
= radeon_get_drawable(&context
->radeon
);
89 GLfloat xoffset
= (GLfloat
) dPriv
->x
;
90 GLfloat yoffset
= (GLfloat
) dPriv
->y
+ dPriv
->h
;
91 const GLfloat
*v
= ctx
->Viewport
._WindowMap
.m
;
94 GLfloat tx
= v
[MAT_TX
] + xoffset
;
95 GLfloat ty
= (-v
[MAT_TY
]) + yoffset
;
97 if (r700
->viewport
[id
].PA_CL_VPORT_XOFFSET
.f32All
!= tx
||
98 r700
->viewport
[id
].PA_CL_VPORT_YOFFSET
.f32All
!= ty
) {
99 /* Note: this should also modify whatever data the context reset
102 R600_STATECHANGE(context
, vpt
);
103 r700
->viewport
[id
].PA_CL_VPORT_XOFFSET
.f32All
= tx
;
104 r700
->viewport
[id
].PA_CL_VPORT_YOFFSET
.f32All
= ty
;
107 radeonUpdateScissor(ctx
);
110 void r700UpdateStateParameters(struct gl_context
* ctx
, GLuint new_state
) //--------------------
112 struct r700_fragment_program
*fp
=
113 (struct r700_fragment_program
*)ctx
->FragmentProgram
._Current
;
114 struct gl_program_parameter_list
*paramList
;
116 if (!(new_state
& (_NEW_BUFFERS
| _NEW_PROGRAM
| _NEW_PROGRAM_CONSTANTS
)))
119 if (!ctx
->FragmentProgram
._Current
|| !fp
)
122 paramList
= ctx
->FragmentProgram
._Current
->Base
.Parameters
;
127 _mesa_load_state_parameters(ctx
, paramList
);
132 * Called by Mesa after an internal state update.
134 static void r700InvalidateState(struct gl_context
* ctx
, GLuint new_state
) //-------------------
136 context_t
*context
= R700_CONTEXT(ctx
);
138 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
140 _swrast_InvalidateState(ctx
, new_state
);
141 _swsetup_InvalidateState(ctx
, new_state
);
142 _vbo_InvalidateState(ctx
, new_state
);
143 _tnl_InvalidateState(ctx
, new_state
);
144 _ae_invalidate_state(ctx
, new_state
);
146 if (new_state
& _NEW_BUFFERS
) {
147 _mesa_update_framebuffer(ctx
);
148 /* this updates the DrawBuffer's Width/Height if it's a FBO */
149 _mesa_update_draw_buffer_bounds(ctx
);
151 R600_STATECHANGE(context
, cb_target
);
152 R600_STATECHANGE(context
, db_target
);
155 if (new_state
& (_NEW_LIGHT
)) {
156 R600_STATECHANGE(context
, su
);
157 if (ctx
->Light
.ProvokingVertex
== GL_LAST_VERTEX_CONVENTION
)
158 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, PROVOKING_VTX_LAST_bit
);
160 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, PROVOKING_VTX_LAST_bit
);
163 r700UpdateStateParameters(ctx
, new_state
);
165 R600_STATECHANGE(context
, cl
);
166 R600_STATECHANGE(context
, spi
);
168 if(GL_TRUE
== r700
->bEnablePerspective
)
170 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
171 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_XY_FMT_bit
);
172 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_Z_FMT_bit
);
174 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_W0_FMT_bit
);
176 SETbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, PERSP_GRADIENT_ENA_bit
);
177 CLEARbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, LINEAR_GRADIENT_ENA_bit
);
181 /* For orthogonal case. */
182 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_XY_FMT_bit
);
183 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_Z_FMT_bit
);
185 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_W0_FMT_bit
);
187 CLEARbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, PERSP_GRADIENT_ENA_bit
);
188 SETbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, LINEAR_GRADIENT_ENA_bit
);
191 context
->radeon
.NewGLState
|= new_state
;
194 static void r700SetDBRenderState(struct gl_context
* ctx
)
196 context_t
*context
= R700_CONTEXT(ctx
);
197 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
198 struct r700_fragment_program
*fp
= (struct r700_fragment_program
*)
199 (ctx
->FragmentProgram
._Current
);
201 R600_STATECHANGE(context
, db
);
203 SETbit(r700
->DB_SHADER_CONTROL
.u32All
, DUAL_EXPORT_ENABLE_bit
);
204 SETfield(r700
->DB_SHADER_CONTROL
.u32All
, EARLY_Z_THEN_LATE_Z
, Z_ORDER_shift
, Z_ORDER_mask
);
205 /* XXX need to enable htile for hiz/s */
206 SETfield(r700
->DB_RENDER_OVERRIDE
.u32All
, FORCE_DISABLE
, FORCE_HIZ_ENABLE_shift
, FORCE_HIZ_ENABLE_mask
);
207 SETfield(r700
->DB_RENDER_OVERRIDE
.u32All
, FORCE_DISABLE
, FORCE_HIS_ENABLE0_shift
, FORCE_HIS_ENABLE0_mask
);
208 SETfield(r700
->DB_RENDER_OVERRIDE
.u32All
, FORCE_DISABLE
, FORCE_HIS_ENABLE1_shift
, FORCE_HIS_ENABLE1_mask
);
210 if (context
->radeon
.query
.current
)
212 SETbit(r700
->DB_RENDER_OVERRIDE
.u32All
, NOOP_CULL_DISABLE_bit
);
213 if (context
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV770
)
215 SETbit(r700
->DB_RENDER_CONTROL
.u32All
, PERFECT_ZPASS_COUNTS_bit
);
220 CLEARbit(r700
->DB_RENDER_OVERRIDE
.u32All
, NOOP_CULL_DISABLE_bit
);
221 if (context
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV770
)
223 CLEARbit(r700
->DB_RENDER_CONTROL
.u32All
, PERFECT_ZPASS_COUNTS_bit
);
229 if (fp
->r700Shader
.killIsUsed
)
231 SETbit(r700
->DB_SHADER_CONTROL
.u32All
, KILL_ENABLE_bit
);
235 CLEARbit(r700
->DB_SHADER_CONTROL
.u32All
, KILL_ENABLE_bit
);
238 if (fp
->r700Shader
.depthIsExported
)
240 SETbit(r700
->DB_SHADER_CONTROL
.u32All
, Z_EXPORT_ENABLE_bit
);
244 CLEARbit(r700
->DB_SHADER_CONTROL
.u32All
, Z_EXPORT_ENABLE_bit
);
249 void r700UpdateShaderStates(struct gl_context
* ctx
)
251 r700SetDBRenderState(ctx
);
252 r600UpdateTextureState(ctx
);
255 static void r700SetDepthState(struct gl_context
* ctx
)
257 struct radeon_renderbuffer
*rrb
;
258 context_t
*context
= R700_CONTEXT(ctx
);
259 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
261 R600_STATECHANGE(context
, db
);
263 rrb
= radeon_get_depthbuffer(&context
->radeon
);
265 if (ctx
->Depth
.Test
&& rrb
&& rrb
->bo
)
267 SETbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_ENABLE_bit
);
270 SETbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_WRITE_ENABLE_bit
);
274 CLEARbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_WRITE_ENABLE_bit
);
277 switch (ctx
->Depth
.Func
)
280 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_NEVER
,
281 ZFUNC_shift
, ZFUNC_mask
);
284 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_LESS
,
285 ZFUNC_shift
, ZFUNC_mask
);
288 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_EQUAL
,
289 ZFUNC_shift
, ZFUNC_mask
);
292 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_LEQUAL
,
293 ZFUNC_shift
, ZFUNC_mask
);
296 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_GREATER
,
297 ZFUNC_shift
, ZFUNC_mask
);
300 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_NOTEQUAL
,
301 ZFUNC_shift
, ZFUNC_mask
);
304 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_GEQUAL
,
305 ZFUNC_shift
, ZFUNC_mask
);
308 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_ALWAYS
,
309 ZFUNC_shift
, ZFUNC_mask
);
312 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_ALWAYS
,
313 ZFUNC_shift
, ZFUNC_mask
);
319 CLEARbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_ENABLE_bit
);
320 CLEARbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_WRITE_ENABLE_bit
);
324 static void r700SetAlphaState(struct gl_context
* ctx
)
326 context_t
*context
= R700_CONTEXT(ctx
);
327 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
328 uint32_t alpha_func
= REF_ALWAYS
;
329 GLboolean really_enabled
= ctx
->Color
.AlphaEnabled
;
331 R600_STATECHANGE(context
, sx
);
333 switch (ctx
->Color
.AlphaFunc
) {
335 alpha_func
= REF_NEVER
;
338 alpha_func
= REF_LESS
;
341 alpha_func
= REF_EQUAL
;
344 alpha_func
= REF_LEQUAL
;
347 alpha_func
= REF_GREATER
;
350 alpha_func
= REF_NOTEQUAL
;
353 alpha_func
= REF_GEQUAL
;
356 /*alpha_func = REF_ALWAYS; */
357 really_enabled
= GL_FALSE
;
361 if (really_enabled
) {
362 SETfield(r700
->SX_ALPHA_TEST_CONTROL
.u32All
, alpha_func
,
363 ALPHA_FUNC_shift
, ALPHA_FUNC_mask
);
364 SETbit(r700
->SX_ALPHA_TEST_CONTROL
.u32All
, ALPHA_TEST_ENABLE_bit
);
365 r700
->SX_ALPHA_REF
.f32All
= ctx
->Color
.AlphaRef
;
367 CLEARbit(r700
->SX_ALPHA_TEST_CONTROL
.u32All
, ALPHA_TEST_ENABLE_bit
);
372 static void r700AlphaFunc(struct gl_context
* ctx
, GLenum func
, GLfloat ref
) //---------------
376 r700SetAlphaState(ctx
);
380 static void r700BlendColor(struct gl_context
* ctx
, const GLfloat cf
[4]) //----------------
382 context_t
*context
= R700_CONTEXT(ctx
);
383 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
385 R600_STATECHANGE(context
, blnd_clr
);
387 r700
->CB_BLEND_RED
.f32All
= cf
[0];
388 r700
->CB_BLEND_GREEN
.f32All
= cf
[1];
389 r700
->CB_BLEND_BLUE
.f32All
= cf
[2];
390 r700
->CB_BLEND_ALPHA
.f32All
= cf
[3];
393 static int blend_factor(GLenum factor
, GLboolean is_src
)
403 return BLEND_DST_COLOR
;
405 case GL_ONE_MINUS_DST_COLOR
:
406 return BLEND_ONE_MINUS_DST_COLOR
;
409 return BLEND_SRC_COLOR
;
411 case GL_ONE_MINUS_SRC_COLOR
:
412 return BLEND_ONE_MINUS_SRC_COLOR
;
415 return BLEND_SRC_ALPHA
;
417 case GL_ONE_MINUS_SRC_ALPHA
:
418 return BLEND_ONE_MINUS_SRC_ALPHA
;
421 return BLEND_DST_ALPHA
;
423 case GL_ONE_MINUS_DST_ALPHA
:
424 return BLEND_ONE_MINUS_DST_ALPHA
;
426 case GL_SRC_ALPHA_SATURATE
:
427 return (is_src
) ? BLEND_SRC_ALPHA_SATURATE
: BLEND_ZERO
;
429 case GL_CONSTANT_COLOR
:
430 return BLEND_CONSTANT_COLOR
;
432 case GL_ONE_MINUS_CONSTANT_COLOR
:
433 return BLEND_ONE_MINUS_CONSTANT_COLOR
;
435 case GL_CONSTANT_ALPHA
:
436 return BLEND_CONSTANT_ALPHA
;
438 case GL_ONE_MINUS_CONSTANT_ALPHA
:
439 return BLEND_ONE_MINUS_CONSTANT_ALPHA
;
442 fprintf(stderr
, "unknown blend factor %x\n", factor
);
443 return (is_src
) ? BLEND_ONE
: BLEND_ZERO
;
448 static void r700SetBlendState(struct gl_context
* ctx
)
450 context_t
*context
= R700_CONTEXT(ctx
);
451 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
453 uint32_t blend_reg
= 0, eqn
, eqnA
;
455 R600_STATECHANGE(context
, blnd
);
457 if (ctx
->Color
.ColorLogicOpEnabled
|| !ctx
->Color
.BlendEnabled
) {
459 BLEND_ONE
, COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
461 BLEND_ZERO
, COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
463 COMB_DST_PLUS_SRC
, COLOR_COMB_FCN_shift
, COLOR_COMB_FCN_mask
);
465 BLEND_ONE
, ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
467 BLEND_ZERO
, ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
469 COMB_DST_PLUS_SRC
, ALPHA_COMB_FCN_shift
, ALPHA_COMB_FCN_mask
);
470 if (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_R600
)
471 r700
->CB_BLEND_CONTROL
.u32All
= blend_reg
;
473 r700
->render_target
[id
].CB_BLEND0_CONTROL
.u32All
= blend_reg
;
478 blend_factor(ctx
->Color
.Blend
[0].SrcRGB
, GL_TRUE
),
479 COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
481 blend_factor(ctx
->Color
.Blend
[0].DstRGB
, GL_FALSE
),
482 COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
484 switch (ctx
->Color
.Blend
[0].EquationRGB
) {
486 eqn
= COMB_DST_PLUS_SRC
;
488 case GL_FUNC_SUBTRACT
:
489 eqn
= COMB_SRC_MINUS_DST
;
491 case GL_FUNC_REVERSE_SUBTRACT
:
492 eqn
= COMB_DST_MINUS_SRC
;
495 eqn
= COMB_MIN_DST_SRC
;
498 COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
501 COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
504 eqn
= COMB_MAX_DST_SRC
;
507 COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
510 COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
515 "[%s:%u] Invalid RGB blend equation (0x%04x).\n",
516 __FUNCTION__
, __LINE__
, ctx
->Color
.Blend
[0].EquationRGB
);
520 eqn
, COLOR_COMB_FCN_shift
, COLOR_COMB_FCN_mask
);
523 blend_factor(ctx
->Color
.Blend
[0].SrcA
, GL_TRUE
),
524 ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
526 blend_factor(ctx
->Color
.Blend
[0].DstA
, GL_FALSE
),
527 ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
529 switch (ctx
->Color
.Blend
[0].EquationA
) {
531 eqnA
= COMB_DST_PLUS_SRC
;
533 case GL_FUNC_SUBTRACT
:
534 eqnA
= COMB_SRC_MINUS_DST
;
536 case GL_FUNC_REVERSE_SUBTRACT
:
537 eqnA
= COMB_DST_MINUS_SRC
;
540 eqnA
= COMB_MIN_DST_SRC
;
543 ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
546 ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
549 eqnA
= COMB_MAX_DST_SRC
;
552 ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
555 ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
559 "[%s:%u] Invalid A blend equation (0x%04x).\n",
560 __FUNCTION__
, __LINE__
, ctx
->Color
.Blend
[0].EquationA
);
565 eqnA
, ALPHA_COMB_FCN_shift
, ALPHA_COMB_FCN_mask
);
567 SETbit(blend_reg
, SEPARATE_ALPHA_BLEND_bit
);
569 if (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_R600
)
570 r700
->CB_BLEND_CONTROL
.u32All
= blend_reg
;
572 r700
->render_target
[id
].CB_BLEND0_CONTROL
.u32All
= blend_reg
;
573 SETbit(r700
->CB_COLOR_CONTROL
.u32All
, PER_MRT_BLEND_bit
);
575 SETfield(r700
->CB_COLOR_CONTROL
.u32All
, (1 << id
),
576 TARGET_BLEND_ENABLE_shift
, TARGET_BLEND_ENABLE_mask
);
580 static void r700BlendEquationSeparate(struct gl_context
* ctx
,
581 GLenum modeRGB
, GLenum modeA
) //-----------------
583 r700SetBlendState(ctx
);
586 static void r700BlendFuncSeparate(struct gl_context
* ctx
,
587 GLenum sfactorRGB
, GLenum dfactorRGB
,
588 GLenum sfactorA
, GLenum dfactorA
) //------------------------
590 r700SetBlendState(ctx
);
594 * Translate LogicOp enums into hardware representation.
596 static GLuint
translate_logicop(GLenum logicop
)
605 case GL_COPY_INVERTED
:
625 case GL_AND_INVERTED
:
632 fprintf(stderr
, "unknown blend logic operation %x\n", logicop
);
638 * Used internally to update the r300->hw hardware state to match the
639 * current OpenGL state.
641 static void r700SetLogicOpState(struct gl_context
*ctx
)
643 context_t
*context
= R700_CONTEXT(ctx
);
644 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&R700_CONTEXT(ctx
)->hw
);
646 R600_STATECHANGE(context
, blnd
);
648 if (ctx
->Color
.ColorLogicOpEnabled
)
649 SETfield(r700
->CB_COLOR_CONTROL
.u32All
,
650 translate_logicop(ctx
->Color
.LogicOp
), ROP3_shift
, ROP3_mask
);
652 SETfield(r700
->CB_COLOR_CONTROL
.u32All
, 0xCC, ROP3_shift
, ROP3_mask
);
656 * Called by Mesa when an application program changes the LogicOp state
659 static void r700LogicOpcode(struct gl_context
*ctx
, GLenum logicop
)
661 if (ctx
->Color
.ColorLogicOpEnabled
)
662 r700SetLogicOpState(ctx
);
665 static void r700UpdateCulling(struct gl_context
* ctx
)
667 context_t
*context
= R700_CONTEXT(ctx
);
668 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&R700_CONTEXT(ctx
)->hw
);
670 R600_STATECHANGE(context
, su
);
672 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
);
673 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
674 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
676 if (ctx
->Polygon
.CullFlag
)
678 switch (ctx
->Polygon
.CullFaceMode
)
681 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
682 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
685 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
686 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
688 case GL_FRONT_AND_BACK
:
689 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
690 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
693 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
694 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
699 switch (ctx
->Polygon
.FrontFace
)
702 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
);
705 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
);
708 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
); /* default: ccw */
712 /* Winding is inverted when rendering to FBO */
713 if (ctx
->DrawBuffer
&& ctx
->DrawBuffer
->Name
)
714 r700
->PA_SU_SC_MODE_CNTL
.u32All
^= FACE_bit
;
717 static void r700UpdateLineStipple(struct gl_context
* ctx
)
719 context_t
*context
= R700_CONTEXT(ctx
);
720 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&R700_CONTEXT(ctx
)->hw
);
722 R600_STATECHANGE(context
, sc
);
724 if (ctx
->Line
.StippleFlag
)
726 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, LINE_STIPPLE_ENABLE_bit
);
730 CLEARbit(r700
->PA_SC_MODE_CNTL
.u32All
, LINE_STIPPLE_ENABLE_bit
);
734 static void r700Enable(struct gl_context
* ctx
, GLenum cap
, GLboolean state
) //------------------
736 context_t
*context
= R700_CONTEXT(ctx
);
748 r700SetAlphaState(ctx
);
750 case GL_COLOR_LOGIC_OP
:
751 r700SetLogicOpState(ctx
);
752 /* fall-through, because logic op overrides blending */
754 r700SetBlendState(ctx
);
762 r700SetClipPlaneState(ctx
, cap
, state
);
765 r700SetDepthState(ctx
);
767 case GL_STENCIL_TEST
:
768 r700SetStencilState(ctx
, state
);
771 r700UpdateCulling(ctx
);
773 case GL_POLYGON_OFFSET_POINT
:
774 case GL_POLYGON_OFFSET_LINE
:
775 case GL_POLYGON_OFFSET_FILL
:
776 r700SetPolygonOffsetState(ctx
, state
);
778 case GL_SCISSOR_TEST
:
779 radeon_firevertices(&context
->radeon
);
780 context
->radeon
.state
.scissor
.enabled
= state
;
781 radeonUpdateScissor(ctx
);
783 case GL_LINE_STIPPLE
:
784 r700UpdateLineStipple(ctx
);
787 r700UpdateWindow(ctx
, 0);
796 * Handle glColorMask()
798 static void r700ColorMask(struct gl_context
* ctx
,
799 GLboolean r
, GLboolean g
, GLboolean b
, GLboolean a
) //------------------
801 context_t
*context
= R700_CONTEXT(ctx
);
802 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&R700_CONTEXT(ctx
)->hw
);
803 unsigned int mask
= ((r
? 1 : 0) |
808 if (mask
!= r700
->CB_TARGET_MASK
.u32All
) {
809 R600_STATECHANGE(context
, cb
);
810 SETfield(r700
->CB_TARGET_MASK
.u32All
, mask
, TARGET0_ENABLE_shift
, TARGET0_ENABLE_mask
);
815 * Change the depth testing function.
817 * \note Mesa already filters redundant calls to this function.
819 static void r700DepthFunc(struct gl_context
* ctx
, GLenum func
) //--------------------
821 r700SetDepthState(ctx
);
825 * Enable/Disable depth writing.
827 * \note Mesa already filters redundant calls to this function.
829 static void r700DepthMask(struct gl_context
* ctx
, GLboolean mask
) //------------------
831 r700SetDepthState(ctx
);
835 * Change the culling mode.
837 * \note Mesa already filters redundant calls to this function.
839 static void r700CullFace(struct gl_context
* ctx
, GLenum mode
) //-----------------
841 r700UpdateCulling(ctx
);
844 /* =============================================================
847 static void r700Fogfv(struct gl_context
* ctx
, GLenum pname
, const GLfloat
* param
) //--------------
852 * Change the polygon orientation.
854 * \note Mesa already filters redundant calls to this function.
856 static void r700FrontFace(struct gl_context
* ctx
, GLenum mode
) //------------------
858 r700UpdateCulling(ctx
);
859 r700UpdatePolygonMode(ctx
);
862 static void r700ShadeModel(struct gl_context
* ctx
, GLenum mode
) //--------------------
864 context_t
*context
= R700_CONTEXT(ctx
);
865 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
867 R600_STATECHANGE(context
, spi
);
869 /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */
872 SETbit(r700
->SPI_INTERP_CONTROL_0
.u32All
, FLAT_SHADE_ENA_bit
);
875 CLEARbit(r700
->SPI_INTERP_CONTROL_0
.u32All
, FLAT_SHADE_ENA_bit
);
882 /* =============================================================
885 static void r700PointSize(struct gl_context
* ctx
, GLfloat size
)
887 context_t
*context
= R700_CONTEXT(ctx
);
888 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
890 R600_STATECHANGE(context
, su
);
892 /* We need to clamp to user defined range here, because
893 * the HW clamping happens only for per vertex point size. */
894 size
= CLAMP(size
, ctx
->Point
.MinSize
, ctx
->Point
.MaxSize
);
896 /* same size limits for AA, non-AA points */
897 size
= CLAMP(size
, ctx
->Const
.MinPointSize
, ctx
->Const
.MaxPointSize
);
899 /* format is 12.4 fixed point */
900 SETfield(r700
->PA_SU_POINT_SIZE
.u32All
, (int)(size
* 8.0),
901 PA_SU_POINT_SIZE__HEIGHT_shift
, PA_SU_POINT_SIZE__HEIGHT_mask
);
902 SETfield(r700
->PA_SU_POINT_SIZE
.u32All
, (int)(size
* 8.0),
903 PA_SU_POINT_SIZE__WIDTH_shift
, PA_SU_POINT_SIZE__WIDTH_mask
);
907 static void r700PointParameter(struct gl_context
* ctx
, GLenum pname
, const GLfloat
* param
) //---------------
909 context_t
*context
= R700_CONTEXT(ctx
);
910 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
912 R600_STATECHANGE(context
, su
);
914 /* format is 12.4 fixed point */
916 case GL_POINT_SIZE_MIN
:
917 SETfield(r700
->PA_SU_POINT_MINMAX
.u32All
, (int)(ctx
->Point
.MinSize
* 8.0),
918 MIN_SIZE_shift
, MIN_SIZE_mask
);
919 r700PointSize(ctx
, ctx
->Point
.Size
);
921 case GL_POINT_SIZE_MAX
:
922 SETfield(r700
->PA_SU_POINT_MINMAX
.u32All
, (int)(ctx
->Point
.MaxSize
* 8.0),
923 MAX_SIZE_shift
, MAX_SIZE_mask
);
924 r700PointSize(ctx
, ctx
->Point
.Size
);
926 case GL_POINT_DISTANCE_ATTENUATION
:
928 case GL_POINT_FADE_THRESHOLD_SIZE
:
935 static int translate_stencil_func(int func
)
958 static int translate_stencil_op(int op
)
966 return STENCIL_REPLACE
;
968 return STENCIL_INCR_CLAMP
;
970 return STENCIL_DECR_CLAMP
;
971 case GL_INCR_WRAP_EXT
:
972 return STENCIL_INCR_WRAP
;
973 case GL_DECR_WRAP_EXT
:
974 return STENCIL_DECR_WRAP
;
976 return STENCIL_INVERT
;
978 WARN_ONCE("Do not know how to translate stencil op");
984 static void r700SetStencilState(struct gl_context
* ctx
, GLboolean state
)
986 context_t
*context
= R700_CONTEXT(ctx
);
987 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
988 GLboolean hw_stencil
= GL_FALSE
;
990 if (ctx
->DrawBuffer
) {
991 struct radeon_renderbuffer
*rrbStencil
992 = radeon_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_STENCIL
);
993 hw_stencil
= (rrbStencil
&& rrbStencil
->bo
);
997 R600_STATECHANGE(context
, db
);
999 SETbit(r700
->DB_DEPTH_CONTROL
.u32All
, STENCIL_ENABLE_bit
);
1000 SETbit(r700
->DB_DEPTH_CONTROL
.u32All
, BACKFACE_ENABLE_bit
);
1002 CLEARbit(r700
->DB_DEPTH_CONTROL
.u32All
, STENCIL_ENABLE_bit
);
1006 static void r700StencilFuncSeparate(struct gl_context
* ctx
, GLenum face
,
1007 GLenum func
, GLint ref
, GLuint mask
) //---------------------
1009 context_t
*context
= R700_CONTEXT(ctx
);
1010 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1011 const unsigned back
= ctx
->Stencil
._BackFace
;
1013 R600_STATECHANGE(context
, stencil
);
1014 R600_STATECHANGE(context
, db
);
1017 SETfield(r700
->DB_STENCILREFMASK
.u32All
, ctx
->Stencil
.Ref
[0],
1018 STENCILREF_shift
, STENCILREF_mask
);
1019 SETfield(r700
->DB_STENCILREFMASK
.u32All
, ctx
->Stencil
.ValueMask
[0],
1020 STENCILMASK_shift
, STENCILMASK_mask
);
1022 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_func(ctx
->Stencil
.Function
[0]),
1023 STENCILFUNC_shift
, STENCILFUNC_mask
);
1026 SETfield(r700
->DB_STENCILREFMASK_BF
.u32All
, ctx
->Stencil
.Ref
[back
],
1027 STENCILREF_BF_shift
, STENCILREF_BF_mask
);
1028 SETfield(r700
->DB_STENCILREFMASK_BF
.u32All
, ctx
->Stencil
.ValueMask
[back
],
1029 STENCILMASK_BF_shift
, STENCILMASK_BF_mask
);
1031 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_func(ctx
->Stencil
.Function
[back
]),
1032 STENCILFUNC_BF_shift
, STENCILFUNC_BF_mask
);
1036 static void r700StencilMaskSeparate(struct gl_context
* ctx
, GLenum face
, GLuint mask
) //--------------
1038 context_t
*context
= R700_CONTEXT(ctx
);
1039 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1040 const unsigned back
= ctx
->Stencil
._BackFace
;
1042 R600_STATECHANGE(context
, stencil
);
1045 SETfield(r700
->DB_STENCILREFMASK
.u32All
, ctx
->Stencil
.WriteMask
[0],
1046 STENCILWRITEMASK_shift
, STENCILWRITEMASK_mask
);
1049 SETfield(r700
->DB_STENCILREFMASK_BF
.u32All
, ctx
->Stencil
.WriteMask
[back
],
1050 STENCILWRITEMASK_BF_shift
, STENCILWRITEMASK_BF_mask
);
1054 static void r700StencilOpSeparate(struct gl_context
* ctx
, GLenum face
,
1055 GLenum fail
, GLenum zfail
, GLenum zpass
) //--------------------
1057 context_t
*context
= R700_CONTEXT(ctx
);
1058 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1059 const unsigned back
= ctx
->Stencil
._BackFace
;
1061 R600_STATECHANGE(context
, db
);
1063 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.FailFunc
[0]),
1064 STENCILFAIL_shift
, STENCILFAIL_mask
);
1065 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.ZFailFunc
[0]),
1066 STENCILZFAIL_shift
, STENCILZFAIL_mask
);
1067 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.ZPassFunc
[0]),
1068 STENCILZPASS_shift
, STENCILZPASS_mask
);
1070 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.FailFunc
[back
]),
1071 STENCILFAIL_BF_shift
, STENCILFAIL_BF_mask
);
1072 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.ZFailFunc
[back
]),
1073 STENCILZFAIL_BF_shift
, STENCILZFAIL_BF_mask
);
1074 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.ZPassFunc
[back
]),
1075 STENCILZPASS_BF_shift
, STENCILZPASS_BF_mask
);
1078 static void r700UpdateWindow(struct gl_context
* ctx
, int id
) //--------------------
1080 context_t
*context
= R700_CONTEXT(ctx
);
1081 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1082 __DRIdrawable
*dPriv
= radeon_get_drawable(&context
->radeon
);
1083 GLfloat xoffset
= dPriv
? (GLfloat
) dPriv
->x
: 0;
1084 GLfloat yoffset
= dPriv
? (GLfloat
) dPriv
->y
+ dPriv
->h
: 0;
1085 const GLfloat
*v
= ctx
->Viewport
._WindowMap
.m
;
1086 const GLfloat depthScale
= 1.0F
/ ctx
->DrawBuffer
->_DepthMaxF
;
1087 const GLboolean render_to_fbo
= (ctx
->DrawBuffer
->Name
!= 0);
1088 GLfloat y_scale
, y_bias
;
1090 if (render_to_fbo
) {
1098 GLfloat sx
= v
[MAT_SX
];
1099 GLfloat tx
= v
[MAT_TX
] + xoffset
;
1100 GLfloat sy
= v
[MAT_SY
] * y_scale
;
1101 GLfloat ty
= (v
[MAT_TY
] * y_scale
) + y_bias
;
1102 GLfloat sz
= v
[MAT_SZ
] * depthScale
;
1103 GLfloat tz
= v
[MAT_TZ
] * depthScale
;
1105 R600_STATECHANGE(context
, vpt
);
1106 R600_STATECHANGE(context
, cl
);
1108 r700
->viewport
[id
].PA_CL_VPORT_XSCALE
.f32All
= sx
;
1109 r700
->viewport
[id
].PA_CL_VPORT_XOFFSET
.f32All
= tx
;
1111 r700
->viewport
[id
].PA_CL_VPORT_YSCALE
.f32All
= sy
;
1112 r700
->viewport
[id
].PA_CL_VPORT_YOFFSET
.f32All
= ty
;
1114 r700
->viewport
[id
].PA_CL_VPORT_ZSCALE
.f32All
= sz
;
1115 r700
->viewport
[id
].PA_CL_VPORT_ZOFFSET
.f32All
= tz
;
1117 if (ctx
->Transform
.DepthClamp
) {
1118 r700
->viewport
[id
].PA_SC_VPORT_ZMIN_0
.f32All
= MIN2(ctx
->Viewport
.Near
, ctx
->Viewport
.Far
);
1119 r700
->viewport
[id
].PA_SC_VPORT_ZMAX_0
.f32All
= MAX2(ctx
->Viewport
.Near
, ctx
->Viewport
.Far
);
1120 SETbit(r700
->PA_CL_CLIP_CNTL
.u32All
, ZCLIP_NEAR_DISABLE_bit
);
1121 SETbit(r700
->PA_CL_CLIP_CNTL
.u32All
, ZCLIP_FAR_DISABLE_bit
);
1123 r700
->viewport
[id
].PA_SC_VPORT_ZMIN_0
.f32All
= 0.0;
1124 r700
->viewport
[id
].PA_SC_VPORT_ZMAX_0
.f32All
= 1.0;
1125 CLEARbit(r700
->PA_CL_CLIP_CNTL
.u32All
, ZCLIP_NEAR_DISABLE_bit
);
1126 CLEARbit(r700
->PA_CL_CLIP_CNTL
.u32All
, ZCLIP_FAR_DISABLE_bit
);
1129 r700
->viewport
[id
].enabled
= GL_TRUE
;
1131 r700SetScissor(context
);
1135 static void r700Viewport(struct gl_context
* ctx
,
1139 GLsizei height
) //--------------------
1141 r700UpdateWindow(ctx
, 0);
1143 radeon_viewport(ctx
, x
, y
, width
, height
);
1146 static void r700DepthRange(struct gl_context
* ctx
, GLclampd nearval
, GLclampd farval
) //-------------
1148 r700UpdateWindow(ctx
, 0);
1151 static void r700LineWidth(struct gl_context
* ctx
, GLfloat widthf
) //---------------
1153 context_t
*context
= R700_CONTEXT(ctx
);
1154 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1155 uint32_t lineWidth
= (uint32_t)((widthf
* 0.5) * (1 << 4));
1157 R600_STATECHANGE(context
, su
);
1159 if (lineWidth
> 0xFFFF)
1161 SETfield(r700
->PA_SU_LINE_CNTL
.u32All
,(uint16_t)lineWidth
,
1162 PA_SU_LINE_CNTL__WIDTH_shift
, PA_SU_LINE_CNTL__WIDTH_mask
);
1165 static void r700LineStipple(struct gl_context
*ctx
, GLint factor
, GLushort pattern
)
1167 context_t
*context
= R700_CONTEXT(ctx
);
1168 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1170 R600_STATECHANGE(context
, sc
);
1172 SETfield(r700
->PA_SC_LINE_STIPPLE
.u32All
, pattern
, LINE_PATTERN_shift
, LINE_PATTERN_mask
);
1173 SETfield(r700
->PA_SC_LINE_STIPPLE
.u32All
, (factor
-1), REPEAT_COUNT_shift
, REPEAT_COUNT_mask
);
1174 SETfield(r700
->PA_SC_LINE_STIPPLE
.u32All
, 1, AUTO_RESET_CNTL_shift
, AUTO_RESET_CNTL_mask
);
1177 static void r700SetPolygonOffsetState(struct gl_context
* ctx
, GLboolean state
)
1179 context_t
*context
= R700_CONTEXT(ctx
);
1180 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1182 R600_STATECHANGE(context
, su
);
1185 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_FRONT_ENABLE_bit
);
1186 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_BACK_ENABLE_bit
);
1187 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_PARA_ENABLE_bit
);
1189 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_FRONT_ENABLE_bit
);
1190 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_BACK_ENABLE_bit
);
1191 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_PARA_ENABLE_bit
);
1195 static void r700PolygonOffset(struct gl_context
* ctx
, GLfloat factor
, GLfloat units
) //--------------
1197 context_t
*context
= R700_CONTEXT(ctx
);
1198 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1199 GLfloat constant
= units
;
1202 R600_STATECHANGE(context
, poly
);
1204 switch (ctx
->Visual
.depthBits
) {
1216 SETfield(r700
->PA_SU_POLY_OFFSET_DB_FMT_CNTL
.u32All
, depth
,
1217 POLY_OFFSET_NEG_NUM_DB_BITS_shift
, POLY_OFFSET_NEG_NUM_DB_BITS_mask
);
1218 //r700->PA_SU_POLY_OFFSET_CLAMP.f32All = constant; //???
1219 r700
->PA_SU_POLY_OFFSET_FRONT_SCALE
.f32All
= factor
;
1220 r700
->PA_SU_POLY_OFFSET_FRONT_OFFSET
.f32All
= constant
;
1221 r700
->PA_SU_POLY_OFFSET_BACK_SCALE
.f32All
= factor
;
1222 r700
->PA_SU_POLY_OFFSET_BACK_OFFSET
.f32All
= constant
;
1225 static void r700UpdatePolygonMode(struct gl_context
* ctx
)
1227 context_t
*context
= R700_CONTEXT(ctx
);
1228 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1230 R600_STATECHANGE(context
, su
);
1232 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DISABLE_POLY_MODE
, POLY_MODE_shift
, POLY_MODE_mask
);
1234 /* Only do something if a polygon mode is wanted, default is GL_FILL */
1235 if (ctx
->Polygon
.FrontMode
!= GL_FILL
||
1236 ctx
->Polygon
.BackMode
!= GL_FILL
) {
1239 /* Handle GL_CW (clock wise and GL_CCW (counter clock wise)
1240 * correctly by selecting the correct front and back face
1242 f
= ctx
->Polygon
.FrontMode
;
1243 b
= ctx
->Polygon
.BackMode
;
1245 /* Enable polygon mode */
1246 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DUAL_MODE
, POLY_MODE_shift
, POLY_MODE_mask
);
1250 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_LINES
,
1251 POLYMODE_FRONT_PTYPE_shift
, POLYMODE_FRONT_PTYPE_mask
);
1254 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_POINTS
,
1255 POLYMODE_FRONT_PTYPE_shift
, POLYMODE_FRONT_PTYPE_mask
);
1258 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_TRIANGLES
,
1259 POLYMODE_FRONT_PTYPE_shift
, POLYMODE_FRONT_PTYPE_mask
);
1265 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_LINES
,
1266 POLYMODE_BACK_PTYPE_shift
, POLYMODE_BACK_PTYPE_mask
);
1269 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_POINTS
,
1270 POLYMODE_BACK_PTYPE_shift
, POLYMODE_BACK_PTYPE_mask
);
1273 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_TRIANGLES
,
1274 POLYMODE_BACK_PTYPE_shift
, POLYMODE_BACK_PTYPE_mask
);
1280 static void r700PolygonMode(struct gl_context
* ctx
, GLenum face
, GLenum mode
) //------------------
1285 r700UpdatePolygonMode(ctx
);
1288 static void r700RenderMode(struct gl_context
* ctx
, GLenum mode
) //---------------------
1292 static void r700ClipPlane( struct gl_context
*ctx
, GLenum plane
, const GLfloat
*eq
)
1294 context_t
*context
= R700_CONTEXT(ctx
);
1295 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1299 p
= (GLint
) plane
- (GLint
) GL_CLIP_PLANE0
;
1300 ip
= (GLint
*)ctx
->Transform
._ClipUserPlane
[p
];
1302 R600_STATECHANGE(context
, ucp
);
1304 r700
->ucp
[p
].PA_CL_UCP_0_X
.u32All
= ip
[0];
1305 r700
->ucp
[p
].PA_CL_UCP_0_Y
.u32All
= ip
[1];
1306 r700
->ucp
[p
].PA_CL_UCP_0_Z
.u32All
= ip
[2];
1307 r700
->ucp
[p
].PA_CL_UCP_0_W
.u32All
= ip
[3];
1310 static void r700SetClipPlaneState(struct gl_context
* ctx
, GLenum cap
, GLboolean state
)
1312 context_t
*context
= R700_CONTEXT(ctx
);
1313 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1316 p
= cap
- GL_CLIP_PLANE0
;
1318 R600_STATECHANGE(context
, cl
);
1321 r700
->PA_CL_CLIP_CNTL
.u32All
|= (UCP_ENA_0_bit
<< p
);
1322 r700
->ucp
[p
].enabled
= GL_TRUE
;
1323 r700ClipPlane(ctx
, cap
, NULL
);
1325 r700
->PA_CL_CLIP_CNTL
.u32All
&= ~(UCP_ENA_0_bit
<< p
);
1326 r700
->ucp
[p
].enabled
= GL_FALSE
;
1330 void r700SetScissor(context_t
*context
) //---------------
1332 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1333 unsigned x1
, y1
, x2
, y2
;
1335 struct radeon_renderbuffer
*rrb
;
1337 rrb
= radeon_get_colorbuffer(&context
->radeon
);
1338 if (!rrb
|| !rrb
->bo
) {
1341 if (context
->radeon
.state
.scissor
.enabled
) {
1342 x1
= context
->radeon
.state
.scissor
.rect
.x1
;
1343 y1
= context
->radeon
.state
.scissor
.rect
.y1
;
1344 x2
= context
->radeon
.state
.scissor
.rect
.x2
;
1345 y2
= context
->radeon
.state
.scissor
.rect
.y2
;
1346 /* r600 has exclusive BR scissors */
1347 if (context
->radeon
.radeonScreen
->kernel_mm
) {
1352 if (context
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
1355 x2
= rrb
->base
.Width
;
1356 y2
= rrb
->base
.Height
;
1360 x2
= rrb
->dPriv
->x
+ rrb
->dPriv
->w
;
1361 y2
= rrb
->dPriv
->y
+ rrb
->dPriv
->h
;
1365 R600_STATECHANGE(context
, scissor
);
1368 SETbit(r700
->PA_SC_SCREEN_SCISSOR_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
1369 SETfield(r700
->PA_SC_SCREEN_SCISSOR_TL
.u32All
, x1
,
1370 PA_SC_SCREEN_SCISSOR_TL__TL_X_shift
, PA_SC_SCREEN_SCISSOR_TL__TL_X_mask
);
1371 SETfield(r700
->PA_SC_SCREEN_SCISSOR_TL
.u32All
, y1
,
1372 PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift
, PA_SC_SCREEN_SCISSOR_TL__TL_Y_mask
);
1374 SETfield(r700
->PA_SC_SCREEN_SCISSOR_BR
.u32All
, x2
,
1375 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift
, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask
);
1376 SETfield(r700
->PA_SC_SCREEN_SCISSOR_BR
.u32All
, y2
,
1377 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift
, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask
);
1380 SETbit(r700
->PA_SC_WINDOW_SCISSOR_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
1381 SETfield(r700
->PA_SC_WINDOW_SCISSOR_TL
.u32All
, x1
,
1382 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift
, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask
);
1383 SETfield(r700
->PA_SC_WINDOW_SCISSOR_TL
.u32All
, y1
,
1384 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift
, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask
);
1386 SETfield(r700
->PA_SC_WINDOW_SCISSOR_BR
.u32All
, x2
,
1387 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift
, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask
);
1388 SETfield(r700
->PA_SC_WINDOW_SCISSOR_BR
.u32All
, y2
,
1389 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift
, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask
);
1392 SETfield(r700
->PA_SC_CLIPRECT_0_TL
.u32All
, x1
,
1393 PA_SC_CLIPRECT_0_TL__TL_X_shift
, PA_SC_CLIPRECT_0_TL__TL_X_mask
);
1394 SETfield(r700
->PA_SC_CLIPRECT_0_TL
.u32All
, y1
,
1395 PA_SC_CLIPRECT_0_TL__TL_Y_shift
, PA_SC_CLIPRECT_0_TL__TL_Y_mask
);
1396 SETfield(r700
->PA_SC_CLIPRECT_0_BR
.u32All
, x2
,
1397 PA_SC_CLIPRECT_0_BR__BR_X_shift
, PA_SC_CLIPRECT_0_BR__BR_X_mask
);
1398 SETfield(r700
->PA_SC_CLIPRECT_0_BR
.u32All
, y2
,
1399 PA_SC_CLIPRECT_0_BR__BR_Y_shift
, PA_SC_CLIPRECT_0_BR__BR_Y_mask
);
1401 r700
->PA_SC_CLIPRECT_1_TL
.u32All
= r700
->PA_SC_CLIPRECT_0_TL
.u32All
;
1402 r700
->PA_SC_CLIPRECT_1_BR
.u32All
= r700
->PA_SC_CLIPRECT_0_BR
.u32All
;
1403 r700
->PA_SC_CLIPRECT_2_TL
.u32All
= r700
->PA_SC_CLIPRECT_0_TL
.u32All
;
1404 r700
->PA_SC_CLIPRECT_2_BR
.u32All
= r700
->PA_SC_CLIPRECT_0_BR
.u32All
;
1405 r700
->PA_SC_CLIPRECT_3_TL
.u32All
= r700
->PA_SC_CLIPRECT_0_TL
.u32All
;
1406 r700
->PA_SC_CLIPRECT_3_BR
.u32All
= r700
->PA_SC_CLIPRECT_0_BR
.u32All
;
1408 /* more....2d clip */
1409 SETbit(r700
->PA_SC_GENERIC_SCISSOR_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
1410 SETfield(r700
->PA_SC_GENERIC_SCISSOR_TL
.u32All
, x1
,
1411 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift
, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask
);
1412 SETfield(r700
->PA_SC_GENERIC_SCISSOR_TL
.u32All
, y1
,
1413 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift
, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask
);
1414 SETfield(r700
->PA_SC_GENERIC_SCISSOR_BR
.u32All
, x2
,
1415 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift
, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask
);
1416 SETfield(r700
->PA_SC_GENERIC_SCISSOR_BR
.u32All
, y2
,
1417 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift
, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask
);
1419 SETbit(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
1420 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_TL
.u32All
, x1
,
1421 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift
, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask
);
1422 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_TL
.u32All
, y1
,
1423 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift
, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask
);
1424 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_BR
.u32All
, x2
,
1425 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift
, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask
);
1426 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_BR
.u32All
, y2
,
1427 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift
, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask
);
1429 r700
->viewport
[id
].enabled
= GL_TRUE
;
1432 static void r700InitSQConfig(struct gl_context
* ctx
)
1434 context_t
*context
= R700_CONTEXT(ctx
);
1435 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1449 int num_ps_stack_entries
;
1450 int num_vs_stack_entries
;
1451 int num_gs_stack_entries
;
1452 int num_es_stack_entries
;
1454 R600_STATECHANGE(context
, sq
);
1461 switch (context
->radeon
.radeonScreen
->chip_family
) {
1462 case CHIP_FAMILY_R600
:
1468 num_ps_threads
= 136;
1469 num_vs_threads
= 48;
1472 num_ps_stack_entries
= 128;
1473 num_vs_stack_entries
= 128;
1474 num_gs_stack_entries
= 0;
1475 num_es_stack_entries
= 0;
1477 case CHIP_FAMILY_RV630
:
1478 case CHIP_FAMILY_RV635
:
1484 num_ps_threads
= 144;
1485 num_vs_threads
= 40;
1488 num_ps_stack_entries
= 40;
1489 num_vs_stack_entries
= 40;
1490 num_gs_stack_entries
= 32;
1491 num_es_stack_entries
= 16;
1493 case CHIP_FAMILY_RV610
:
1494 case CHIP_FAMILY_RV620
:
1495 case CHIP_FAMILY_RS780
:
1496 case CHIP_FAMILY_RS880
:
1503 num_ps_threads
= 136;
1504 num_vs_threads
= 48;
1507 num_ps_stack_entries
= 40;
1508 num_vs_stack_entries
= 40;
1509 num_gs_stack_entries
= 32;
1510 num_es_stack_entries
= 16;
1512 case CHIP_FAMILY_RV670
:
1518 num_ps_threads
= 136;
1519 num_vs_threads
= 48;
1522 num_ps_stack_entries
= 40;
1523 num_vs_stack_entries
= 40;
1524 num_gs_stack_entries
= 32;
1525 num_es_stack_entries
= 16;
1527 case CHIP_FAMILY_RV770
:
1533 num_ps_threads
= 188;
1534 num_vs_threads
= 60;
1537 num_ps_stack_entries
= 256;
1538 num_vs_stack_entries
= 256;
1539 num_gs_stack_entries
= 0;
1540 num_es_stack_entries
= 0;
1542 case CHIP_FAMILY_RV730
:
1543 case CHIP_FAMILY_RV740
:
1549 num_ps_threads
= 188;
1550 num_vs_threads
= 60;
1553 num_ps_stack_entries
= 128;
1554 num_vs_stack_entries
= 128;
1555 num_gs_stack_entries
= 0;
1556 num_es_stack_entries
= 0;
1558 case CHIP_FAMILY_RV710
:
1564 num_ps_threads
= 144;
1565 num_vs_threads
= 48;
1568 num_ps_stack_entries
= 128;
1569 num_vs_stack_entries
= 128;
1570 num_gs_stack_entries
= 0;
1571 num_es_stack_entries
= 0;
1575 r700
->sq_config
.SQ_CONFIG
.u32All
= 0;
1576 if ((context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV610
) ||
1577 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV620
) ||
1578 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RS780
) ||
1579 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RS880
) ||
1580 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV710
))
1581 CLEARbit(r700
->sq_config
.SQ_CONFIG
.u32All
, VC_ENABLE_bit
);
1583 SETbit(r700
->sq_config
.SQ_CONFIG
.u32All
, VC_ENABLE_bit
);
1585 if(GL_TRUE
== r700
->bShaderUseMemConstant
)
1587 CLEARbit(r700
->sq_config
.SQ_CONFIG
.u32All
, DX9_CONSTS_bit
);
1591 SETbit(r700
->sq_config
.SQ_CONFIG
.u32All
, DX9_CONSTS_bit
);
1594 SETbit(r700
->sq_config
.SQ_CONFIG
.u32All
, ALU_INST_PREFER_VECTOR_bit
);
1595 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, ps_prio
, PS_PRIO_shift
, PS_PRIO_mask
);
1596 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, vs_prio
, VS_PRIO_shift
, VS_PRIO_mask
);
1597 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, gs_prio
, GS_PRIO_shift
, GS_PRIO_mask
);
1598 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, es_prio
, ES_PRIO_shift
, ES_PRIO_mask
);
1600 r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
= 0;
1601 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
, num_ps_gprs
, NUM_PS_GPRS_shift
, NUM_PS_GPRS_mask
);
1602 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
, num_vs_gprs
, NUM_VS_GPRS_shift
, NUM_VS_GPRS_mask
);
1603 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
, num_temp_gprs
,
1604 NUM_CLAUSE_TEMP_GPRS_shift
, NUM_CLAUSE_TEMP_GPRS_mask
);
1606 r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_2
.u32All
= 0;
1607 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_2
.u32All
, num_gs_gprs
, NUM_GS_GPRS_shift
, NUM_GS_GPRS_mask
);
1608 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_2
.u32All
, num_es_gprs
, NUM_ES_GPRS_shift
, NUM_ES_GPRS_mask
);
1610 r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
= 0;
1611 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_ps_threads
,
1612 NUM_PS_THREADS_shift
, NUM_PS_THREADS_mask
);
1613 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_vs_threads
,
1614 NUM_VS_THREADS_shift
, NUM_VS_THREADS_mask
);
1615 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_gs_threads
,
1616 NUM_GS_THREADS_shift
, NUM_GS_THREADS_mask
);
1617 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_es_threads
,
1618 NUM_ES_THREADS_shift
, NUM_ES_THREADS_mask
);
1620 r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_1
.u32All
= 0;
1621 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_1
.u32All
, num_ps_stack_entries
,
1622 NUM_PS_STACK_ENTRIES_shift
, NUM_PS_STACK_ENTRIES_mask
);
1623 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_1
.u32All
, num_vs_stack_entries
,
1624 NUM_VS_STACK_ENTRIES_shift
, NUM_VS_STACK_ENTRIES_mask
);
1626 r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_2
.u32All
= 0;
1627 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_2
.u32All
, num_gs_stack_entries
,
1628 NUM_GS_STACK_ENTRIES_shift
, NUM_GS_STACK_ENTRIES_mask
);
1629 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_2
.u32All
, num_es_stack_entries
,
1630 NUM_ES_STACK_ENTRIES_shift
, NUM_ES_STACK_ENTRIES_mask
);
1635 * Calculate initial hardware state and register state functions.
1636 * Assumes that the command buffer and state atoms have been
1637 * initialized already.
1639 void r700InitState(struct gl_context
* ctx
) //-------------------
1641 context_t
*context
= R700_CONTEXT(ctx
);
1642 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1645 r700
->TA_CNTL_AUX
.u32All
= 0;
1646 SETfield(r700
->TA_CNTL_AUX
.u32All
, 28, TD_FIFO_CREDIT_shift
, TD_FIFO_CREDIT_mask
);
1647 r700
->VC_ENHANCE
.u32All
= 0;
1648 r700
->DB_WATERMARKS
.u32All
= 0;
1649 SETfield(r700
->DB_WATERMARKS
.u32All
, 4, DEPTH_FREE_shift
, DEPTH_FREE_mask
);
1650 SETfield(r700
->DB_WATERMARKS
.u32All
, 16, DEPTH_FLUSH_shift
, DEPTH_FLUSH_mask
);
1651 SETfield(r700
->DB_WATERMARKS
.u32All
, 0, FORCE_SUMMARIZE_shift
, FORCE_SUMMARIZE_mask
);
1652 SETfield(r700
->DB_WATERMARKS
.u32All
, 4, DEPTH_PENDING_FREE_shift
, DEPTH_PENDING_FREE_mask
);
1653 r700
->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
.u32All
= 0;
1654 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
) {
1655 SETfield(r700
->TA_CNTL_AUX
.u32All
, 3, GRADIENT_CREDIT_shift
, GRADIENT_CREDIT_mask
);
1656 r700
->DB_DEBUG
.u32All
= 0x82000000;
1657 SETfield(r700
->DB_WATERMARKS
.u32All
, 16, DEPTH_CACHELINE_FREE_shift
, DEPTH_CACHELINE_FREE_mask
);
1659 SETfield(r700
->TA_CNTL_AUX
.u32All
, 2, GRADIENT_CREDIT_shift
, GRADIENT_CREDIT_mask
);
1660 SETfield(r700
->DB_WATERMARKS
.u32All
, 4, DEPTH_CACHELINE_FREE_shift
, DEPTH_CACHELINE_FREE_mask
);
1661 SETbit(r700
->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
.u32All
, VS_PC_LIMIT_ENABLE_bit
);
1664 /* Turn off vgt reuse */
1665 r700
->VGT_REUSE_OFF
.u32All
= 0;
1666 SETbit(r700
->VGT_REUSE_OFF
.u32All
, REUSE_OFF_bit
);
1668 /* Specify offsetting and clamp values for vertices */
1669 r700
->VGT_MAX_VTX_INDX
.u32All
= 0xFFFFFF;
1670 r700
->VGT_MIN_VTX_INDX
.u32All
= 0;
1671 r700
->VGT_INDX_OFFSET
.u32All
= 0;
1673 /* default shader connections. */
1674 r700
->SPI_VS_OUT_ID_0
.u32All
= 0x03020100;
1675 r700
->SPI_VS_OUT_ID_1
.u32All
= 0x07060504;
1676 r700
->SPI_VS_OUT_ID_2
.u32All
= 0x0b0a0908;
1677 r700
->SPI_VS_OUT_ID_3
.u32All
= 0x0f0e0d0c;
1679 r700
->SPI_THREAD_GROUPING
.u32All
= 0;
1680 if (context
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV770
)
1681 SETfield(r700
->SPI_THREAD_GROUPING
.u32All
, 1, PS_GROUPING_shift
, PS_GROUPING_mask
);
1683 /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
1684 r700
->PA_SC_CLIPRECT_RULE
.u32All
= 0;
1685 SETfield(r700
->PA_SC_CLIPRECT_RULE
.u32All
, CLIP_RULE_mask
, CLIP_RULE_shift
, CLIP_RULE_mask
);
1687 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
)
1688 r700
->PA_SC_EDGERULE
.u32All
= 0;
1690 r700
->PA_SC_EDGERULE
.u32All
= 0xAAAAAAAA;
1692 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
) {
1693 r700
->PA_SC_MODE_CNTL
.u32All
= 0;
1694 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, WALK_ORDER_ENABLE_bit
);
1695 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, FORCE_EOV_CNTDWN_ENABLE_bit
);
1697 r700
->PA_SC_MODE_CNTL
.u32All
= 0x00500000;
1698 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, FORCE_EOV_REZ_ENABLE_bit
);
1699 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, FORCE_EOV_CNTDWN_ENABLE_bit
);
1702 /* Do scale XY and Z by 1/W0. */
1703 r700
->bEnablePerspective
= GL_TRUE
;
1705 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_XY_FMT_bit
);
1706 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_Z_FMT_bit
);
1707 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_W0_FMT_bit
);
1709 /* Enable viewport scaling for all three axis */
1710 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_X_SCALE_ENA_bit
);
1711 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_X_OFFSET_ENA_bit
);
1712 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Y_SCALE_ENA_bit
);
1713 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Y_OFFSET_ENA_bit
);
1714 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Z_SCALE_ENA_bit
);
1715 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Z_OFFSET_ENA_bit
);
1717 /* GL uses last vtx for flat shading components */
1718 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, PROVOKING_VTX_LAST_bit
);
1720 /* Set up vertex control */
1721 r700
->PA_SU_VTX_CNTL
.u32All
= 0;
1722 CLEARfield(r700
->PA_SU_VTX_CNTL
.u32All
, QUANT_MODE_mask
);
1723 SETbit(r700
->PA_SU_VTX_CNTL
.u32All
, PIX_CENTER_bit
);
1724 SETfield(r700
->PA_SU_VTX_CNTL
.u32All
, X_ROUND_TO_EVEN
,
1725 PA_SU_VTX_CNTL__ROUND_MODE_shift
, PA_SU_VTX_CNTL__ROUND_MODE_mask
);
1727 /* to 1.0 = no guard band */
1728 r700
->PA_CL_GB_VERT_CLIP_ADJ
.u32All
= 0x3F800000; /* 1.0 */
1729 r700
->PA_CL_GB_VERT_DISC_ADJ
.u32All
= 0x3F800000;
1730 r700
->PA_CL_GB_HORZ_CLIP_ADJ
.u32All
= 0x3F800000;
1731 r700
->PA_CL_GB_HORZ_DISC_ADJ
.u32All
= 0x3F800000;
1733 /* Enable all samples for multi-sample anti-aliasing */
1734 r700
->PA_SC_AA_MASK
.u32All
= 0xFFFFFFFF;
1736 r700
->PA_SC_AA_CONFIG
.u32All
= 0;
1738 r700
->SX_MISC
.u32All
= 0;
1740 r700InitSQConfig(ctx
);
1743 ctx
->Color
.ColorMask
[0][RCOMP
],
1744 ctx
->Color
.ColorMask
[0][GCOMP
],
1745 ctx
->Color
.ColorMask
[0][BCOMP
],
1746 ctx
->Color
.ColorMask
[0][ACOMP
]);
1748 r700Enable(ctx
, GL_DEPTH_TEST
, ctx
->Depth
.Test
);
1749 r700DepthMask(ctx
, ctx
->Depth
.Mask
);
1750 r700DepthFunc(ctx
, ctx
->Depth
.Func
);
1751 r700
->DB_DEPTH_CLEAR
.u32All
= 0x3F800000;
1752 SETbit(r700
->DB_RENDER_CONTROL
.u32All
, STENCIL_COMPRESS_DISABLE_bit
);
1753 SETbit(r700
->DB_RENDER_CONTROL
.u32All
, DEPTH_COMPRESS_DISABLE_bit
);
1754 r700SetDBRenderState(ctx
);
1756 r700
->DB_ALPHA_TO_MASK
.u32All
= 0;
1757 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET0_shift
, ALPHA_TO_MASK_OFFSET0_mask
);
1758 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET1_shift
, ALPHA_TO_MASK_OFFSET1_mask
);
1759 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET2_shift
, ALPHA_TO_MASK_OFFSET2_mask
);
1760 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET3_shift
, ALPHA_TO_MASK_OFFSET3_mask
);
1763 r700Enable(ctx
, GL_STENCIL_TEST
, ctx
->Stencil
._Enabled
);
1764 r700StencilMaskSeparate(ctx
, 0, ctx
->Stencil
.WriteMask
[0]);
1765 r700StencilFuncSeparate(ctx
, 0, ctx
->Stencil
.Function
[0],
1766 ctx
->Stencil
.Ref
[0], ctx
->Stencil
.ValueMask
[0]);
1767 r700StencilOpSeparate(ctx
, 0, ctx
->Stencil
.FailFunc
[0],
1768 ctx
->Stencil
.ZFailFunc
[0],
1769 ctx
->Stencil
.ZPassFunc
[0]);
1771 r700UpdateCulling(ctx
);
1773 r700SetBlendState(ctx
);
1774 r700SetLogicOpState(ctx
);
1776 r700AlphaFunc(ctx
, ctx
->Color
.AlphaFunc
, ctx
->Color
.AlphaRef
);
1777 r700Enable(ctx
, GL_ALPHA_TEST
, ctx
->Color
.AlphaEnabled
);
1779 r700PointSize(ctx
, 1.0);
1781 CLEARfield(r700
->PA_SU_POINT_MINMAX
.u32All
, MIN_SIZE_mask
);
1782 SETfield(r700
->PA_SU_POINT_MINMAX
.u32All
, 0x8000, MAX_SIZE_shift
, MAX_SIZE_mask
);
1784 r700LineWidth(ctx
, 1.0);
1786 r700
->PA_SC_LINE_CNTL
.u32All
= 0;
1787 CLEARbit(r700
->PA_SC_LINE_CNTL
.u32All
, EXPAND_LINE_WIDTH_bit
);
1788 SETbit(r700
->PA_SC_LINE_CNTL
.u32All
, LAST_PIXEL_bit
);
1790 r700ShadeModel(ctx
, ctx
->Light
.ShadeModel
);
1791 r700PolygonMode(ctx
, GL_FRONT
, ctx
->Polygon
.FrontMode
);
1792 r700PolygonMode(ctx
, GL_BACK
, ctx
->Polygon
.BackMode
);
1793 r700PolygonOffset(ctx
, ctx
->Polygon
.OffsetFactor
,
1794 ctx
->Polygon
.OffsetUnits
);
1795 r700Enable(ctx
, GL_POLYGON_OFFSET_POINT
, ctx
->Polygon
.OffsetPoint
);
1796 r700Enable(ctx
, GL_POLYGON_OFFSET_LINE
, ctx
->Polygon
.OffsetLine
);
1797 r700Enable(ctx
, GL_POLYGON_OFFSET_FILL
, ctx
->Polygon
.OffsetFill
);
1800 r700BlendColor(ctx
, ctx
->Color
.BlendColor
);
1802 r700
->CB_CLEAR_RED_R6XX
.f32All
= 1.0; //r6xx only
1803 r700
->CB_CLEAR_GREEN_R6XX
.f32All
= 0.0; //r6xx only
1804 r700
->CB_CLEAR_BLUE_R6XX
.f32All
= 1.0; //r6xx only
1805 r700
->CB_CLEAR_ALPHA_R6XX
.f32All
= 1.0; //r6xx only
1806 r700
->CB_FOG_RED_R6XX
.u32All
= 0; //r6xx only
1807 r700
->CB_FOG_GREEN_R6XX
.u32All
= 0; //r6xx only
1808 r700
->CB_FOG_BLUE_R6XX
.u32All
= 0; //r6xx only
1810 /* Disable color compares */
1811 SETfield(r700
->CB_CLRCMP_CONTROL
.u32All
, CLRCMP_DRAW_ALWAYS
,
1812 CLRCMP_FCN_SRC_shift
, CLRCMP_FCN_SRC_mask
);
1813 SETfield(r700
->CB_CLRCMP_CONTROL
.u32All
, CLRCMP_DRAW_ALWAYS
,
1814 CLRCMP_FCN_DST_shift
, CLRCMP_FCN_DST_mask
);
1815 SETfield(r700
->CB_CLRCMP_CONTROL
.u32All
, CLRCMP_SEL_SRC
,
1816 CLRCMP_FCN_SEL_shift
, CLRCMP_FCN_SEL_mask
);
1818 /* Zero out source */
1819 r700
->CB_CLRCMP_SRC
.u32All
= 0x00000000;
1821 /* Put a compare color in for error checking */
1822 r700
->CB_CLRCMP_DST
.u32All
= 0x000000FF;
1824 /* Set up color compare mask */
1825 r700
->CB_CLRCMP_MSK
.u32All
= 0xFFFFFFFF;
1827 /* screen/window/view */
1828 SETfield(r700
->CB_SHADER_MASK
.u32All
, 0xF, (4 * id
), OUTPUT0_ENABLE_mask
);
1830 context
->radeon
.hw
.all_dirty
= GL_TRUE
;
1834 void r700InitStateFuncs(radeonContextPtr radeon
, struct dd_function_table
*functions
)
1836 functions
->UpdateState
= r700InvalidateState
;
1837 functions
->AlphaFunc
= r700AlphaFunc
;
1838 functions
->BlendColor
= r700BlendColor
;
1839 functions
->BlendEquationSeparate
= r700BlendEquationSeparate
;
1840 functions
->BlendFuncSeparate
= r700BlendFuncSeparate
;
1841 functions
->Enable
= r700Enable
;
1842 functions
->ColorMask
= r700ColorMask
;
1843 functions
->DepthFunc
= r700DepthFunc
;
1844 functions
->DepthMask
= r700DepthMask
;
1845 functions
->CullFace
= r700CullFace
;
1846 functions
->Fogfv
= r700Fogfv
;
1847 functions
->FrontFace
= r700FrontFace
;
1848 functions
->ShadeModel
= r700ShadeModel
;
1849 functions
->LogicOpcode
= r700LogicOpcode
;
1851 /* ARB_point_parameters */
1852 functions
->PointParameterfv
= r700PointParameter
;
1854 /* Stencil related */
1855 functions
->StencilFuncSeparate
= r700StencilFuncSeparate
;
1856 functions
->StencilMaskSeparate
= r700StencilMaskSeparate
;
1857 functions
->StencilOpSeparate
= r700StencilOpSeparate
;
1859 /* Viewport related */
1860 functions
->Viewport
= r700Viewport
;
1861 functions
->DepthRange
= r700DepthRange
;
1862 functions
->PointSize
= r700PointSize
;
1863 functions
->LineWidth
= r700LineWidth
;
1864 functions
->LineStipple
= r700LineStipple
;
1866 functions
->PolygonOffset
= r700PolygonOffset
;
1867 functions
->PolygonMode
= r700PolygonMode
;
1869 functions
->RenderMode
= r700RenderMode
;
1871 functions
->ClipPlane
= r700ClipPlane
;
1873 functions
->Scissor
= radeonScissor
;
1875 functions
->DrawBuffer
= radeonDrawBuffer
;
1876 functions
->ReadBuffer
= radeonReadBuffer
;
1878 functions
->CopyPixels
= _mesa_meta_CopyPixels
;
1879 functions
->DrawPixels
= _mesa_meta_DrawPixels
;
1880 if (radeon
->radeonScreen
->kernel_mm
)
1881 functions
->ReadPixels
= radeonReadPixels
;