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r600: fix point sizes
[mesa.git] / src / mesa / drivers / dri / r600 / r700_state.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/context.h"
34 #include "main/dd.h"
35 #include "main/simple_list.h"
36
37 #include "tnl/tnl.h"
38 #include "tnl/t_pipeline.h"
39 #include "tnl/t_vp_build.h"
40 #include "swrast/swrast.h"
41 #include "swrast_setup/swrast_setup.h"
42 #include "main/api_arrayelt.h"
43 #include "main/state.h"
44 #include "main/framebuffer.h"
45
46 #include "shader/prog_parameter.h"
47 #include "shader/prog_statevars.h"
48 #include "vbo/vbo.h"
49 #include "main/texformat.h"
50
51 #include "r600_context.h"
52
53 #include "r700_state.h"
54
55 #include "r700_fragprog.h"
56 #include "r700_vertprog.h"
57
58
59 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state);
60 static void r700UpdatePolygonMode(GLcontext * ctx);
61 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state);
62 static void r700SetStencilState(GLcontext * ctx, GLboolean state);
63
64 void r700UpdateShaders (GLcontext * ctx) //----------------------------------
65 {
66 context_t *context = R700_CONTEXT(ctx);
67 GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
68 GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
69 int i;
70
71 /* should only happenen once, just after context is created */
72 /* TODO: shouldn't we fallback to sw here? */
73 if (!ctx->FragmentProgram._Current) {
74 _mesa_fprintf(stderr, "No ctx->FragmentProgram._Current!!\n");
75 return;
76 }
77
78 r700SelectFragmentShader(ctx);
79
80 if (context->radeon.NewGLState) {
81 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++) {
82 /* mat states from state var not array for sw */
83 dummy_attrib[i].stride = 0;
84 temp_attrib[i] = TNL_CONTEXT(ctx)->vb.AttribPtr[i];
85 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = &(dummy_attrib[i]);
86 }
87
88 _tnl_UpdateFixedFunctionProgram(ctx);
89
90 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++) {
91 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = temp_attrib[i];
92 }
93 }
94
95 r700SelectVertexShader(ctx);
96 r700UpdateStateParameters(ctx, _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS);
97 context->radeon.NewGLState = 0;
98 }
99
100 /*
101 * To correctly position primitives:
102 */
103 void r700UpdateViewportOffset(GLcontext * ctx) //------------------
104 {
105 context_t *context = R700_CONTEXT(ctx);
106 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
107 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
108 GLfloat xoffset = (GLfloat) dPriv->x;
109 GLfloat yoffset = (GLfloat) dPriv->y + dPriv->h;
110 const GLfloat *v = ctx->Viewport._WindowMap.m;
111 int id = 0;
112
113 GLfloat tx = v[MAT_TX] + xoffset;
114 GLfloat ty = (-v[MAT_TY]) + yoffset;
115
116 if (r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All != tx ||
117 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All != ty) {
118 /* Note: this should also modify whatever data the context reset
119 * code uses...
120 */
121 R600_STATECHANGE(context, vpt);
122 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
123 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
124 }
125
126 radeonUpdateScissor(ctx);
127 }
128
129 void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state) //--------------------
130 {
131 struct r700_fragment_program *fp =
132 (struct r700_fragment_program *)ctx->FragmentProgram._Current;
133 struct gl_program_parameter_list *paramList;
134
135 if (!(new_state & (_NEW_BUFFERS | _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS)))
136 return;
137
138 if (!ctx->FragmentProgram._Current || !fp)
139 return;
140
141 paramList = ctx->FragmentProgram._Current->Base.Parameters;
142
143 if (!paramList)
144 return;
145
146 _mesa_load_state_parameters(ctx, paramList);
147
148 }
149
150 /**
151 * Called by Mesa after an internal state update.
152 */
153 static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //-------------------
154 {
155 context_t *context = R700_CONTEXT(ctx);
156
157 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
158
159 _swrast_InvalidateState(ctx, new_state);
160 _swsetup_InvalidateState(ctx, new_state);
161 _vbo_InvalidateState(ctx, new_state);
162 _tnl_InvalidateState(ctx, new_state);
163 _ae_invalidate_state(ctx, new_state);
164
165 if (new_state & _NEW_BUFFERS) {
166 _mesa_update_framebuffer(ctx);
167 /* this updates the DrawBuffer's Width/Height if it's a FBO */
168 _mesa_update_draw_buffer_bounds(ctx);
169
170 R600_STATECHANGE(context, cb_target);
171 R600_STATECHANGE(context, db_target);
172 }
173
174 if (new_state & (_NEW_LIGHT)) {
175 R600_STATECHANGE(context, su);
176 if (ctx->Light.ProvokingVertex == GL_LAST_VERTEX_CONVENTION)
177 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
178 else
179 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
180 }
181
182 r700UpdateStateParameters(ctx, new_state);
183
184 R600_STATECHANGE(context, cl);
185 R600_STATECHANGE(context, spi);
186
187 if(GL_TRUE == r700->bEnablePerspective)
188 {
189 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
190 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
191 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
192
193 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
194
195 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
196 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
197 }
198 else
199 {
200 /* For orthogonal case. */
201 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
202 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
203
204 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
205
206 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
207 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
208 }
209
210 context->radeon.NewGLState |= new_state;
211 }
212
213 static void r700SetDepthState(GLcontext * ctx)
214 {
215 context_t *context = R700_CONTEXT(ctx);
216 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
217
218 R600_STATECHANGE(context, db);
219
220 if (ctx->Depth.Test)
221 {
222 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
223 if (ctx->Depth.Mask)
224 {
225 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
226 }
227 else
228 {
229 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
230 }
231
232 switch (ctx->Depth.Func)
233 {
234 case GL_NEVER:
235 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NEVER,
236 ZFUNC_shift, ZFUNC_mask);
237 break;
238 case GL_LESS:
239 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LESS,
240 ZFUNC_shift, ZFUNC_mask);
241 break;
242 case GL_EQUAL:
243 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_EQUAL,
244 ZFUNC_shift, ZFUNC_mask);
245 break;
246 case GL_LEQUAL:
247 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LEQUAL,
248 ZFUNC_shift, ZFUNC_mask);
249 break;
250 case GL_GREATER:
251 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GREATER,
252 ZFUNC_shift, ZFUNC_mask);
253 break;
254 case GL_NOTEQUAL:
255 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NOTEQUAL,
256 ZFUNC_shift, ZFUNC_mask);
257 break;
258 case GL_GEQUAL:
259 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GEQUAL,
260 ZFUNC_shift, ZFUNC_mask);
261 break;
262 case GL_ALWAYS:
263 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
264 ZFUNC_shift, ZFUNC_mask);
265 break;
266 default:
267 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
268 ZFUNC_shift, ZFUNC_mask);
269 break;
270 }
271 }
272 else
273 {
274 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
275 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
276 }
277 }
278
279 static void r700SetAlphaState(GLcontext * ctx)
280 {
281 context_t *context = R700_CONTEXT(ctx);
282 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
283 uint32_t alpha_func = REF_ALWAYS;
284 GLboolean really_enabled = ctx->Color.AlphaEnabled;
285
286 R600_STATECHANGE(context, sx);
287
288 switch (ctx->Color.AlphaFunc) {
289 case GL_NEVER:
290 alpha_func = REF_NEVER;
291 break;
292 case GL_LESS:
293 alpha_func = REF_LESS;
294 break;
295 case GL_EQUAL:
296 alpha_func = REF_EQUAL;
297 break;
298 case GL_LEQUAL:
299 alpha_func = REF_LEQUAL;
300 break;
301 case GL_GREATER:
302 alpha_func = REF_GREATER;
303 break;
304 case GL_NOTEQUAL:
305 alpha_func = REF_NOTEQUAL;
306 break;
307 case GL_GEQUAL:
308 alpha_func = REF_GEQUAL;
309 break;
310 case GL_ALWAYS:
311 /*alpha_func = REF_ALWAYS; */
312 really_enabled = GL_FALSE;
313 break;
314 }
315
316 if (really_enabled) {
317 SETfield(r700->SX_ALPHA_TEST_CONTROL.u32All, alpha_func,
318 ALPHA_FUNC_shift, ALPHA_FUNC_mask);
319 SETbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
320 r700->SX_ALPHA_REF.f32All = ctx->Color.AlphaRef;
321 } else {
322 CLEARbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
323 }
324
325 }
326
327 static void r700AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref) //---------------
328 {
329 (void)func;
330 (void)ref;
331 r700SetAlphaState(ctx);
332 }
333
334
335 static void r700BlendColor(GLcontext * ctx, const GLfloat cf[4]) //----------------
336 {
337 context_t *context = R700_CONTEXT(ctx);
338 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
339
340 R600_STATECHANGE(context, blnd_clr);
341
342 r700->CB_BLEND_RED.f32All = cf[0];
343 r700->CB_BLEND_GREEN.f32All = cf[1];
344 r700->CB_BLEND_BLUE.f32All = cf[2];
345 r700->CB_BLEND_ALPHA.f32All = cf[3];
346 }
347
348 static int blend_factor(GLenum factor, GLboolean is_src)
349 {
350 switch (factor) {
351 case GL_ZERO:
352 return BLEND_ZERO;
353 break;
354 case GL_ONE:
355 return BLEND_ONE;
356 break;
357 case GL_DST_COLOR:
358 return BLEND_DST_COLOR;
359 break;
360 case GL_ONE_MINUS_DST_COLOR:
361 return BLEND_ONE_MINUS_DST_COLOR;
362 break;
363 case GL_SRC_COLOR:
364 return BLEND_SRC_COLOR;
365 break;
366 case GL_ONE_MINUS_SRC_COLOR:
367 return BLEND_ONE_MINUS_SRC_COLOR;
368 break;
369 case GL_SRC_ALPHA:
370 return BLEND_SRC_ALPHA;
371 break;
372 case GL_ONE_MINUS_SRC_ALPHA:
373 return BLEND_ONE_MINUS_SRC_ALPHA;
374 break;
375 case GL_DST_ALPHA:
376 return BLEND_DST_ALPHA;
377 break;
378 case GL_ONE_MINUS_DST_ALPHA:
379 return BLEND_ONE_MINUS_DST_ALPHA;
380 break;
381 case GL_SRC_ALPHA_SATURATE:
382 return (is_src) ? BLEND_SRC_ALPHA_SATURATE : BLEND_ZERO;
383 break;
384 case GL_CONSTANT_COLOR:
385 return BLEND_CONSTANT_COLOR;
386 break;
387 case GL_ONE_MINUS_CONSTANT_COLOR:
388 return BLEND_ONE_MINUS_CONSTANT_COLOR;
389 break;
390 case GL_CONSTANT_ALPHA:
391 return BLEND_CONSTANT_ALPHA;
392 break;
393 case GL_ONE_MINUS_CONSTANT_ALPHA:
394 return BLEND_ONE_MINUS_CONSTANT_ALPHA;
395 break;
396 default:
397 fprintf(stderr, "unknown blend factor %x\n", factor);
398 return (is_src) ? BLEND_ONE : BLEND_ZERO;
399 break;
400 }
401 }
402
403 static void r700SetBlendState(GLcontext * ctx)
404 {
405 context_t *context = R700_CONTEXT(ctx);
406 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
407 int id = 0;
408 uint32_t blend_reg = 0, eqn, eqnA;
409
410 R600_STATECHANGE(context, blnd);
411
412 if (RGBA_LOGICOP_ENABLED(ctx) || !ctx->Color.BlendEnabled) {
413 SETfield(blend_reg,
414 BLEND_ONE, COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
415 SETfield(blend_reg,
416 BLEND_ZERO, COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
417 SETfield(blend_reg,
418 COMB_DST_PLUS_SRC, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
419 SETfield(blend_reg,
420 BLEND_ONE, ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
421 SETfield(blend_reg,
422 BLEND_ZERO, ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
423 SETfield(blend_reg,
424 COMB_DST_PLUS_SRC, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
425 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
426 r700->CB_BLEND_CONTROL.u32All = blend_reg;
427 else
428 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
429 return;
430 }
431
432 SETfield(blend_reg,
433 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
434 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
435 SETfield(blend_reg,
436 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
437 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
438
439 switch (ctx->Color.BlendEquationRGB) {
440 case GL_FUNC_ADD:
441 eqn = COMB_DST_PLUS_SRC;
442 break;
443 case GL_FUNC_SUBTRACT:
444 eqn = COMB_SRC_MINUS_DST;
445 break;
446 case GL_FUNC_REVERSE_SUBTRACT:
447 eqn = COMB_DST_MINUS_SRC;
448 break;
449 case GL_MIN:
450 eqn = COMB_MIN_DST_SRC;
451 SETfield(blend_reg,
452 BLEND_ONE,
453 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
454 SETfield(blend_reg,
455 BLEND_ONE,
456 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
457 break;
458 case GL_MAX:
459 eqn = COMB_MAX_DST_SRC;
460 SETfield(blend_reg,
461 BLEND_ONE,
462 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
463 SETfield(blend_reg,
464 BLEND_ONE,
465 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
466 break;
467
468 default:
469 fprintf(stderr,
470 "[%s:%u] Invalid RGB blend equation (0x%04x).\n",
471 __FUNCTION__, __LINE__, ctx->Color.BlendEquationRGB);
472 return;
473 }
474 SETfield(blend_reg,
475 eqn, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
476
477 SETfield(blend_reg,
478 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
479 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
480 SETfield(blend_reg,
481 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
482 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
483
484 switch (ctx->Color.BlendEquationA) {
485 case GL_FUNC_ADD:
486 eqnA = COMB_DST_PLUS_SRC;
487 break;
488 case GL_FUNC_SUBTRACT:
489 eqnA = COMB_SRC_MINUS_DST;
490 break;
491 case GL_FUNC_REVERSE_SUBTRACT:
492 eqnA = COMB_DST_MINUS_SRC;
493 break;
494 case GL_MIN:
495 eqnA = COMB_MIN_DST_SRC;
496 SETfield(blend_reg,
497 BLEND_ONE,
498 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
499 SETfield(blend_reg,
500 BLEND_ONE,
501 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
502 break;
503 case GL_MAX:
504 eqnA = COMB_MAX_DST_SRC;
505 SETfield(blend_reg,
506 BLEND_ONE,
507 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
508 SETfield(blend_reg,
509 BLEND_ONE,
510 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
511 break;
512 default:
513 fprintf(stderr,
514 "[%s:%u] Invalid A blend equation (0x%04x).\n",
515 __FUNCTION__, __LINE__, ctx->Color.BlendEquationA);
516 return;
517 }
518
519 SETfield(blend_reg,
520 eqnA, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
521
522 SETbit(blend_reg, SEPARATE_ALPHA_BLEND_bit);
523
524 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
525 r700->CB_BLEND_CONTROL.u32All = blend_reg;
526 else {
527 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
528 SETbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit);
529 }
530 SETfield(r700->CB_COLOR_CONTROL.u32All, (1 << id),
531 TARGET_BLEND_ENABLE_shift, TARGET_BLEND_ENABLE_mask);
532
533 }
534
535 static void r700BlendEquationSeparate(GLcontext * ctx,
536 GLenum modeRGB, GLenum modeA) //-----------------
537 {
538 r700SetBlendState(ctx);
539 }
540
541 static void r700BlendFuncSeparate(GLcontext * ctx,
542 GLenum sfactorRGB, GLenum dfactorRGB,
543 GLenum sfactorA, GLenum dfactorA) //------------------------
544 {
545 r700SetBlendState(ctx);
546 }
547
548 /**
549 * Translate LogicOp enums into hardware representation.
550 */
551 static GLuint translate_logicop(GLenum logicop)
552 {
553 switch (logicop) {
554 case GL_CLEAR:
555 return 0x00;
556 case GL_SET:
557 return 0xff;
558 case GL_COPY:
559 return 0xcc;
560 case GL_COPY_INVERTED:
561 return 0x33;
562 case GL_NOOP:
563 return 0xaa;
564 case GL_INVERT:
565 return 0x55;
566 case GL_AND:
567 return 0x88;
568 case GL_NAND:
569 return 0x77;
570 case GL_OR:
571 return 0xee;
572 case GL_NOR:
573 return 0x11;
574 case GL_XOR:
575 return 0x66;
576 case GL_EQUIV:
577 return 0xaa;
578 case GL_AND_REVERSE:
579 return 0x44;
580 case GL_AND_INVERTED:
581 return 0x22;
582 case GL_OR_REVERSE:
583 return 0xdd;
584 case GL_OR_INVERTED:
585 return 0xbb;
586 default:
587 fprintf(stderr, "unknown blend logic operation %x\n", logicop);
588 return 0xcc;
589 }
590 }
591
592 /**
593 * Used internally to update the r300->hw hardware state to match the
594 * current OpenGL state.
595 */
596 static void r700SetLogicOpState(GLcontext *ctx)
597 {
598 context_t *context = R700_CONTEXT(ctx);
599 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
600
601 R600_STATECHANGE(context, blnd);
602
603 if (RGBA_LOGICOP_ENABLED(ctx))
604 SETfield(r700->CB_COLOR_CONTROL.u32All,
605 translate_logicop(ctx->Color.LogicOp), ROP3_shift, ROP3_mask);
606 else
607 SETfield(r700->CB_COLOR_CONTROL.u32All, 0xCC, ROP3_shift, ROP3_mask);
608 }
609
610 /**
611 * Called by Mesa when an application program changes the LogicOp state
612 * via glLogicOp.
613 */
614 static void r700LogicOpcode(GLcontext *ctx, GLenum logicop)
615 {
616 if (RGBA_LOGICOP_ENABLED(ctx))
617 r700SetLogicOpState(ctx);
618 }
619
620 static void r700UpdateCulling(GLcontext * ctx)
621 {
622 context_t *context = R700_CONTEXT(ctx);
623 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
624
625 R600_STATECHANGE(context, su);
626
627 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
628 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
629 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
630
631 if (ctx->Polygon.CullFlag)
632 {
633 switch (ctx->Polygon.CullFaceMode)
634 {
635 case GL_FRONT:
636 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
637 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
638 break;
639 case GL_BACK:
640 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
641 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
642 break;
643 case GL_FRONT_AND_BACK:
644 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
645 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
646 break;
647 default:
648 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
649 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
650 break;
651 }
652 }
653
654 switch (ctx->Polygon.FrontFace)
655 {
656 case GL_CW:
657 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
658 break;
659 case GL_CCW:
660 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
661 break;
662 default:
663 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); /* default: ccw */
664 break;
665 }
666 }
667
668 static void r700UpdateLineStipple(GLcontext * ctx)
669 {
670 context_t *context = R700_CONTEXT(ctx);
671 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
672
673 R600_STATECHANGE(context, sc);
674
675 if (ctx->Line.StippleFlag)
676 {
677 SETbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
678 }
679 else
680 {
681 CLEARbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
682 }
683 }
684
685 static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //------------------
686 {
687 context_t *context = R700_CONTEXT(ctx);
688
689 switch (cap) {
690 case GL_TEXTURE_1D:
691 case GL_TEXTURE_2D:
692 case GL_TEXTURE_3D:
693 /* empty */
694 break;
695 case GL_FOG:
696 /* empty */
697 break;
698 case GL_ALPHA_TEST:
699 r700SetAlphaState(ctx);
700 break;
701 case GL_COLOR_LOGIC_OP:
702 r700SetLogicOpState(ctx);
703 /* fall-through, because logic op overrides blending */
704 case GL_BLEND:
705 r700SetBlendState(ctx);
706 break;
707 case GL_CLIP_PLANE0:
708 case GL_CLIP_PLANE1:
709 case GL_CLIP_PLANE2:
710 case GL_CLIP_PLANE3:
711 case GL_CLIP_PLANE4:
712 case GL_CLIP_PLANE5:
713 r700SetClipPlaneState(ctx, cap, state);
714 break;
715 case GL_DEPTH_TEST:
716 r700SetDepthState(ctx);
717 break;
718 case GL_STENCIL_TEST:
719 r700SetStencilState(ctx, state);
720 break;
721 case GL_CULL_FACE:
722 r700UpdateCulling(ctx);
723 break;
724 case GL_POLYGON_OFFSET_POINT:
725 case GL_POLYGON_OFFSET_LINE:
726 case GL_POLYGON_OFFSET_FILL:
727 r700SetPolygonOffsetState(ctx, state);
728 break;
729 case GL_SCISSOR_TEST:
730 radeon_firevertices(&context->radeon);
731 context->radeon.state.scissor.enabled = state;
732 radeonUpdateScissor(ctx);
733 break;
734 case GL_LINE_STIPPLE:
735 r700UpdateLineStipple(ctx);
736 break;
737 default:
738 break;
739 }
740
741 }
742
743 /**
744 * Handle glColorMask()
745 */
746 static void r700ColorMask(GLcontext * ctx,
747 GLboolean r, GLboolean g, GLboolean b, GLboolean a) //------------------
748 {
749 context_t *context = R700_CONTEXT(ctx);
750 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
751 unsigned int mask = ((r ? 1 : 0) |
752 (g ? 2 : 0) |
753 (b ? 4 : 0) |
754 (a ? 8 : 0));
755
756 if (mask != r700->CB_SHADER_MASK.u32All) {
757 R600_STATECHANGE(context, cb);
758 SETfield(r700->CB_SHADER_MASK.u32All, mask, OUTPUT0_ENABLE_shift, OUTPUT0_ENABLE_mask);
759 }
760 }
761
762 /**
763 * Change the depth testing function.
764 *
765 * \note Mesa already filters redundant calls to this function.
766 */
767 static void r700DepthFunc(GLcontext * ctx, GLenum func) //--------------------
768 {
769 r700SetDepthState(ctx);
770 }
771
772 /**
773 * Enable/Disable depth writing.
774 *
775 * \note Mesa already filters redundant calls to this function.
776 */
777 static void r700DepthMask(GLcontext * ctx, GLboolean mask) //------------------
778 {
779 r700SetDepthState(ctx);
780 }
781
782 /**
783 * Change the culling mode.
784 *
785 * \note Mesa already filters redundant calls to this function.
786 */
787 static void r700CullFace(GLcontext * ctx, GLenum mode) //-----------------
788 {
789 r700UpdateCulling(ctx);
790 }
791
792 /* =============================================================
793 * Fog
794 */
795 static void r700Fogfv(GLcontext * ctx, GLenum pname, const GLfloat * param) //--------------
796 {
797 }
798
799 /**
800 * Change the polygon orientation.
801 *
802 * \note Mesa already filters redundant calls to this function.
803 */
804 static void r700FrontFace(GLcontext * ctx, GLenum mode) //------------------
805 {
806 r700UpdateCulling(ctx);
807 r700UpdatePolygonMode(ctx);
808 }
809
810 static void r700ShadeModel(GLcontext * ctx, GLenum mode) //--------------------
811 {
812 context_t *context = R700_CONTEXT(ctx);
813 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
814
815 R600_STATECHANGE(context, spi);
816
817 /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */
818 switch (mode) {
819 case GL_FLAT:
820 SETbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
821 break;
822 case GL_SMOOTH:
823 CLEARbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
824 break;
825 default:
826 return;
827 }
828 }
829
830 /* =============================================================
831 * Point state
832 */
833 static void r700PointSize(GLcontext * ctx, GLfloat size)
834 {
835 context_t *context = R700_CONTEXT(ctx);
836 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
837
838 R600_STATECHANGE(context, su);
839
840 /* We need to clamp to user defined range here, because
841 * the HW clamping happens only for per vertex point size. */
842 size = CLAMP(size, ctx->Point.MinSize, ctx->Point.MaxSize);
843
844 /* same size limits for AA, non-AA points */
845 size = CLAMP(size, ctx->Const.MinPointSize, ctx->Const.MaxPointSize);
846
847 /* format is 12.4 fixed point */
848 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 8.0),
849 PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask);
850 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 8.0),
851 PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask);
852
853 }
854
855 static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * param) //---------------
856 {
857 context_t *context = R700_CONTEXT(ctx);
858 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
859
860 R600_STATECHANGE(context, su);
861
862 /* format is 12.4 fixed point */
863 switch (pname) {
864 case GL_POINT_SIZE_MIN:
865 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MinSize * 8.0),
866 MIN_SIZE_shift, MIN_SIZE_mask);
867 break;
868 case GL_POINT_SIZE_MAX:
869 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MaxSize * 8.0),
870 MAX_SIZE_shift, MAX_SIZE_mask);
871 break;
872 case GL_POINT_DISTANCE_ATTENUATION:
873 break;
874 case GL_POINT_FADE_THRESHOLD_SIZE:
875 break;
876 default:
877 break;
878 }
879 }
880
881 static int translate_stencil_func(int func)
882 {
883 switch (func) {
884 case GL_NEVER:
885 return REF_NEVER;
886 case GL_LESS:
887 return REF_LESS;
888 case GL_EQUAL:
889 return REF_EQUAL;
890 case GL_LEQUAL:
891 return REF_LEQUAL;
892 case GL_GREATER:
893 return REF_GREATER;
894 case GL_NOTEQUAL:
895 return REF_NOTEQUAL;
896 case GL_GEQUAL:
897 return REF_GEQUAL;
898 case GL_ALWAYS:
899 return REF_ALWAYS;
900 }
901 return 0;
902 }
903
904 static int translate_stencil_op(int op)
905 {
906 switch (op) {
907 case GL_KEEP:
908 return STENCIL_KEEP;
909 case GL_ZERO:
910 return STENCIL_ZERO;
911 case GL_REPLACE:
912 return STENCIL_REPLACE;
913 case GL_INCR:
914 return STENCIL_INCR_CLAMP;
915 case GL_DECR:
916 return STENCIL_DECR_CLAMP;
917 case GL_INCR_WRAP_EXT:
918 return STENCIL_INCR_WRAP;
919 case GL_DECR_WRAP_EXT:
920 return STENCIL_DECR_WRAP;
921 case GL_INVERT:
922 return STENCIL_INVERT;
923 default:
924 WARN_ONCE("Do not know how to translate stencil op");
925 return STENCIL_KEEP;
926 }
927 return 0;
928 }
929
930 static void r700SetStencilState(GLcontext * ctx, GLboolean state)
931 {
932 context_t *context = R700_CONTEXT(ctx);
933 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
934 GLboolean hw_stencil = GL_FALSE;
935
936 if (ctx->DrawBuffer) {
937 struct radeon_renderbuffer *rrbStencil
938 = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
939 hw_stencil = (rrbStencil && rrbStencil->bo);
940 }
941
942 if (hw_stencil) {
943 R600_STATECHANGE(context, db);
944 if (state) {
945 SETbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
946 SETbit(r700->DB_DEPTH_CONTROL.u32All, BACKFACE_ENABLE_bit);
947 } else
948 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
949 }
950 }
951
952 static void r700StencilFuncSeparate(GLcontext * ctx, GLenum face,
953 GLenum func, GLint ref, GLuint mask) //---------------------
954 {
955 context_t *context = R700_CONTEXT(ctx);
956 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
957 const unsigned back = ctx->Stencil._BackFace;
958
959 R600_STATECHANGE(context, stencil);
960 R600_STATECHANGE(context, db);
961
962 //front
963 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.Ref[0],
964 STENCILREF_shift, STENCILREF_mask);
965 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.ValueMask[0],
966 STENCILMASK_shift, STENCILMASK_mask);
967
968 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[0]),
969 STENCILFUNC_shift, STENCILFUNC_mask);
970
971 //back
972 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.Ref[back],
973 STENCILREF_BF_shift, STENCILREF_BF_mask);
974 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.ValueMask[back],
975 STENCILMASK_BF_shift, STENCILMASK_BF_mask);
976
977 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[back]),
978 STENCILFUNC_BF_shift, STENCILFUNC_BF_mask);
979
980 }
981
982 static void r700StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) //--------------
983 {
984 context_t *context = R700_CONTEXT(ctx);
985 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
986 const unsigned back = ctx->Stencil._BackFace;
987
988 R600_STATECHANGE(context, stencil);
989
990 // front
991 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.WriteMask[0],
992 STENCILWRITEMASK_shift, STENCILWRITEMASK_mask);
993
994 // back
995 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.WriteMask[back],
996 STENCILWRITEMASK_BF_shift, STENCILWRITEMASK_BF_mask);
997
998 }
999
1000 static void r700StencilOpSeparate(GLcontext * ctx, GLenum face,
1001 GLenum fail, GLenum zfail, GLenum zpass) //--------------------
1002 {
1003 context_t *context = R700_CONTEXT(ctx);
1004 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1005 const unsigned back = ctx->Stencil._BackFace;
1006
1007 R600_STATECHANGE(context, db);
1008
1009 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[0]),
1010 STENCILFAIL_shift, STENCILFAIL_mask);
1011 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[0]),
1012 STENCILZFAIL_shift, STENCILZFAIL_mask);
1013 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[0]),
1014 STENCILZPASS_shift, STENCILZPASS_mask);
1015
1016 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[back]),
1017 STENCILFAIL_BF_shift, STENCILFAIL_BF_mask);
1018 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[back]),
1019 STENCILZFAIL_BF_shift, STENCILZFAIL_BF_mask);
1020 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[back]),
1021 STENCILZPASS_BF_shift, STENCILZPASS_BF_mask);
1022 }
1023
1024 static void r700UpdateWindow(GLcontext * ctx, int id) //--------------------
1025 {
1026 context_t *context = R700_CONTEXT(ctx);
1027 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1028 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
1029 GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
1030 GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
1031 const GLfloat *v = ctx->Viewport._WindowMap.m;
1032 const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
1033 const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
1034 GLfloat y_scale, y_bias;
1035
1036 if (render_to_fbo) {
1037 y_scale = 1.0;
1038 y_bias = 0;
1039 } else {
1040 y_scale = -1.0;
1041 y_bias = yoffset;
1042 }
1043
1044 GLfloat sx = v[MAT_SX];
1045 GLfloat tx = v[MAT_TX] + xoffset;
1046 GLfloat sy = v[MAT_SY] * y_scale;
1047 GLfloat ty = (v[MAT_TY] * y_scale) + y_bias;
1048 GLfloat sz = v[MAT_SZ] * depthScale;
1049 GLfloat tz = v[MAT_TZ] * depthScale;
1050
1051 R600_STATECHANGE(context, vpt);
1052
1053 r700->viewport[id].PA_CL_VPORT_XSCALE.f32All = sx;
1054 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
1055
1056 r700->viewport[id].PA_CL_VPORT_YSCALE.f32All = sy;
1057 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
1058
1059 r700->viewport[id].PA_CL_VPORT_ZSCALE.f32All = sz;
1060 r700->viewport[id].PA_CL_VPORT_ZOFFSET.f32All = tz;
1061
1062 r700->viewport[id].enabled = GL_TRUE;
1063
1064 r700SetScissor(context);
1065 }
1066
1067
1068 static void r700Viewport(GLcontext * ctx,
1069 GLint x,
1070 GLint y,
1071 GLsizei width,
1072 GLsizei height) //--------------------
1073 {
1074 r700UpdateWindow(ctx, 0);
1075
1076 radeon_viewport(ctx, x, y, width, height);
1077 }
1078
1079 static void r700DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) //-------------
1080 {
1081 r700UpdateWindow(ctx, 0);
1082 }
1083
1084 static void r700LineWidth(GLcontext * ctx, GLfloat widthf) //---------------
1085 {
1086 context_t *context = R700_CONTEXT(ctx);
1087 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1088 uint32_t lineWidth = (uint32_t)((widthf * 0.5) * (1 << 4));
1089
1090 R600_STATECHANGE(context, su);
1091
1092 if (lineWidth > 0xFFFF)
1093 lineWidth = 0xFFFF;
1094 SETfield(r700->PA_SU_LINE_CNTL.u32All,(uint16_t)lineWidth,
1095 PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
1096 }
1097
1098 static void r700LineStipple(GLcontext *ctx, GLint factor, GLushort pattern)
1099 {
1100 context_t *context = R700_CONTEXT(ctx);
1101 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1102
1103 R600_STATECHANGE(context, sc);
1104
1105 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, pattern, LINE_PATTERN_shift, LINE_PATTERN_mask);
1106 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, (factor-1), REPEAT_COUNT_shift, REPEAT_COUNT_mask);
1107 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, 1, AUTO_RESET_CNTL_shift, AUTO_RESET_CNTL_mask);
1108 }
1109
1110 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state)
1111 {
1112 context_t *context = R700_CONTEXT(ctx);
1113 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1114
1115 R600_STATECHANGE(context, su);
1116
1117 if (state) {
1118 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1119 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1120 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1121 } else {
1122 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1123 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1124 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1125 }
1126 }
1127
1128 static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) //--------------
1129 {
1130 context_t *context = R700_CONTEXT(ctx);
1131 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1132 GLfloat constant = units;
1133 GLchar depth = 0;
1134
1135 R600_STATECHANGE(context, poly);
1136
1137 switch (ctx->Visual.depthBits) {
1138 case 16:
1139 constant *= 4.0;
1140 depth = -16;
1141 break;
1142 case 24:
1143 constant *= 2.0;
1144 depth = -24;
1145 break;
1146 }
1147
1148 factor *= 12.0;
1149 SETfield(r700->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All, depth,
1150 POLY_OFFSET_NEG_NUM_DB_BITS_shift, POLY_OFFSET_NEG_NUM_DB_BITS_mask);
1151 //r700->PA_SU_POLY_OFFSET_CLAMP.f32All = constant; //???
1152 r700->PA_SU_POLY_OFFSET_FRONT_SCALE.f32All = factor;
1153 r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.f32All = constant;
1154 r700->PA_SU_POLY_OFFSET_BACK_SCALE.f32All = factor;
1155 r700->PA_SU_POLY_OFFSET_BACK_OFFSET.f32All = constant;
1156 }
1157
1158 static void r700UpdatePolygonMode(GLcontext * ctx)
1159 {
1160 context_t *context = R700_CONTEXT(ctx);
1161 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1162
1163 R600_STATECHANGE(context, su);
1164
1165 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DISABLE_POLY_MODE, POLY_MODE_shift, POLY_MODE_mask);
1166
1167 /* Only do something if a polygon mode is wanted, default is GL_FILL */
1168 if (ctx->Polygon.FrontMode != GL_FILL ||
1169 ctx->Polygon.BackMode != GL_FILL) {
1170 GLenum f, b;
1171
1172 /* Handle GL_CW (clock wise and GL_CCW (counter clock wise)
1173 * correctly by selecting the correct front and back face
1174 */
1175 if (ctx->Polygon.FrontFace == GL_CCW) {
1176 f = ctx->Polygon.FrontMode;
1177 b = ctx->Polygon.BackMode;
1178 } else {
1179 f = ctx->Polygon.BackMode;
1180 b = ctx->Polygon.FrontMode;
1181 }
1182
1183 /* Enable polygon mode */
1184 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DUAL_MODE, POLY_MODE_shift, POLY_MODE_mask);
1185
1186 switch (f) {
1187 case GL_LINE:
1188 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1189 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1190 break;
1191 case GL_POINT:
1192 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1193 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1194 break;
1195 case GL_FILL:
1196 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1197 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1198 break;
1199 }
1200
1201 switch (b) {
1202 case GL_LINE:
1203 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1204 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1205 break;
1206 case GL_POINT:
1207 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1208 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1209 break;
1210 case GL_FILL:
1211 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1212 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1213 break;
1214 }
1215 }
1216 }
1217
1218 static void r700PolygonMode(GLcontext * ctx, GLenum face, GLenum mode) //------------------
1219 {
1220 (void)face;
1221 (void)mode;
1222
1223 r700UpdatePolygonMode(ctx);
1224 }
1225
1226 static void r700RenderMode(GLcontext * ctx, GLenum mode) //---------------------
1227 {
1228 }
1229
1230 static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
1231 {
1232 context_t *context = R700_CONTEXT(ctx);
1233 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1234 GLint p;
1235 GLint *ip;
1236
1237 p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
1238 ip = (GLint *)ctx->Transform._ClipUserPlane[p];
1239
1240 R600_STATECHANGE(context, ucp);
1241
1242 r700->ucp[p].PA_CL_UCP_0_X.u32All = ip[0];
1243 r700->ucp[p].PA_CL_UCP_0_Y.u32All = ip[1];
1244 r700->ucp[p].PA_CL_UCP_0_Z.u32All = ip[2];
1245 r700->ucp[p].PA_CL_UCP_0_W.u32All = ip[3];
1246 }
1247
1248 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state)
1249 {
1250 context_t *context = R700_CONTEXT(ctx);
1251 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1252 GLuint p;
1253
1254 p = cap - GL_CLIP_PLANE0;
1255
1256 R600_STATECHANGE(context, cl);
1257
1258 if (state) {
1259 r700->PA_CL_CLIP_CNTL.u32All |= (UCP_ENA_0_bit << p);
1260 r700->ucp[p].enabled = GL_TRUE;
1261 r700ClipPlane(ctx, cap, NULL);
1262 } else {
1263 r700->PA_CL_CLIP_CNTL.u32All &= ~(UCP_ENA_0_bit << p);
1264 r700->ucp[p].enabled = GL_FALSE;
1265 }
1266 }
1267
1268 void r700SetScissor(context_t *context) //---------------
1269 {
1270 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1271 unsigned x1, y1, x2, y2;
1272 int id = 0;
1273 struct radeon_renderbuffer *rrb;
1274
1275 rrb = radeon_get_colorbuffer(&context->radeon);
1276 if (!rrb || !rrb->bo) {
1277 return;
1278 }
1279 if (context->radeon.state.scissor.enabled) {
1280 x1 = context->radeon.state.scissor.rect.x1;
1281 y1 = context->radeon.state.scissor.rect.y1;
1282 x2 = context->radeon.state.scissor.rect.x2;
1283 y2 = context->radeon.state.scissor.rect.y2;
1284 } else {
1285 if (context->radeon.radeonScreen->driScreen->dri2.enabled) {
1286 x1 = 0;
1287 y1 = 0;
1288 x2 = rrb->base.Width;
1289 y2 = rrb->base.Height;
1290 } else {
1291 x1 = rrb->dPriv->x;
1292 y1 = rrb->dPriv->y;
1293 x2 = rrb->dPriv->x + rrb->dPriv->w;
1294 y2 = rrb->dPriv->y + rrb->dPriv->h;
1295 }
1296 }
1297
1298 R600_STATECHANGE(context, scissor);
1299
1300 /* screen */
1301 SETbit(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1302 SETfield(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, x1,
1303 PA_SC_SCREEN_SCISSOR_TL__TL_X_shift, PA_SC_SCREEN_SCISSOR_TL__TL_X_mask);
1304 SETfield(r700->PA_SC_SCREEN_SCISSOR_TL.u32All, y1,
1305 PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift, PA_SC_SCREEN_SCISSOR_TL__TL_Y_mask);
1306
1307 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, x2,
1308 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask);
1309 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, y2,
1310 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask);
1311
1312 /* window */
1313 SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1314 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, x1,
1315 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask);
1316 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, y1,
1317 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask);
1318
1319 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, x2,
1320 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask);
1321 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, y2,
1322 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask);
1323
1324
1325 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, x1,
1326 PA_SC_CLIPRECT_0_TL__TL_X_shift, PA_SC_CLIPRECT_0_TL__TL_X_mask);
1327 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, y1,
1328 PA_SC_CLIPRECT_0_TL__TL_Y_shift, PA_SC_CLIPRECT_0_TL__TL_Y_mask);
1329 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, x2,
1330 PA_SC_CLIPRECT_0_BR__BR_X_shift, PA_SC_CLIPRECT_0_BR__BR_X_mask);
1331 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, y2,
1332 PA_SC_CLIPRECT_0_BR__BR_Y_shift, PA_SC_CLIPRECT_0_BR__BR_Y_mask);
1333
1334 r700->PA_SC_CLIPRECT_1_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1335 r700->PA_SC_CLIPRECT_1_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1336 r700->PA_SC_CLIPRECT_2_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1337 r700->PA_SC_CLIPRECT_2_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1338 r700->PA_SC_CLIPRECT_3_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1339 r700->PA_SC_CLIPRECT_3_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1340
1341 /* more....2d clip */
1342 SETbit(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1343 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, x1,
1344 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask);
1345 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, y1,
1346 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask);
1347 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, x2,
1348 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask);
1349 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, y2,
1350 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask);
1351
1352 SETbit(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1353 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, x1,
1354 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask);
1355 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, y1,
1356 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask);
1357 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, x2,
1358 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask);
1359 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, y2,
1360 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask);
1361
1362 r700->viewport[id].PA_SC_VPORT_ZMIN_0.u32All = 0;
1363 r700->viewport[id].PA_SC_VPORT_ZMAX_0.u32All = 0x3F800000;
1364 r700->viewport[id].enabled = GL_TRUE;
1365 }
1366
1367 static void r700InitSQConfig(GLcontext * ctx)
1368 {
1369 context_t *context = R700_CONTEXT(ctx);
1370 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1371 int ps_prio;
1372 int vs_prio;
1373 int gs_prio;
1374 int es_prio;
1375 int num_ps_gprs;
1376 int num_vs_gprs;
1377 int num_gs_gprs;
1378 int num_es_gprs;
1379 int num_temp_gprs;
1380 int num_ps_threads;
1381 int num_vs_threads;
1382 int num_gs_threads;
1383 int num_es_threads;
1384 int num_ps_stack_entries;
1385 int num_vs_stack_entries;
1386 int num_gs_stack_entries;
1387 int num_es_stack_entries;
1388
1389 R600_STATECHANGE(context, sq);
1390
1391 // SQ
1392 ps_prio = 0;
1393 vs_prio = 1;
1394 gs_prio = 2;
1395 es_prio = 3;
1396 switch (context->radeon.radeonScreen->chip_family) {
1397 case CHIP_FAMILY_R600:
1398 num_ps_gprs = 192;
1399 num_vs_gprs = 56;
1400 num_temp_gprs = 4;
1401 num_gs_gprs = 0;
1402 num_es_gprs = 0;
1403 num_ps_threads = 136;
1404 num_vs_threads = 48;
1405 num_gs_threads = 4;
1406 num_es_threads = 4;
1407 num_ps_stack_entries = 128;
1408 num_vs_stack_entries = 128;
1409 num_gs_stack_entries = 0;
1410 num_es_stack_entries = 0;
1411 break;
1412 case CHIP_FAMILY_RV630:
1413 case CHIP_FAMILY_RV635:
1414 num_ps_gprs = 84;
1415 num_vs_gprs = 36;
1416 num_temp_gprs = 4;
1417 num_gs_gprs = 0;
1418 num_es_gprs = 0;
1419 num_ps_threads = 144;
1420 num_vs_threads = 40;
1421 num_gs_threads = 4;
1422 num_es_threads = 4;
1423 num_ps_stack_entries = 40;
1424 num_vs_stack_entries = 40;
1425 num_gs_stack_entries = 32;
1426 num_es_stack_entries = 16;
1427 break;
1428 case CHIP_FAMILY_RV610:
1429 case CHIP_FAMILY_RV620:
1430 case CHIP_FAMILY_RS780:
1431 case CHIP_FAMILY_RS880:
1432 default:
1433 num_ps_gprs = 84;
1434 num_vs_gprs = 36;
1435 num_temp_gprs = 4;
1436 num_gs_gprs = 0;
1437 num_es_gprs = 0;
1438 num_ps_threads = 136;
1439 num_vs_threads = 48;
1440 num_gs_threads = 4;
1441 num_es_threads = 4;
1442 num_ps_stack_entries = 40;
1443 num_vs_stack_entries = 40;
1444 num_gs_stack_entries = 32;
1445 num_es_stack_entries = 16;
1446 break;
1447 case CHIP_FAMILY_RV670:
1448 num_ps_gprs = 144;
1449 num_vs_gprs = 40;
1450 num_temp_gprs = 4;
1451 num_gs_gprs = 0;
1452 num_es_gprs = 0;
1453 num_ps_threads = 136;
1454 num_vs_threads = 48;
1455 num_gs_threads = 4;
1456 num_es_threads = 4;
1457 num_ps_stack_entries = 40;
1458 num_vs_stack_entries = 40;
1459 num_gs_stack_entries = 32;
1460 num_es_stack_entries = 16;
1461 break;
1462 case CHIP_FAMILY_RV770:
1463 num_ps_gprs = 192;
1464 num_vs_gprs = 56;
1465 num_temp_gprs = 4;
1466 num_gs_gprs = 0;
1467 num_es_gprs = 0;
1468 num_ps_threads = 188;
1469 num_vs_threads = 60;
1470 num_gs_threads = 0;
1471 num_es_threads = 0;
1472 num_ps_stack_entries = 256;
1473 num_vs_stack_entries = 256;
1474 num_gs_stack_entries = 0;
1475 num_es_stack_entries = 0;
1476 break;
1477 case CHIP_FAMILY_RV730:
1478 case CHIP_FAMILY_RV740:
1479 num_ps_gprs = 84;
1480 num_vs_gprs = 36;
1481 num_temp_gprs = 4;
1482 num_gs_gprs = 0;
1483 num_es_gprs = 0;
1484 num_ps_threads = 188;
1485 num_vs_threads = 60;
1486 num_gs_threads = 0;
1487 num_es_threads = 0;
1488 num_ps_stack_entries = 128;
1489 num_vs_stack_entries = 128;
1490 num_gs_stack_entries = 0;
1491 num_es_stack_entries = 0;
1492 break;
1493 case CHIP_FAMILY_RV710:
1494 num_ps_gprs = 192;
1495 num_vs_gprs = 56;
1496 num_temp_gprs = 4;
1497 num_gs_gprs = 0;
1498 num_es_gprs = 0;
1499 num_ps_threads = 144;
1500 num_vs_threads = 48;
1501 num_gs_threads = 0;
1502 num_es_threads = 0;
1503 num_ps_stack_entries = 128;
1504 num_vs_stack_entries = 128;
1505 num_gs_stack_entries = 0;
1506 num_es_stack_entries = 0;
1507 break;
1508 }
1509
1510 r700->sq_config.SQ_CONFIG.u32All = 0;
1511 if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
1512 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
1513 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
1514 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) ||
1515 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
1516 CLEARbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1517 else
1518 SETbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1519 SETbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit);
1520 SETbit(r700->sq_config.SQ_CONFIG.u32All, ALU_INST_PREFER_VECTOR_bit);
1521 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, PS_PRIO_shift, PS_PRIO_mask);
1522 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, VS_PRIO_shift, VS_PRIO_mask);
1523 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, GS_PRIO_shift, GS_PRIO_mask);
1524 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, ES_PRIO_shift, ES_PRIO_mask);
1525
1526 r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All = 0;
1527 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_ps_gprs, NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
1528 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_vs_gprs, NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
1529 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_temp_gprs,
1530 NUM_CLAUSE_TEMP_GPRS_shift, NUM_CLAUSE_TEMP_GPRS_mask);
1531
1532 r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All = 0;
1533 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_gs_gprs, NUM_GS_GPRS_shift, NUM_GS_GPRS_mask);
1534 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_es_gprs, NUM_ES_GPRS_shift, NUM_ES_GPRS_mask);
1535
1536 r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All = 0;
1537 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_ps_threads,
1538 NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
1539 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_vs_threads,
1540 NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
1541 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_gs_threads,
1542 NUM_GS_THREADS_shift, NUM_GS_THREADS_mask);
1543 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_es_threads,
1544 NUM_ES_THREADS_shift, NUM_ES_THREADS_mask);
1545
1546 r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All = 0;
1547 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_ps_stack_entries,
1548 NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
1549 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_vs_stack_entries,
1550 NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
1551
1552 r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All = 0;
1553 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_gs_stack_entries,
1554 NUM_GS_STACK_ENTRIES_shift, NUM_GS_STACK_ENTRIES_mask);
1555 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_es_stack_entries,
1556 NUM_ES_STACK_ENTRIES_shift, NUM_ES_STACK_ENTRIES_mask);
1557
1558 }
1559
1560 /**
1561 * Calculate initial hardware state and register state functions.
1562 * Assumes that the command buffer and state atoms have been
1563 * initialized already.
1564 */
1565 void r700InitState(GLcontext * ctx) //-------------------
1566 {
1567 context_t *context = R700_CONTEXT(ctx);
1568 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1569 int id = 0;
1570
1571 radeon_firevertices(&context->radeon);
1572
1573 r700->TA_CNTL_AUX.u32All = 0;
1574 SETfield(r700->TA_CNTL_AUX.u32All, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask);
1575 r700->VC_ENHANCE.u32All = 0;
1576 r700->DB_WATERMARKS.u32All = 0;
1577 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_FREE_shift, DEPTH_FREE_mask);
1578 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_FLUSH_shift, DEPTH_FLUSH_mask);
1579 SETfield(r700->DB_WATERMARKS.u32All, 0, FORCE_SUMMARIZE_shift, FORCE_SUMMARIZE_mask);
1580 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_PENDING_FREE_shift, DEPTH_PENDING_FREE_mask);
1581 r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All = 0;
1582 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1583 SETfield(r700->TA_CNTL_AUX.u32All, 3, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1584 r700->DB_DEBUG.u32All = 0x82000000;
1585 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1586 } else {
1587 SETfield(r700->TA_CNTL_AUX.u32All, 2, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1588 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1589 SETbit(r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All, VS_PC_LIMIT_ENABLE_bit);
1590 }
1591
1592 /* Turn off vgt reuse */
1593 r700->VGT_REUSE_OFF.u32All = 0;
1594 SETbit(r700->VGT_REUSE_OFF.u32All, REUSE_OFF_bit);
1595
1596 /* Specify offsetting and clamp values for vertices */
1597 r700->VGT_MAX_VTX_INDX.u32All = 0xFFFFFF;
1598 r700->VGT_MIN_VTX_INDX.u32All = 0;
1599 r700->VGT_INDX_OFFSET.u32All = 0;
1600
1601 /* default shader connections. */
1602 r700->SPI_VS_OUT_ID_0.u32All = 0x03020100;
1603 r700->SPI_VS_OUT_ID_1.u32All = 0x07060504;
1604 r700->SPI_VS_OUT_ID_2.u32All = 0x0b0a0908;
1605 r700->SPI_VS_OUT_ID_3.u32All = 0x0f0e0d0c;
1606
1607 r700->SPI_THREAD_GROUPING.u32All = 0;
1608 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
1609 SETfield(r700->SPI_THREAD_GROUPING.u32All, 1, PS_GROUPING_shift, PS_GROUPING_mask);
1610
1611 /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
1612 r700->PA_SC_CLIPRECT_RULE.u32All = 0;
1613 SETfield(r700->PA_SC_CLIPRECT_RULE.u32All, CLIP_RULE_mask, CLIP_RULE_shift, CLIP_RULE_mask);
1614
1615 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1616 r700->PA_SC_EDGERULE.u32All = 0;
1617 else
1618 r700->PA_SC_EDGERULE.u32All = 0xAAAAAAAA;
1619
1620 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1621 r700->PA_SC_MODE_CNTL.u32All = 0;
1622 SETbit(r700->PA_SC_MODE_CNTL.u32All, WALK_ORDER_ENABLE_bit);
1623 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1624 } else {
1625 r700->PA_SC_MODE_CNTL.u32All = 0x00500000;
1626 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_REZ_ENABLE_bit);
1627 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1628 }
1629
1630 /* Do scale XY and Z by 1/W0. */
1631 r700->bEnablePerspective = GL_TRUE;
1632 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
1633 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
1634 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
1635
1636 /* Enable viewport scaling for all three axis */
1637 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_SCALE_ENA_bit);
1638 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_OFFSET_ENA_bit);
1639 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_SCALE_ENA_bit);
1640 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_OFFSET_ENA_bit);
1641 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_SCALE_ENA_bit);
1642 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_OFFSET_ENA_bit);
1643
1644 /* GL uses last vtx for flat shading components */
1645 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
1646
1647 /* Set up vertex control */
1648 r700->PA_SU_VTX_CNTL.u32All = 0;
1649 CLEARfield(r700->PA_SU_VTX_CNTL.u32All, QUANT_MODE_mask);
1650 SETbit(r700->PA_SU_VTX_CNTL.u32All, PIX_CENTER_bit);
1651 SETfield(r700->PA_SU_VTX_CNTL.u32All, X_ROUND_TO_EVEN,
1652 PA_SU_VTX_CNTL__ROUND_MODE_shift, PA_SU_VTX_CNTL__ROUND_MODE_mask);
1653
1654 /* to 1.0 = no guard band */
1655 r700->PA_CL_GB_VERT_CLIP_ADJ.u32All = 0x3F800000; /* 1.0 */
1656 r700->PA_CL_GB_VERT_DISC_ADJ.u32All = 0x3F800000;
1657 r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All = 0x3F800000;
1658 r700->PA_CL_GB_HORZ_DISC_ADJ.u32All = 0x3F800000;
1659
1660 /* Enable all samples for multi-sample anti-aliasing */
1661 r700->PA_SC_AA_MASK.u32All = 0xFFFFFFFF;
1662 /* Turn off AA */
1663 r700->PA_SC_AA_CONFIG.u32All = 0;
1664
1665 r700->SX_MISC.u32All = 0;
1666
1667 r700InitSQConfig(ctx);
1668
1669 r700ColorMask(ctx,
1670 ctx->Color.ColorMask[RCOMP],
1671 ctx->Color.ColorMask[GCOMP],
1672 ctx->Color.ColorMask[BCOMP],
1673 ctx->Color.ColorMask[ACOMP]);
1674
1675 r700Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test);
1676 r700DepthMask(ctx, ctx->Depth.Mask);
1677 r700DepthFunc(ctx, ctx->Depth.Func);
1678 SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
1679
1680 r700->DB_DEPTH_CLEAR.u32All = 0x3F800000;
1681
1682 r700->DB_RENDER_CONTROL.u32All = 0;
1683 SETbit(r700->DB_RENDER_CONTROL.u32All, STENCIL_COMPRESS_DISABLE_bit);
1684 SETbit(r700->DB_RENDER_CONTROL.u32All, DEPTH_COMPRESS_DISABLE_bit);
1685 r700->DB_RENDER_OVERRIDE.u32All = 0;
1686 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1687 SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit);
1688 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
1689 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
1690 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
1691
1692 r700->DB_ALPHA_TO_MASK.u32All = 0;
1693 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask);
1694 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET1_shift, ALPHA_TO_MASK_OFFSET1_mask);
1695 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET2_shift, ALPHA_TO_MASK_OFFSET2_mask);
1696 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET3_shift, ALPHA_TO_MASK_OFFSET3_mask);
1697
1698 /* stencil */
1699 r700Enable(ctx, GL_STENCIL_TEST, ctx->Stencil._Enabled);
1700 r700StencilMaskSeparate(ctx, 0, ctx->Stencil.WriteMask[0]);
1701 r700StencilFuncSeparate(ctx, 0, ctx->Stencil.Function[0],
1702 ctx->Stencil.Ref[0], ctx->Stencil.ValueMask[0]);
1703 r700StencilOpSeparate(ctx, 0, ctx->Stencil.FailFunc[0],
1704 ctx->Stencil.ZFailFunc[0],
1705 ctx->Stencil.ZPassFunc[0]);
1706
1707 r700UpdateCulling(ctx);
1708
1709 r700SetBlendState(ctx);
1710 r700SetLogicOpState(ctx);
1711
1712 r700AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef);
1713 r700Enable(ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled);
1714
1715 r700PointSize(ctx, 1.0);
1716
1717 CLEARfield(r700->PA_SU_POINT_MINMAX.u32All, MIN_SIZE_mask);
1718 SETfield(r700->PA_SU_POINT_MINMAX.u32All, 0x8000, MAX_SIZE_shift, MAX_SIZE_mask);
1719
1720 r700LineWidth(ctx, 1.0);
1721
1722 r700->PA_SC_LINE_CNTL.u32All = 0;
1723 CLEARbit(r700->PA_SC_LINE_CNTL.u32All, EXPAND_LINE_WIDTH_bit);
1724 SETbit(r700->PA_SC_LINE_CNTL.u32All, LAST_PIXEL_bit);
1725
1726 r700ShadeModel(ctx, ctx->Light.ShadeModel);
1727 r700PolygonMode(ctx, GL_FRONT, ctx->Polygon.FrontMode);
1728 r700PolygonMode(ctx, GL_BACK, ctx->Polygon.BackMode);
1729 r700PolygonOffset(ctx, ctx->Polygon.OffsetFactor,
1730 ctx->Polygon.OffsetUnits);
1731 r700Enable(ctx, GL_POLYGON_OFFSET_POINT, ctx->Polygon.OffsetPoint);
1732 r700Enable(ctx, GL_POLYGON_OFFSET_LINE, ctx->Polygon.OffsetLine);
1733 r700Enable(ctx, GL_POLYGON_OFFSET_FILL, ctx->Polygon.OffsetFill);
1734
1735 /* CB */
1736 r700BlendColor(ctx, ctx->Color.BlendColor);
1737
1738 r700->CB_CLEAR_RED_R6XX.f32All = 1.0; //r6xx only
1739 r700->CB_CLEAR_GREEN_R6XX.f32All = 0.0; //r6xx only
1740 r700->CB_CLEAR_BLUE_R6XX.f32All = 1.0; //r6xx only
1741 r700->CB_CLEAR_ALPHA_R6XX.f32All = 1.0; //r6xx only
1742 r700->CB_FOG_RED_R6XX.u32All = 0; //r6xx only
1743 r700->CB_FOG_GREEN_R6XX.u32All = 0; //r6xx only
1744 r700->CB_FOG_BLUE_R6XX.u32All = 0; //r6xx only
1745
1746 /* Disable color compares */
1747 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1748 CLRCMP_FCN_SRC_shift, CLRCMP_FCN_SRC_mask);
1749 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1750 CLRCMP_FCN_DST_shift, CLRCMP_FCN_DST_mask);
1751 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_SEL_SRC,
1752 CLRCMP_FCN_SEL_shift, CLRCMP_FCN_SEL_mask);
1753
1754 /* Zero out source */
1755 r700->CB_CLRCMP_SRC.u32All = 0x00000000;
1756
1757 /* Put a compare color in for error checking */
1758 r700->CB_CLRCMP_DST.u32All = 0x000000FF;
1759
1760 /* Set up color compare mask */
1761 r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF;
1762
1763 /* screen/window/view */
1764 SETfield(r700->CB_TARGET_MASK.u32All, 0xF, (4 * id), TARGET0_ENABLE_mask);
1765
1766 context->radeon.hw.all_dirty = GL_TRUE;
1767
1768 }
1769
1770 void r700InitStateFuncs(struct dd_function_table *functions) //-----------------
1771 {
1772 functions->UpdateState = r700InvalidateState;
1773 functions->AlphaFunc = r700AlphaFunc;
1774 functions->BlendColor = r700BlendColor;
1775 functions->BlendEquationSeparate = r700BlendEquationSeparate;
1776 functions->BlendFuncSeparate = r700BlendFuncSeparate;
1777 functions->Enable = r700Enable;
1778 functions->ColorMask = r700ColorMask;
1779 functions->DepthFunc = r700DepthFunc;
1780 functions->DepthMask = r700DepthMask;
1781 functions->CullFace = r700CullFace;
1782 functions->Fogfv = r700Fogfv;
1783 functions->FrontFace = r700FrontFace;
1784 functions->ShadeModel = r700ShadeModel;
1785 functions->LogicOpcode = r700LogicOpcode;
1786
1787 /* ARB_point_parameters */
1788 functions->PointParameterfv = r700PointParameter;
1789
1790 /* Stencil related */
1791 functions->StencilFuncSeparate = r700StencilFuncSeparate;
1792 functions->StencilMaskSeparate = r700StencilMaskSeparate;
1793 functions->StencilOpSeparate = r700StencilOpSeparate;
1794
1795 /* Viewport related */
1796 functions->Viewport = r700Viewport;
1797 functions->DepthRange = r700DepthRange;
1798 functions->PointSize = r700PointSize;
1799 functions->LineWidth = r700LineWidth;
1800 functions->LineStipple = r700LineStipple;
1801
1802 functions->PolygonOffset = r700PolygonOffset;
1803 functions->PolygonMode = r700PolygonMode;
1804
1805 functions->RenderMode = r700RenderMode;
1806
1807 functions->ClipPlane = r700ClipPlane;
1808
1809 functions->Scissor = radeonScissor;
1810
1811 functions->DrawBuffer = radeonDrawBuffer;
1812 functions->ReadBuffer = radeonReadBuffer;
1813
1814 }
1815