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R6xx/r7xx: Fix texture perspective gradients issue
[mesa.git] / src / mesa / drivers / dri / r600 / r700_state.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/dd.h"
34 #include "main/simple_list.h"
35
36 #include "tnl/tnl.h"
37 #include "tnl/t_pipeline.h"
38 #include "tnl/t_vp_build.h"
39 #include "swrast/swrast.h"
40 #include "swrast_setup/swrast_setup.h"
41 #include "main/api_arrayelt.h"
42 #include "main/state.h"
43 #include "main/framebuffer.h"
44
45 #include "shader/prog_parameter.h"
46 #include "shader/prog_statevars.h"
47 #include "vbo/vbo.h"
48 #include "main/texformat.h"
49
50 #include "r600_context.h"
51
52 #include "r700_state.h"
53
54 #include "r700_fragprog.h"
55 #include "r700_vertprog.h"
56
57
58 void r700SetDefaultStates(context_t *context) //--------------------
59 {
60
61 }
62
63 void r700UpdateShaders (GLcontext * ctx) //----------------------------------
64 {
65 context_t *context = R700_CONTEXT(ctx);
66
67 GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
68 GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
69
70 struct r700_vertex_program *vp;
71 int i;
72
73 if (context->radeon.NewGLState)
74 {
75 context->radeon.NewGLState = 0;
76
77 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++)
78 {
79 /* mat states from state var not array for sw */
80 dummy_attrib[i].stride = 0;
81
82 temp_attrib[i] = TNL_CONTEXT(ctx)->vb.AttribPtr[i];
83 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = &(dummy_attrib[i]);
84 }
85
86 _tnl_UpdateFixedFunctionProgram(ctx);
87
88 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++)
89 {
90 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = temp_attrib[i];
91 }
92
93 r700SelectVertexShader(ctx);
94 vp = (struct r700_vertex_program *)ctx->VertexProgram._Current;
95
96 if (vp->translated == GL_FALSE)
97 {
98 // TODO
99 //fprintf(stderr, "Failing back to sw-tcl\n");
100 //hw_tcl_on = future_hw_tcl_on = 0;
101 //r300ResetHwState(rmesa);
102 //
103 r700UpdateStateParameters(ctx, _NEW_PROGRAM);
104 return;
105 }
106 }
107
108 r700UpdateStateParameters(ctx, _NEW_PROGRAM);
109 }
110
111 /*
112 * To correctly position primitives:
113 */
114 void r700UpdateViewportOffset(GLcontext * ctx) //------------------
115 {
116 return;
117 }
118
119 /**
120 * Tell the card where to render (offset, pitch).
121 * Effected by glDrawBuffer, etc
122 */
123 void r700UpdateDrawBuffer(GLcontext * ctx) /* TODO */ //---------------------
124 {
125 #if 0 /* to be enabled */
126 context_t *context = R700_CONTEXT(ctx);
127
128 switch (ctx->DrawBuffer->_ColorDrawBufferIndexes[0])
129 {
130 case BUFFER_FRONT_LEFT:
131 context->target.rt = context->screen->frontBuffer;
132 break;
133 case BUFFER_BACK_LEFT:
134 context->target.rt = context->screen->backBuffer;
135 break;
136 default:
137 memset (&context->target.rt, sizeof(context->target.rt), 0);
138 }
139 #endif /* to be enabled */
140 }
141
142 static void r700FetchStateParameter(GLcontext * ctx,
143 const gl_state_index state[STATE_LENGTH],
144 GLfloat * value)
145 {
146 context_t *context = R700_CONTEXT(ctx);
147
148 /* TODO */
149 }
150
151 void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state) //--------------------
152 {
153 struct r700_fragment_program *fp;
154 struct gl_program_parameter_list *paramList;
155 GLuint i;
156
157 if (!(new_state & (_NEW_BUFFERS | _NEW_PROGRAM)))
158 return;
159
160 fp = (struct r700_fragment_program *)ctx->FragmentProgram._Current;
161 if (!fp)
162 {
163 return;
164 }
165
166 paramList = fp->mesa_program.Base.Parameters;
167
168 if (!paramList)
169 {
170 return;
171 }
172
173 for (i = 0; i < paramList->NumParameters; i++)
174 {
175 if (paramList->Parameters[i].Type == PROGRAM_STATE_VAR)
176 {
177 r700FetchStateParameter(ctx,
178 paramList->Parameters[i].
179 StateIndexes,
180 paramList->ParameterValues[i]);
181 }
182 }
183 }
184
185 /**
186 * Called by Mesa after an internal state update.
187 */
188 static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //-------------------
189 {
190 context_t *context = R700_CONTEXT(ctx);
191
192 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
193
194 _swrast_InvalidateState(ctx, new_state);
195 _swsetup_InvalidateState(ctx, new_state);
196 _vbo_InvalidateState(ctx, new_state);
197 _tnl_InvalidateState(ctx, new_state);
198 _ae_invalidate_state(ctx, new_state);
199
200 if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL))
201 {
202 _mesa_update_framebuffer(ctx);
203 /* this updates the DrawBuffer's Width/Height if it's a FBO */
204 _mesa_update_draw_buffer_bounds(ctx);
205
206 r700UpdateDrawBuffer(ctx);
207 }
208
209 r700UpdateStateParameters(ctx, new_state);
210
211 if(GL_TRUE == r700->bEnablePerspective)
212 {
213 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
214 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
215 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
216
217 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
218
219 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
220 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
221 }
222 else
223 {
224 /* For orthogonal case. */
225 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
226 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
227
228 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
229
230 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
231 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
232 }
233
234 context->radeon.NewGLState |= new_state;
235 }
236
237 static void r700SetDepthState(GLcontext * ctx)
238 {
239 context_t *context = R700_CONTEXT(ctx);
240
241 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
242
243 if (ctx->Depth.Test)
244 {
245 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
246 if (ctx->Depth.Mask)
247 {
248 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
249 }
250 else
251 {
252 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
253 }
254
255 switch (ctx->Depth.Func)
256 {
257 case GL_NEVER:
258 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NEVER,
259 ZFUNC_shift, ZFUNC_mask);
260 break;
261 case GL_LESS:
262 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LESS,
263 ZFUNC_shift, ZFUNC_mask);
264 break;
265 case GL_EQUAL:
266 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_EQUAL,
267 ZFUNC_shift, ZFUNC_mask);
268 break;
269 case GL_LEQUAL:
270 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LEQUAL,
271 ZFUNC_shift, ZFUNC_mask);
272 break;
273 case GL_GREATER:
274 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GREATER,
275 ZFUNC_shift, ZFUNC_mask);
276 break;
277 case GL_NOTEQUAL:
278 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NOTEQUAL,
279 ZFUNC_shift, ZFUNC_mask);
280 break;
281 case GL_GEQUAL:
282 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GEQUAL,
283 ZFUNC_shift, ZFUNC_mask);
284 break;
285 case GL_ALWAYS:
286 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
287 ZFUNC_shift, ZFUNC_mask);
288 break;
289 default:
290 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
291 ZFUNC_shift, ZFUNC_mask);
292 break;
293 }
294 }
295 else
296 {
297 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
298 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
299 }
300 }
301
302 static void r700AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref) //---------------
303 {
304 }
305
306
307 static void r700BlendColor(GLcontext * ctx, const GLfloat cf[4]) //----------------
308 {
309 }
310
311 static void r700BlendEquationSeparate(GLcontext * ctx,
312 GLenum modeRGB, GLenum modeA) //-----------------
313 {
314 }
315
316 static void r700BlendFuncSeparate(GLcontext * ctx,
317 GLenum sfactorRGB, GLenum dfactorRGB,
318 GLenum sfactorA, GLenum dfactorA) //------------------------
319 {
320 }
321
322 static void r700UpdateCulling(GLcontext * ctx)
323 {
324 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
325
326 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
327 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
328 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
329
330 if (ctx->Polygon.CullFlag)
331 {
332 switch (ctx->Polygon.CullFaceMode)
333 {
334 case GL_FRONT:
335 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
336 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
337 break;
338 case GL_BACK:
339 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
340 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
341 break;
342 case GL_FRONT_AND_BACK:
343 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
344 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
345 break;
346 default:
347 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
348 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
349 break;
350 }
351 }
352
353 switch (ctx->Polygon.FrontFace)
354 {
355 case GL_CW:
356 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
357 break;
358 case GL_CCW:
359 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
360 break;
361 default:
362 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); /* default: ccw */
363 break;
364 }
365 }
366
367 static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //------------------
368 {
369 switch (cap)
370 {
371 case GL_TEXTURE_1D:
372 case GL_TEXTURE_2D:
373 case GL_TEXTURE_3D:
374 break;
375 case GL_FOG:
376 break;
377 case GL_ALPHA_TEST:
378 break;
379 case GL_COLOR_LOGIC_OP:
380 case GL_BLEND:
381 break;
382 case GL_CLIP_PLANE0:
383 case GL_CLIP_PLANE1:
384 case GL_CLIP_PLANE2:
385 case GL_CLIP_PLANE3:
386 case GL_CLIP_PLANE4:
387 case GL_CLIP_PLANE5:
388 break;
389 case GL_DEPTH_TEST:
390 r700SetDepthState(ctx);
391 break;
392 case GL_STENCIL_TEST:
393 break;
394 case GL_CULL_FACE:
395 r700UpdateCulling(ctx);
396 break;
397 case GL_POLYGON_OFFSET_POINT:
398 case GL_POLYGON_OFFSET_LINE:
399 case GL_POLYGON_OFFSET_FILL:
400 break;
401 default:
402 break;
403 }
404 }
405
406 /**
407 * Handle glColorMask()
408 */
409 static void r700ColorMask(GLcontext * ctx,
410 GLboolean r, GLboolean g, GLboolean b, GLboolean a) //------------------
411 {
412 }
413
414 /**
415 * Change the depth testing function.
416 *
417 * \note Mesa already filters redundant calls to this function.
418 */
419 static void r700DepthFunc(GLcontext * ctx, GLenum func) //--------------------
420 {
421 r700SetDepthState(ctx);
422 }
423
424 /**
425 * Enable/Disable depth writing.
426 *
427 * \note Mesa already filters redundant calls to this function.
428 */
429 static void r700DepthMask(GLcontext * ctx, GLboolean mask) //------------------
430 {
431 r700SetDepthState(ctx);
432 }
433
434 /**
435 * Change the culling mode.
436 *
437 * \note Mesa already filters redundant calls to this function.
438 */
439 static void r700CullFace(GLcontext * ctx, GLenum mode) //-----------------
440 {
441 r700UpdateCulling(ctx);
442 }
443
444 /* =============================================================
445 * Fog
446 */
447 static void r700Fogfv(GLcontext * ctx, GLenum pname, const GLfloat * param) //--------------
448 {
449 }
450
451 /**
452 * Change the polygon orientation.
453 *
454 * \note Mesa already filters redundant calls to this function.
455 */
456 static void r700FrontFace(GLcontext * ctx, GLenum mode) //------------------
457 {
458 r700UpdateCulling(ctx);
459 }
460
461 static void r700ShadeModel(GLcontext * ctx, GLenum mode) //--------------------
462 {
463 }
464
465 static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * param) //---------------
466 {
467 }
468
469 static void r700StencilFuncSeparate(GLcontext * ctx, GLenum face,
470 GLenum func, GLint ref, GLuint mask) //---------------------
471 {
472 }
473
474
475 static void r700StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) //--------------
476 {
477 }
478
479 static void r700StencilOpSeparate(GLcontext * ctx, GLenum face,
480 GLenum fail, GLenum zfail, GLenum zpass) //--------------------
481 {
482 }
483
484 static void r700Viewport(GLcontext * ctx,
485 GLint x,
486 GLint y,
487 GLsizei width,
488 GLsizei height) //--------------------
489 {
490 context_t *context = R700_CONTEXT(ctx);
491
492 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
493
494 __DRIdrawablePrivate *dPriv = context->radeon.dri.drawable;
495
496 GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
497 GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
498
499 const GLfloat *v = ctx->Viewport._WindowMap.m;
500
501 GLfloat sx, tx, sy, ty, sz, tz;
502 GLfloat scale;
503
504 switch (ctx->Visual.depthBits)
505 {
506 case 16:
507 scale = 1.0 / (GLfloat) 0xffff;
508 break;
509 case 24:
510 scale = 1.0 / (GLfloat) 0xffffff;
511 break;
512 default:
513 fprintf(stderr, "Error: Unsupported depth %d... exiting\n",
514 ctx->Visual.depthBits);
515 _mesa_exit(-1);
516 }
517
518 sx = v[MAT_SX];
519 tx = v[MAT_TX] + xoffset;
520 sy = -v[MAT_SY];
521 ty = (-v[MAT_TY]) + yoffset;
522 sz = v[MAT_SZ] * scale;
523 tz = v[MAT_TZ] * scale;
524
525 /* TODO : Need DMA flush as well. */
526
527 r700->PA_CL_VPORT_XSCALE.u32All = *((unsigned int*)(&sx));
528 r700->PA_CL_VPORT_XOFFSET.u32All = *((unsigned int*)(&tx));
529
530 r700->PA_CL_VPORT_YSCALE.u32All = *((unsigned int*)(&sy));
531 r700->PA_CL_VPORT_YOFFSET.u32All = *((unsigned int*)(&ty));
532
533 r700->PA_CL_VPORT_ZSCALE.u32All = *((unsigned int*)(&sz));
534 r700->PA_CL_VPORT_ZOFFSET.u32All = *((unsigned int*)(&tz));
535 }
536
537
538 static void r700DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) //-------------
539 {
540 }
541
542 static void r700PointSize(GLcontext * ctx, GLfloat size) //-------------------
543 {
544 }
545
546 static void r700LineWidth(GLcontext * ctx, GLfloat widthf) //---------------
547 {
548 }
549
550 static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) //--------------
551 {
552 }
553
554
555 static void r700PolygonMode(GLcontext * ctx, GLenum face, GLenum mode) //------------------
556 {
557 }
558
559 static void r700RenderMode(GLcontext * ctx, GLenum mode) //---------------------
560 {
561 }
562
563 static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq ) //-----------------
564 {
565 }
566
567 static void r700Scissor(GLcontext* ctx, GLint x, GLint y, GLsizei w, GLsizei h) //---------------
568 {
569 if (ctx->Scissor.Enabled)
570 {
571 /* We don't pipeline cliprect changes */
572 /* r700Flush(ctx); */
573
574 //__DRIdrawablePrivate *dPriv = radeon->dri.drawable;
575 //int x1 = dPriv->x + ctx->Scissor.X;
576 //int y1 = dPriv->y + dPriv->h - (ctx->Scissor.Y + ctx->Scissor.Height);
577
578 //radeon->state.scissor.rect.x1 = x1;
579 //radeon->state.scissor.rect.y1 = y1;
580 //radeon->state.scissor.rect.x2 = x1 + ctx->Scissor.Width;
581 //radeon->state.scissor.rect.y2 = y1 + ctx->Scissor.Height;
582 /* radeonRecalcScissorRects(radeon); */
583 }
584 }
585
586 void r700SetRenderTarget(context_t *context)
587 {
588 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
589
590 struct radeon_renderbuffer *rrb;
591 unsigned int nPitchInPixel;
592
593 /* screen/window/view */
594 SETfield(r700->CB_TARGET_MASK.u32All, 0xF, TARGET0_ENABLE_shift, TARGET0_ENABLE_mask);
595 SETfield(r700->CB_SHADER_MASK.u32All, 0xF, OUTPUT0_ENABLE_shift, OUTPUT0_ENABLE_mask);
596
597 /* screen */
598 r700->PA_SC_SCREEN_SCISSOR_TL.u32All = 0x0;
599
600 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->width,
601 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask);
602 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->height,
603 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask);
604
605 /* window */
606 SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
607 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, context->radeon.dri.drawable->x,
608 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask);
609 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, context->radeon.dri.drawable->y,
610 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask);
611
612 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, context->radeon.dri.drawable->x + context->radeon.dri.drawable->w,
613 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask);
614 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, context->radeon.dri.drawable->y + context->radeon.dri.drawable->h,
615 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask);
616
617 /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
618 r700->PA_SC_CLIPRECT_RULE.u32All = 0x0000FFFF;
619
620 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, context->radeon.dri.drawable->x,
621 PA_SC_CLIPRECT_0_TL__TL_X_shift, PA_SC_CLIPRECT_0_TL__TL_X_mask);
622 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, context->radeon.dri.drawable->y,
623 PA_SC_CLIPRECT_0_TL__TL_Y_shift, PA_SC_CLIPRECT_0_TL__TL_Y_mask);
624 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, context->radeon.dri.drawable->x + context->radeon.dri.drawable->w,
625 PA_SC_CLIPRECT_0_BR__BR_X_shift, PA_SC_CLIPRECT_0_BR__BR_X_mask);
626 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, context->radeon.dri.drawable->y + context->radeon.dri.drawable->h,
627 PA_SC_CLIPRECT_0_BR__BR_Y_shift, PA_SC_CLIPRECT_0_BR__BR_Y_mask);
628
629 r700->PA_SC_CLIPRECT_1_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
630 r700->PA_SC_CLIPRECT_1_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
631 r700->PA_SC_CLIPRECT_2_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
632 r700->PA_SC_CLIPRECT_2_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
633 r700->PA_SC_CLIPRECT_3_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
634 r700->PA_SC_CLIPRECT_3_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
635
636 /* edgerule for triangles, points, recs, lines */
637 r700->PA_SC_EDGERULE.u32All = 0x555AA96A;
638
639 /* more....2d clip */
640 SETbit(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
641 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, context->radeon.dri.drawable->x,
642 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask);
643 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, context->radeon.dri.drawable->y,
644 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask);
645 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, context->radeon.dri.drawable->x + context->radeon.dri.drawable->w,
646 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask);
647 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, context->radeon.dri.drawable->y + context->radeon.dri.drawable->h,
648 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask);
649
650 SETbit(r700->PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
651 SETfield(r700->PA_SC_VPORT_SCISSOR_0_TL.u32All, context->radeon.dri.drawable->x,
652 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask);
653 SETfield(r700->PA_SC_VPORT_SCISSOR_0_TL.u32All, context->radeon.dri.drawable->y,
654 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask);
655 SETfield(r700->PA_SC_VPORT_SCISSOR_0_BR.u32All, context->radeon.dri.drawable->x + context->radeon.dri.drawable->w,
656 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask);
657 SETfield(r700->PA_SC_VPORT_SCISSOR_0_BR.u32All, context->radeon.dri.drawable->y + context->radeon.dri.drawable->h,
658 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask);
659
660 SETbit(r700->PA_SC_VPORT_SCISSOR_1_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
661 SETfield(r700->PA_SC_VPORT_SCISSOR_1_TL.u32All, context->radeon.dri.drawable->x,
662 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask);
663 SETfield(r700->PA_SC_VPORT_SCISSOR_1_TL.u32All, context->radeon.dri.drawable->y,
664 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask);
665 SETfield(r700->PA_SC_VPORT_SCISSOR_1_BR.u32All, context->radeon.dri.drawable->x + context->radeon.dri.drawable->w,
666 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask);
667 SETfield(r700->PA_SC_VPORT_SCISSOR_1_BR.u32All, context->radeon.dri.drawable->y + context->radeon.dri.drawable->h,
668 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask);
669
670 /* setup viewport */
671 r700Viewport(GL_CONTEXT(context),
672 0,
673 0,
674 context->radeon.dri.drawable->w,
675 context->radeon.dri.drawable->h);
676
677 rrb = radeon_get_colorbuffer(&context->radeon);
678 if (!rrb || !rrb->bo) {
679 fprintf(stderr, "no rrb\n");
680 return;
681 }
682
683 /* color buffer */
684 r700->CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset;
685
686 nPitchInPixel = rrb->pitch/rrb->cpp;
687 SETfield(r700->CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1,
688 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
689 SETfield(r700->CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
690 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
691 r700->CB_COLOR0_BASE.u32All = 0;
692 SETfield(r700->CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
693 SETfield(r700->CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL,
694 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
695 if(4 == rrb->cpp)
696 {
697 SETfield(r700->CB_COLOR0_INFO.u32All, COLOR_8_8_8_8,
698 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
699 SETfield(r700->CB_COLOR0_INFO.u32All, SWAP_ALT, COMP_SWAP_shift, COMP_SWAP_mask);
700 }
701 else
702 {
703 SETfield(r700->CB_COLOR0_INFO.u32All, COLOR_5_6_5,
704 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
705 SETfield(r700->CB_COLOR0_INFO.u32All, SWAP_ALT_REV,
706 COMP_SWAP_shift, COMP_SWAP_mask);
707 }
708 SETbit(r700->CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
709 SETbit(r700->CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit);
710 SETfield(r700->CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
711
712 /* depth buf */
713 r700->DB_DEPTH_SIZE.u32All = 0;
714 r700->DB_DEPTH_BASE.u32All = 0;
715 r700->DB_DEPTH_INFO.u32All = 0;
716
717 r700->DB_DEPTH_CONTROL.u32All = 0;
718 r700->DB_DEPTH_CLEAR.u32All = 0x3F800000;
719 r700->DB_DEPTH_VIEW.u32All = 0;
720 r700->DB_RENDER_CONTROL.u32All = 0;
721 r700->DB_RENDER_OVERRIDE.u32All = 0;
722 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
723 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
724 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
725
726 rrb = radeon_get_depthbuffer(&context->radeon);
727 if (!rrb)
728 return;
729
730 nPitchInPixel = rrb->pitch/rrb->cpp;
731
732 SETfield(r700->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1,
733 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
734 SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
735 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */
736
737 if(4 == rrb->cpp)
738 {
739 switch (GL_CONTEXT(context)->Visual.depthBits)
740 {
741 case 16:
742 case 24:
743 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_8_24,
744 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
745 break;
746 default:
747 fprintf(stderr, "Error: Unsupported depth %d... exiting\n",
748 GL_CONTEXT(context)->Visual.depthBits);
749 _mesa_exit(-1);
750 }
751 }
752 else
753 {
754 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16,
755 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
756 }
757 SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_2D_TILED_THIN1,
758 DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask);
759 /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */
760 }
761
762 /**
763 * Calculate initial hardware state and register state functions.
764 * Assumes that the command buffer and state atoms have been
765 * initialized already.
766 */
767 void r700InitState(GLcontext * ctx) //-------------------
768 {
769 context_t *context = R700_CONTEXT(ctx);
770
771 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
772
773 /* Turn off vgt reuse */
774 r700->VGT_REUSE_OFF.u32All = 0;
775 SETbit(r700->VGT_REUSE_OFF.u32All, REUSE_OFF_bit);
776
777 /* Specify offsetting and clamp values for vertices */
778 r700->VGT_MAX_VTX_INDX.u32All = 0xFFFFFF;
779 r700->VGT_MIN_VTX_INDX.u32All = 0;
780 r700->VGT_INDX_OFFSET.u32All = 0;
781
782 /* Specify the number of instances */
783 r700->VGT_DMA_NUM_INSTANCES.u32All = 1;
784
785 /* not alpha blend */
786 CLEARfield(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_FUNC_mask);
787 CLEARbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
788
789 /* defualt shader connections. */
790 r700->SPI_VS_OUT_ID_0.u32All = 0x03020100;
791 r700->SPI_VS_OUT_ID_1.u32All = 0x07060504;
792
793 r700->SPI_PS_INPUT_CNTL_0.u32All = 0x00000800;
794 r700->SPI_PS_INPUT_CNTL_1.u32All = 0x00000801;
795 r700->SPI_PS_INPUT_CNTL_2.u32All = 0x00000802;
796
797 SETfield(r700->CB_COLOR_CONTROL.u32All, 0xCC, ROP3_shift, ROP3_mask);
798 CLEARbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit);
799 CLEARfield(r700->CB_BLEND0_CONTROL.u32All, COLOR_SRCBLEND_mask); /* no dst blend */
800 CLEARfield(r700->CB_BLEND0_CONTROL.u32All, ALPHA_SRCBLEND_mask); /* no dst blend */
801
802 r700->DB_SHADER_CONTROL.u32All = 0;
803 SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
804
805 /* Set up the culling control register */
806 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
807 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
808 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
809 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
810
811 /* Do scale XY and Z by 1/W0. */
812 r700->bEnablePerspective = GL_TRUE;
813 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
814 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
815 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
816
817 /* Enable viewport scaling for all three axis */
818 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_SCALE_ENA_bit);
819 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_OFFSET_ENA_bit);
820 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_SCALE_ENA_bit);
821 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_OFFSET_ENA_bit);
822 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_SCALE_ENA_bit);
823 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_OFFSET_ENA_bit);
824
825 /* Set up point sizes and min/max values */
826 SETfield(r700->PA_SU_POINT_SIZE.u32All, 0x8,
827 PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask);
828 SETfield(r700->PA_SU_POINT_SIZE.u32All, 0x8,
829 PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask);
830 CLEARfield(r700->PA_SU_POINT_MINMAX.u32All, MIN_SIZE_mask);
831 SETfield(r700->PA_SU_POINT_MINMAX.u32All, 0x8000, MAX_SIZE_shift, MAX_SIZE_mask);
832
833 /* Set up line control */
834 SETfield(r700->PA_SU_LINE_CNTL.u32All, 0x8,
835 PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
836
837 r700->PA_SC_LINE_CNTL.u32All = 0;
838 CLEARbit(r700->PA_SC_LINE_CNTL.u32All, EXPAND_LINE_WIDTH_bit);
839 SETbit(r700->PA_SC_LINE_CNTL.u32All, LAST_PIXEL_bit);
840
841 /* Set up vertex control */
842 r700->PA_SU_VTX_CNTL.u32All = 0;
843 CLEARfield(r700->PA_SU_VTX_CNTL.u32All, QUANT_MODE_mask);
844 SETbit(r700->PA_SU_VTX_CNTL.u32All, PIX_CENTER_bit);
845 SETfield(r700->PA_SU_VTX_CNTL.u32All, X_ROUND_TO_EVEN,
846 PA_SU_VTX_CNTL__ROUND_MODE_shift, PA_SU_VTX_CNTL__ROUND_MODE_mask);
847
848 /* to 1.0 = no guard band */
849 r700->PA_CL_GB_VERT_CLIP_ADJ.u32All = 0x3F800000; /* 1.0 */
850 r700->PA_CL_GB_VERT_DISC_ADJ.u32All = 0x3F800000;
851 r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All = 0x3F800000;
852 r700->PA_CL_GB_HORZ_DISC_ADJ.u32All = 0x3F800000;
853
854 /* Disble color compares */
855 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
856 CLRCMP_FCN_SRC_shift, CLRCMP_FCN_SRC_mask);
857 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
858 CLRCMP_FCN_DST_shift, CLRCMP_FCN_DST_mask);
859 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_SEL_SRC,
860 CLRCMP_FCN_SEL_shift, CLRCMP_FCN_SEL_mask);
861
862 /* Zero out source */
863 r700->CB_CLRCMP_SRC.u32All = 0x00000000;
864
865 /* Put a compare color in for error checking */
866 r700->CB_CLRCMP_DST.u32All = 0x000000FF;
867
868 /* Set up color compare mask */
869 r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF;
870
871 /* Enable all samples for multi-sample anti-aliasing */
872 r700->PA_SC_AA_MASK.u32All = 0xFFFFFFFF;
873 /* Turn off AA */
874 r700->PA_SC_AA_CONFIG.u32All = 0;
875
876 SETfield(r700->VGT_OUT_DEALLOC_CNTL.u32All, 16, DEALLOC_DIST_shift, DEALLOC_DIST_mask);
877 SETfield(r700->VGT_VERTEX_REUSE_BLOCK_CNTL.u32All, 14, VTX_REUSE_DEPTH_shift, VTX_REUSE_DEPTH_mask);
878
879 r700->SX_MISC.u32All = 0;
880
881 /* depth buf */
882 r700->DB_DEPTH_SIZE.u32All = 0;
883 r700->DB_DEPTH_BASE.u32All = 0;
884 r700->DB_DEPTH_INFO.u32All = 0;
885 r700->DB_DEPTH_CONTROL.u32All = 0;
886 r700->DB_DEPTH_CLEAR.u32All = 0x3F800000;
887 r700->DB_DEPTH_VIEW.u32All = 0;
888 r700->DB_RENDER_CONTROL.u32All = 0;
889 r700->DB_RENDER_OVERRIDE.u32All = 0;
890 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
891 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
892 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
893
894 /* color buffer */
895 r700->CB_COLOR0_SIZE.u32All = 0;
896 r700->CB_COLOR0_BASE.u32All = 0;
897 r700->CB_COLOR0_INFO.u32All = 0;
898 SETbit(r700->CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
899 SETbit(r700->CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit);
900 SETfield(r700->CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
901 r700->CB_COLOR0_VIEW.u32All = 0;
902 r700->CB_COLOR0_TILE.u32All = 0;
903 r700->CB_COLOR0_FRAG.u32All = 0;
904 r700->CB_COLOR0_MASK.u32All = 0;
905
906 r700->PA_SC_VPORT_ZMAX_0.u32All = 0x3F800000;
907 }
908
909 void r700InitStateFuncs(struct dd_function_table *functions) //-----------------
910 {
911 functions->UpdateState = r700InvalidateState;
912 functions->AlphaFunc = r700AlphaFunc;
913 functions->BlendColor = r700BlendColor;
914 functions->BlendEquationSeparate = r700BlendEquationSeparate;
915 functions->BlendFuncSeparate = r700BlendFuncSeparate;
916 functions->Enable = r700Enable;
917 functions->ColorMask = r700ColorMask;
918 functions->DepthFunc = r700DepthFunc;
919 functions->DepthMask = r700DepthMask;
920 functions->CullFace = r700CullFace;
921 functions->Fogfv = r700Fogfv;
922 functions->FrontFace = r700FrontFace;
923 functions->ShadeModel = r700ShadeModel;
924
925 /* ARB_point_parameters */
926 functions->PointParameterfv = r700PointParameter;
927
928 /* Stencil related */
929 functions->StencilFuncSeparate = r700StencilFuncSeparate;
930 functions->StencilMaskSeparate = r700StencilMaskSeparate;
931 functions->StencilOpSeparate = r700StencilOpSeparate;
932
933 /* Viewport related */
934 functions->Viewport = r700Viewport;
935 functions->DepthRange = r700DepthRange;
936 functions->PointSize = r700PointSize;
937 functions->LineWidth = r700LineWidth;
938
939 functions->PolygonOffset = r700PolygonOffset;
940 functions->PolygonMode = r700PolygonMode;
941
942 functions->RenderMode = r700RenderMode;
943
944 functions->ClipPlane = r700ClipPlane;
945
946 functions->Scissor = r700Scissor;
947 }
948