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r600: map 16 VS outputs
[mesa.git] / src / mesa / drivers / dri / r600 / r700_state.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/context.h"
34 #include "main/dd.h"
35 #include "main/simple_list.h"
36
37 #include "tnl/tnl.h"
38 #include "tnl/t_pipeline.h"
39 #include "tnl/t_vp_build.h"
40 #include "swrast/swrast.h"
41 #include "swrast_setup/swrast_setup.h"
42 #include "main/api_arrayelt.h"
43 #include "main/state.h"
44 #include "main/framebuffer.h"
45
46 #include "shader/prog_parameter.h"
47 #include "shader/prog_statevars.h"
48 #include "vbo/vbo.h"
49 #include "main/texformat.h"
50
51 #include "r600_context.h"
52
53 #include "r700_state.h"
54
55 #include "r700_fragprog.h"
56 #include "r700_vertprog.h"
57
58
59 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state);
60 static void r700UpdatePolygonMode(GLcontext * ctx);
61 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state);
62 static void r700SetStencilState(GLcontext * ctx, GLboolean state);
63 static void r700SetRenderTarget(context_t *context, int id);
64 static void r700SetDepthTarget(context_t *context);
65
66 void r700SetDefaultStates(context_t *context) //--------------------
67 {
68
69 }
70
71 void r700UpdateShaders (GLcontext * ctx) //----------------------------------
72 {
73 context_t *context = R700_CONTEXT(ctx);
74
75 GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
76 GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
77 int i;
78
79 if (ctx->FragmentProgram._Current) {
80 struct r700_fragment_program *fp = (struct r700_fragment_program *)
81 (ctx->FragmentProgram._Current);
82 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
83 {
84 fp->r700AsmCode.bR6xx = 1;
85 }
86
87 if(GL_FALSE == fp->translated)
88 {
89 if( GL_FALSE == r700TranslateFragmentShader(fp, &(fp->mesa_program)) )
90 {
91 //return GL_TRUE;
92 }
93 }
94 }
95
96 if (context->radeon.NewGLState)
97 {
98 struct r700_vertex_program *vp;
99 context->radeon.NewGLState = 0;
100
101 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++)
102 {
103 /* mat states from state var not array for sw */
104 dummy_attrib[i].stride = 0;
105
106 temp_attrib[i] = TNL_CONTEXT(ctx)->vb.AttribPtr[i];
107 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = &(dummy_attrib[i]);
108 }
109
110 _tnl_UpdateFixedFunctionProgram(ctx);
111
112 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++)
113 {
114 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = temp_attrib[i];
115 }
116
117 r700SelectVertexShader(ctx);
118 vp = (struct r700_vertex_program *)ctx->VertexProgram._Current;
119
120 if (vp->translated == GL_FALSE)
121 {
122 // TODO
123 //fprintf(stderr, "Failing back to sw-tcl\n");
124 //hw_tcl_on = future_hw_tcl_on = 0;
125 //r300ResetHwState(rmesa);
126 //
127 r700UpdateStateParameters(ctx, _NEW_PROGRAM);
128 return;
129 }
130 }
131
132 r700UpdateStateParameters(ctx, _NEW_PROGRAM);
133 }
134
135 /*
136 * To correctly position primitives:
137 */
138 void r700UpdateViewportOffset(GLcontext * ctx) //------------------
139 {
140 context_t *context = R700_CONTEXT(ctx);
141 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
142 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
143 GLfloat xoffset = (GLfloat) dPriv->x;
144 GLfloat yoffset = (GLfloat) dPriv->y + dPriv->h;
145 const GLfloat *v = ctx->Viewport._WindowMap.m;
146 int id = 0;
147
148 GLfloat tx = v[MAT_TX] + xoffset;
149 GLfloat ty = (-v[MAT_TY]) + yoffset;
150
151 if (r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All != tx ||
152 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All != ty) {
153 /* Note: this should also modify whatever data the context reset
154 * code uses...
155 */
156 R600_STATECHANGE(context, vpt);
157 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
158 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
159 }
160
161 radeonUpdateScissor(ctx);
162 }
163
164 /**
165 * Tell the card where to render (offset, pitch).
166 * Effected by glDrawBuffer, etc
167 */
168 void r700UpdateDrawBuffer(GLcontext * ctx) /* TODO */ //---------------------
169 {
170 context_t *context = R700_CONTEXT(ctx);
171
172 R600_STATECHANGE(context, cb_target);
173 R600_STATECHANGE(context, db_target);
174
175 r700SetRenderTarget(context, 0);
176 r700SetDepthTarget(context);
177 }
178
179 static void r700FetchStateParameter(GLcontext * ctx,
180 const gl_state_index state[STATE_LENGTH],
181 GLfloat * value)
182 {
183 /* TODO */
184 }
185
186 void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state) //--------------------
187 {
188 struct r700_fragment_program *fp;
189 struct gl_program_parameter_list *paramList;
190 GLuint i;
191
192 if (!(new_state & (_NEW_BUFFERS | _NEW_PROGRAM)))
193 return;
194
195 fp = (struct r700_fragment_program *)ctx->FragmentProgram._Current;
196 if (!fp)
197 {
198 return;
199 }
200
201 paramList = fp->mesa_program.Base.Parameters;
202
203 if (!paramList)
204 {
205 return;
206 }
207
208 for (i = 0; i < paramList->NumParameters; i++)
209 {
210 if (paramList->Parameters[i].Type == PROGRAM_STATE_VAR)
211 {
212 r700FetchStateParameter(ctx,
213 paramList->Parameters[i].
214 StateIndexes,
215 paramList->ParameterValues[i]);
216 }
217 }
218 }
219
220 /**
221 * Called by Mesa after an internal state update.
222 */
223 static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //-------------------
224 {
225 context_t *context = R700_CONTEXT(ctx);
226
227 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
228
229 _swrast_InvalidateState(ctx, new_state);
230 _swsetup_InvalidateState(ctx, new_state);
231 _vbo_InvalidateState(ctx, new_state);
232 _tnl_InvalidateState(ctx, new_state);
233 _ae_invalidate_state(ctx, new_state);
234
235 if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL))
236 {
237 _mesa_update_framebuffer(ctx);
238 /* this updates the DrawBuffer's Width/Height if it's a FBO */
239 _mesa_update_draw_buffer_bounds(ctx);
240
241 r700UpdateDrawBuffer(ctx);
242 }
243
244 r700UpdateStateParameters(ctx, new_state);
245
246 R600_STATECHANGE(context, cl);
247 R600_STATECHANGE(context, spi);
248
249 if(GL_TRUE == r700->bEnablePerspective)
250 {
251 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
252 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
253 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
254
255 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
256
257 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
258 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
259 }
260 else
261 {
262 /* For orthogonal case. */
263 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
264 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
265
266 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
267
268 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
269 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
270 }
271
272 context->radeon.NewGLState |= new_state;
273 }
274
275 static void r700SetDepthState(GLcontext * ctx)
276 {
277 context_t *context = R700_CONTEXT(ctx);
278 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
279
280 R600_STATECHANGE(context, db);
281
282 if (ctx->Depth.Test)
283 {
284 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
285 if (ctx->Depth.Mask)
286 {
287 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
288 }
289 else
290 {
291 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
292 }
293
294 switch (ctx->Depth.Func)
295 {
296 case GL_NEVER:
297 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NEVER,
298 ZFUNC_shift, ZFUNC_mask);
299 break;
300 case GL_LESS:
301 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LESS,
302 ZFUNC_shift, ZFUNC_mask);
303 break;
304 case GL_EQUAL:
305 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_EQUAL,
306 ZFUNC_shift, ZFUNC_mask);
307 break;
308 case GL_LEQUAL:
309 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LEQUAL,
310 ZFUNC_shift, ZFUNC_mask);
311 break;
312 case GL_GREATER:
313 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GREATER,
314 ZFUNC_shift, ZFUNC_mask);
315 break;
316 case GL_NOTEQUAL:
317 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NOTEQUAL,
318 ZFUNC_shift, ZFUNC_mask);
319 break;
320 case GL_GEQUAL:
321 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GEQUAL,
322 ZFUNC_shift, ZFUNC_mask);
323 break;
324 case GL_ALWAYS:
325 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
326 ZFUNC_shift, ZFUNC_mask);
327 break;
328 default:
329 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
330 ZFUNC_shift, ZFUNC_mask);
331 break;
332 }
333 }
334 else
335 {
336 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
337 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
338 }
339 }
340
341 static void r700SetAlphaState(GLcontext * ctx)
342 {
343 context_t *context = R700_CONTEXT(ctx);
344 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
345 uint32_t alpha_func = REF_ALWAYS;
346 GLboolean really_enabled = ctx->Color.AlphaEnabled;
347
348 R600_STATECHANGE(context, sx);
349
350 switch (ctx->Color.AlphaFunc) {
351 case GL_NEVER:
352 alpha_func = REF_NEVER;
353 break;
354 case GL_LESS:
355 alpha_func = REF_LESS;
356 break;
357 case GL_EQUAL:
358 alpha_func = REF_EQUAL;
359 break;
360 case GL_LEQUAL:
361 alpha_func = REF_LEQUAL;
362 break;
363 case GL_GREATER:
364 alpha_func = REF_GREATER;
365 break;
366 case GL_NOTEQUAL:
367 alpha_func = REF_NOTEQUAL;
368 break;
369 case GL_GEQUAL:
370 alpha_func = REF_GEQUAL;
371 break;
372 case GL_ALWAYS:
373 /*alpha_func = REF_ALWAYS; */
374 really_enabled = GL_FALSE;
375 break;
376 }
377
378 if (really_enabled) {
379 SETfield(r700->SX_ALPHA_TEST_CONTROL.u32All, alpha_func,
380 ALPHA_FUNC_shift, ALPHA_FUNC_mask);
381 SETbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
382 r700->SX_ALPHA_REF.f32All = ctx->Color.AlphaRef;
383 } else {
384 CLEARbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
385 }
386
387 }
388
389 static void r700AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref) //---------------
390 {
391 (void)func;
392 (void)ref;
393 r700SetAlphaState(ctx);
394 }
395
396
397 static void r700BlendColor(GLcontext * ctx, const GLfloat cf[4]) //----------------
398 {
399 context_t *context = R700_CONTEXT(ctx);
400 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
401
402 R600_STATECHANGE(context, blnd_clr);
403
404 r700->CB_BLEND_RED.f32All = cf[0];
405 r700->CB_BLEND_GREEN.f32All = cf[1];
406 r700->CB_BLEND_BLUE.f32All = cf[2];
407 r700->CB_BLEND_ALPHA.f32All = cf[3];
408 }
409
410 static int blend_factor(GLenum factor, GLboolean is_src)
411 {
412 switch (factor) {
413 case GL_ZERO:
414 return BLEND_ZERO;
415 break;
416 case GL_ONE:
417 return BLEND_ONE;
418 break;
419 case GL_DST_COLOR:
420 return BLEND_DST_COLOR;
421 break;
422 case GL_ONE_MINUS_DST_COLOR:
423 return BLEND_ONE_MINUS_DST_COLOR;
424 break;
425 case GL_SRC_COLOR:
426 return BLEND_SRC_COLOR;
427 break;
428 case GL_ONE_MINUS_SRC_COLOR:
429 return BLEND_ONE_MINUS_SRC_COLOR;
430 break;
431 case GL_SRC_ALPHA:
432 return BLEND_SRC_ALPHA;
433 break;
434 case GL_ONE_MINUS_SRC_ALPHA:
435 return BLEND_ONE_MINUS_SRC_ALPHA;
436 break;
437 case GL_DST_ALPHA:
438 return BLEND_DST_ALPHA;
439 break;
440 case GL_ONE_MINUS_DST_ALPHA:
441 return BLEND_ONE_MINUS_DST_ALPHA;
442 break;
443 case GL_SRC_ALPHA_SATURATE:
444 return (is_src) ? BLEND_SRC_ALPHA_SATURATE : BLEND_ZERO;
445 break;
446 case GL_CONSTANT_COLOR:
447 return BLEND_CONSTANT_COLOR;
448 break;
449 case GL_ONE_MINUS_CONSTANT_COLOR:
450 return BLEND_ONE_MINUS_CONSTANT_COLOR;
451 break;
452 case GL_CONSTANT_ALPHA:
453 return BLEND_CONSTANT_ALPHA;
454 break;
455 case GL_ONE_MINUS_CONSTANT_ALPHA:
456 return BLEND_ONE_MINUS_CONSTANT_ALPHA;
457 break;
458 default:
459 fprintf(stderr, "unknown blend factor %x\n", factor);
460 return (is_src) ? BLEND_ONE : BLEND_ZERO;
461 break;
462 }
463 }
464
465 static void r700SetBlendState(GLcontext * ctx)
466 {
467 context_t *context = R700_CONTEXT(ctx);
468 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
469 int id = 0;
470 uint32_t blend_reg = 0, eqn, eqnA;
471
472 R600_STATECHANGE(context, blnd);
473
474 if (RGBA_LOGICOP_ENABLED(ctx) || !ctx->Color.BlendEnabled) {
475 SETfield(blend_reg,
476 BLEND_ONE, COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
477 SETfield(blend_reg,
478 BLEND_ZERO, COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
479 SETfield(blend_reg,
480 COMB_DST_PLUS_SRC, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
481 SETfield(blend_reg,
482 BLEND_ONE, ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
483 SETfield(blend_reg,
484 BLEND_ZERO, ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
485 SETfield(blend_reg,
486 COMB_DST_PLUS_SRC, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
487 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
488 r700->CB_BLEND_CONTROL.u32All = blend_reg;
489 else
490 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
491 return;
492 }
493
494 SETfield(blend_reg,
495 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
496 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
497 SETfield(blend_reg,
498 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
499 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
500
501 switch (ctx->Color.BlendEquationRGB) {
502 case GL_FUNC_ADD:
503 eqn = COMB_DST_PLUS_SRC;
504 break;
505 case GL_FUNC_SUBTRACT:
506 eqn = COMB_SRC_MINUS_DST;
507 break;
508 case GL_FUNC_REVERSE_SUBTRACT:
509 eqn = COMB_DST_MINUS_SRC;
510 break;
511 case GL_MIN:
512 eqn = COMB_MIN_DST_SRC;
513 SETfield(blend_reg,
514 BLEND_ONE,
515 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
516 SETfield(blend_reg,
517 BLEND_ONE,
518 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
519 break;
520 case GL_MAX:
521 eqn = COMB_MAX_DST_SRC;
522 SETfield(blend_reg,
523 BLEND_ONE,
524 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
525 SETfield(blend_reg,
526 BLEND_ONE,
527 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
528 break;
529
530 default:
531 fprintf(stderr,
532 "[%s:%u] Invalid RGB blend equation (0x%04x).\n",
533 __FUNCTION__, __LINE__, ctx->Color.BlendEquationRGB);
534 return;
535 }
536 SETfield(blend_reg,
537 eqn, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
538
539 SETfield(blend_reg,
540 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
541 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
542 SETfield(blend_reg,
543 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
544 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
545
546 switch (ctx->Color.BlendEquationA) {
547 case GL_FUNC_ADD:
548 eqnA = COMB_DST_PLUS_SRC;
549 break;
550 case GL_FUNC_SUBTRACT:
551 eqnA = COMB_SRC_MINUS_DST;
552 break;
553 case GL_FUNC_REVERSE_SUBTRACT:
554 eqnA = COMB_DST_MINUS_SRC;
555 break;
556 case GL_MIN:
557 eqnA = COMB_MIN_DST_SRC;
558 SETfield(blend_reg,
559 BLEND_ONE,
560 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
561 SETfield(blend_reg,
562 BLEND_ONE,
563 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
564 break;
565 case GL_MAX:
566 eqnA = COMB_MAX_DST_SRC;
567 SETfield(blend_reg,
568 BLEND_ONE,
569 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
570 SETfield(blend_reg,
571 BLEND_ONE,
572 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
573 break;
574 default:
575 fprintf(stderr,
576 "[%s:%u] Invalid A blend equation (0x%04x).\n",
577 __FUNCTION__, __LINE__, ctx->Color.BlendEquationA);
578 return;
579 }
580
581 SETfield(blend_reg,
582 eqnA, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
583
584 SETbit(blend_reg, SEPARATE_ALPHA_BLEND_bit);
585
586 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
587 r700->CB_BLEND_CONTROL.u32All = blend_reg;
588 else {
589 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
590 SETbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit);
591 }
592 SETfield(r700->CB_COLOR_CONTROL.u32All, (1 << id),
593 TARGET_BLEND_ENABLE_shift, TARGET_BLEND_ENABLE_mask);
594
595 }
596
597 static void r700BlendEquationSeparate(GLcontext * ctx,
598 GLenum modeRGB, GLenum modeA) //-----------------
599 {
600 r700SetBlendState(ctx);
601 }
602
603 static void r700BlendFuncSeparate(GLcontext * ctx,
604 GLenum sfactorRGB, GLenum dfactorRGB,
605 GLenum sfactorA, GLenum dfactorA) //------------------------
606 {
607 r700SetBlendState(ctx);
608 }
609
610 /**
611 * Translate LogicOp enums into hardware representation.
612 */
613 static GLuint translate_logicop(GLenum logicop)
614 {
615 switch (logicop) {
616 case GL_CLEAR:
617 return 0x00;
618 case GL_SET:
619 return 0xff;
620 case GL_COPY:
621 return 0xcc;
622 case GL_COPY_INVERTED:
623 return 0x33;
624 case GL_NOOP:
625 return 0xaa;
626 case GL_INVERT:
627 return 0x55;
628 case GL_AND:
629 return 0x88;
630 case GL_NAND:
631 return 0x77;
632 case GL_OR:
633 return 0xee;
634 case GL_NOR:
635 return 0x11;
636 case GL_XOR:
637 return 0x66;
638 case GL_EQUIV:
639 return 0xaa;
640 case GL_AND_REVERSE:
641 return 0x44;
642 case GL_AND_INVERTED:
643 return 0x22;
644 case GL_OR_REVERSE:
645 return 0xdd;
646 case GL_OR_INVERTED:
647 return 0xbb;
648 default:
649 fprintf(stderr, "unknown blend logic operation %x\n", logicop);
650 return 0xcc;
651 }
652 }
653
654 /**
655 * Used internally to update the r300->hw hardware state to match the
656 * current OpenGL state.
657 */
658 static void r700SetLogicOpState(GLcontext *ctx)
659 {
660 context_t *context = R700_CONTEXT(ctx);
661 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
662
663 R600_STATECHANGE(context, blnd);
664
665 if (RGBA_LOGICOP_ENABLED(ctx))
666 SETfield(r700->CB_COLOR_CONTROL.u32All,
667 translate_logicop(ctx->Color.LogicOp), ROP3_shift, ROP3_mask);
668 else
669 SETfield(r700->CB_COLOR_CONTROL.u32All, 0xCC, ROP3_shift, ROP3_mask);
670 }
671
672 /**
673 * Called by Mesa when an application program changes the LogicOp state
674 * via glLogicOp.
675 */
676 static void r700LogicOpcode(GLcontext *ctx, GLenum logicop)
677 {
678 if (RGBA_LOGICOP_ENABLED(ctx))
679 r700SetLogicOpState(ctx);
680 }
681
682 static void r700UpdateCulling(GLcontext * ctx)
683 {
684 context_t *context = R700_CONTEXT(ctx);
685 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
686
687 R600_STATECHANGE(context, su);
688
689 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
690 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
691 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
692
693 if (ctx->Polygon.CullFlag)
694 {
695 switch (ctx->Polygon.CullFaceMode)
696 {
697 case GL_FRONT:
698 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
699 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
700 break;
701 case GL_BACK:
702 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
703 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
704 break;
705 case GL_FRONT_AND_BACK:
706 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
707 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
708 break;
709 default:
710 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
711 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
712 break;
713 }
714 }
715
716 switch (ctx->Polygon.FrontFace)
717 {
718 case GL_CW:
719 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
720 break;
721 case GL_CCW:
722 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
723 break;
724 default:
725 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); /* default: ccw */
726 break;
727 }
728 }
729
730 static void r700UpdateLineStipple(GLcontext * ctx)
731 {
732 context_t *context = R700_CONTEXT(ctx);
733 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
734
735 R600_STATECHANGE(context, sc);
736
737 if (ctx->Line.StippleFlag)
738 {
739 SETbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
740 }
741 else
742 {
743 CLEARbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
744 }
745 }
746
747 static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //------------------
748 {
749 context_t *context = R700_CONTEXT(ctx);
750
751 switch (cap) {
752 case GL_TEXTURE_1D:
753 case GL_TEXTURE_2D:
754 case GL_TEXTURE_3D:
755 /* empty */
756 break;
757 case GL_FOG:
758 /* empty */
759 break;
760 case GL_ALPHA_TEST:
761 r700SetAlphaState(ctx);
762 break;
763 case GL_COLOR_LOGIC_OP:
764 r700SetLogicOpState(ctx);
765 /* fall-through, because logic op overrides blending */
766 case GL_BLEND:
767 r700SetBlendState(ctx);
768 break;
769 case GL_CLIP_PLANE0:
770 case GL_CLIP_PLANE1:
771 case GL_CLIP_PLANE2:
772 case GL_CLIP_PLANE3:
773 case GL_CLIP_PLANE4:
774 case GL_CLIP_PLANE5:
775 r700SetClipPlaneState(ctx, cap, state);
776 break;
777 case GL_DEPTH_TEST:
778 r700SetDepthState(ctx);
779 break;
780 case GL_STENCIL_TEST:
781 r700SetStencilState(ctx, state);
782 break;
783 case GL_CULL_FACE:
784 r700UpdateCulling(ctx);
785 break;
786 case GL_POLYGON_OFFSET_POINT:
787 case GL_POLYGON_OFFSET_LINE:
788 case GL_POLYGON_OFFSET_FILL:
789 r700SetPolygonOffsetState(ctx, state);
790 break;
791 case GL_SCISSOR_TEST:
792 radeon_firevertices(&context->radeon);
793 context->radeon.state.scissor.enabled = state;
794 radeonUpdateScissor(ctx);
795 break;
796 case GL_LINE_STIPPLE:
797 r700UpdateLineStipple(ctx);
798 break;
799 default:
800 break;
801 }
802
803 }
804
805 /**
806 * Handle glColorMask()
807 */
808 static void r700ColorMask(GLcontext * ctx,
809 GLboolean r, GLboolean g, GLboolean b, GLboolean a) //------------------
810 {
811 context_t *context = R700_CONTEXT(ctx);
812 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
813 unsigned int mask = ((r ? 1 : 0) |
814 (g ? 2 : 0) |
815 (b ? 4 : 0) |
816 (a ? 8 : 0));
817
818 if (mask != r700->CB_SHADER_MASK.u32All) {
819 R600_STATECHANGE(context, cb);
820 SETfield(r700->CB_SHADER_MASK.u32All, mask, OUTPUT0_ENABLE_shift, OUTPUT0_ENABLE_mask);
821 }
822 }
823
824 /**
825 * Change the depth testing function.
826 *
827 * \note Mesa already filters redundant calls to this function.
828 */
829 static void r700DepthFunc(GLcontext * ctx, GLenum func) //--------------------
830 {
831 r700SetDepthState(ctx);
832 }
833
834 /**
835 * Enable/Disable depth writing.
836 *
837 * \note Mesa already filters redundant calls to this function.
838 */
839 static void r700DepthMask(GLcontext * ctx, GLboolean mask) //------------------
840 {
841 r700SetDepthState(ctx);
842 }
843
844 /**
845 * Change the culling mode.
846 *
847 * \note Mesa already filters redundant calls to this function.
848 */
849 static void r700CullFace(GLcontext * ctx, GLenum mode) //-----------------
850 {
851 r700UpdateCulling(ctx);
852 }
853
854 /* =============================================================
855 * Fog
856 */
857 static void r700Fogfv(GLcontext * ctx, GLenum pname, const GLfloat * param) //--------------
858 {
859 }
860
861 /**
862 * Change the polygon orientation.
863 *
864 * \note Mesa already filters redundant calls to this function.
865 */
866 static void r700FrontFace(GLcontext * ctx, GLenum mode) //------------------
867 {
868 r700UpdateCulling(ctx);
869 r700UpdatePolygonMode(ctx);
870 }
871
872 static void r700ShadeModel(GLcontext * ctx, GLenum mode) //--------------------
873 {
874 context_t *context = R700_CONTEXT(ctx);
875 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
876
877 R600_STATECHANGE(context, spi);
878
879 /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */
880 switch (mode) {
881 case GL_FLAT:
882 SETbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
883 break;
884 case GL_SMOOTH:
885 CLEARbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
886 break;
887 default:
888 return;
889 }
890 }
891
892 /* =============================================================
893 * Point state
894 */
895 static void r700PointSize(GLcontext * ctx, GLfloat size)
896 {
897 context_t *context = R700_CONTEXT(ctx);
898 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
899
900 R600_STATECHANGE(context, su);
901
902 /* We need to clamp to user defined range here, because
903 * the HW clamping happens only for per vertex point size. */
904 size = CLAMP(size, ctx->Point.MinSize, ctx->Point.MaxSize);
905
906 /* same size limits for AA, non-AA points */
907 size = CLAMP(size, ctx->Const.MinPointSize, ctx->Const.MaxPointSize);
908
909 /* format is 12.4 fixed point */
910 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 16),
911 PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask);
912 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 16),
913 PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask);
914
915 }
916
917 static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * param) //---------------
918 {
919 context_t *context = R700_CONTEXT(ctx);
920 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
921
922 R600_STATECHANGE(context, su);
923
924 /* format is 12.4 fixed point */
925 switch (pname) {
926 case GL_POINT_SIZE_MIN:
927 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MinSize * 16.0),
928 MIN_SIZE_shift, MIN_SIZE_mask);
929 break;
930 case GL_POINT_SIZE_MAX:
931 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MaxSize * 16.0),
932 MAX_SIZE_shift, MAX_SIZE_mask);
933 break;
934 case GL_POINT_DISTANCE_ATTENUATION:
935 break;
936 case GL_POINT_FADE_THRESHOLD_SIZE:
937 break;
938 default:
939 break;
940 }
941 }
942
943 static int translate_stencil_func(int func)
944 {
945 switch (func) {
946 case GL_NEVER:
947 return REF_NEVER;
948 case GL_LESS:
949 return REF_LESS;
950 case GL_EQUAL:
951 return REF_EQUAL;
952 case GL_LEQUAL:
953 return REF_LEQUAL;
954 case GL_GREATER:
955 return REF_GREATER;
956 case GL_NOTEQUAL:
957 return REF_NOTEQUAL;
958 case GL_GEQUAL:
959 return REF_GEQUAL;
960 case GL_ALWAYS:
961 return REF_ALWAYS;
962 }
963 return 0;
964 }
965
966 static int translate_stencil_op(int op)
967 {
968 switch (op) {
969 case GL_KEEP:
970 return STENCIL_KEEP;
971 case GL_ZERO:
972 return STENCIL_ZERO;
973 case GL_REPLACE:
974 return STENCIL_REPLACE;
975 case GL_INCR:
976 return STENCIL_INCR_CLAMP;
977 case GL_DECR:
978 return STENCIL_DECR_CLAMP;
979 case GL_INCR_WRAP_EXT:
980 return STENCIL_INCR_WRAP;
981 case GL_DECR_WRAP_EXT:
982 return STENCIL_DECR_WRAP;
983 case GL_INVERT:
984 return STENCIL_INVERT;
985 default:
986 WARN_ONCE("Do not know how to translate stencil op");
987 return STENCIL_KEEP;
988 }
989 return 0;
990 }
991
992 static void r700SetStencilState(GLcontext * ctx, GLboolean state)
993 {
994 context_t *context = R700_CONTEXT(ctx);
995 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
996 GLboolean hw_stencil = GL_FALSE;
997
998 //fixme
999 //r300CatchStencilFallback(ctx);
1000
1001 if (ctx->DrawBuffer) {
1002 struct radeon_renderbuffer *rrbStencil
1003 = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
1004 hw_stencil = (rrbStencil && rrbStencil->bo);
1005 }
1006
1007 if (hw_stencil) {
1008 R600_STATECHANGE(context, db);
1009 if (state)
1010 SETbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
1011 else
1012 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
1013 }
1014 }
1015
1016 static void r700StencilFuncSeparate(GLcontext * ctx, GLenum face,
1017 GLenum func, GLint ref, GLuint mask) //---------------------
1018 {
1019 context_t *context = R700_CONTEXT(ctx);
1020 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1021 const unsigned back = ctx->Stencil._BackFace;
1022
1023 //fixme
1024 //r300CatchStencilFallback(ctx);
1025
1026 R600_STATECHANGE(context, stencil);
1027
1028 //front
1029 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.Ref[0],
1030 STENCILREF_shift, STENCILREF_mask);
1031 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.ValueMask[0],
1032 STENCILMASK_shift, STENCILMASK_mask);
1033
1034 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[0]),
1035 STENCILFUNC_shift, STENCILFUNC_mask);
1036
1037 //back
1038 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.Ref[back],
1039 STENCILREF_BF_shift, STENCILREF_BF_mask);
1040 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.ValueMask[back],
1041 STENCILMASK_BF_shift, STENCILMASK_BF_mask);
1042
1043 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[back]),
1044 STENCILFUNC_BF_shift, STENCILFUNC_BF_mask);
1045
1046 }
1047
1048 static void r700StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) //--------------
1049 {
1050 context_t *context = R700_CONTEXT(ctx);
1051 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1052 const unsigned back = ctx->Stencil._BackFace;
1053
1054 //fixme
1055 //r300CatchStencilFallback(ctx);
1056
1057 R600_STATECHANGE(context, stencil);
1058
1059 // front
1060 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.WriteMask[0],
1061 STENCILWRITEMASK_shift, STENCILWRITEMASK_mask);
1062
1063 // back
1064 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.WriteMask[back],
1065 STENCILWRITEMASK_BF_shift, STENCILWRITEMASK_BF_mask);
1066
1067 }
1068
1069 static void r700StencilOpSeparate(GLcontext * ctx, GLenum face,
1070 GLenum fail, GLenum zfail, GLenum zpass) //--------------------
1071 {
1072 context_t *context = R700_CONTEXT(ctx);
1073 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1074 const unsigned back = ctx->Stencil._BackFace;
1075
1076 //fixme
1077 //r300CatchStencilFallback(ctx);
1078
1079 R600_STATECHANGE(context, db);
1080
1081 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[0]),
1082 STENCILFAIL_shift, STENCILFAIL_mask);
1083 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[0]),
1084 STENCILZFAIL_shift, STENCILZFAIL_mask);
1085 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[0]),
1086 STENCILZPASS_shift, STENCILZPASS_mask);
1087
1088 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[back]),
1089 STENCILFAIL_BF_shift, STENCILFAIL_BF_mask);
1090 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[back]),
1091 STENCILZFAIL_BF_shift, STENCILZFAIL_BF_mask);
1092 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[back]),
1093 STENCILZPASS_BF_shift, STENCILZPASS_BF_mask);
1094 }
1095
1096 static void r700UpdateWindow(GLcontext * ctx, int id) //--------------------
1097 {
1098 context_t *context = R700_CONTEXT(ctx);
1099 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1100 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
1101 GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
1102 GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
1103 const GLfloat *v = ctx->Viewport._WindowMap.m;
1104 const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
1105 const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
1106 GLfloat y_scale, y_bias;
1107
1108 if (render_to_fbo) {
1109 y_scale = 1.0;
1110 y_bias = 0;
1111 } else {
1112 y_scale = -1.0;
1113 y_bias = yoffset;
1114 }
1115
1116 GLfloat sx = v[MAT_SX];
1117 GLfloat tx = v[MAT_TX] + xoffset;
1118 GLfloat sy = v[MAT_SY] * y_scale;
1119 GLfloat ty = (v[MAT_TY] * y_scale) + y_bias;
1120 GLfloat sz = v[MAT_SZ] * depthScale;
1121 GLfloat tz = v[MAT_TZ] * depthScale;
1122
1123 R600_STATECHANGE(context, vpt);
1124
1125 r700->viewport[id].PA_CL_VPORT_XSCALE.f32All = sx;
1126 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
1127
1128 r700->viewport[id].PA_CL_VPORT_YSCALE.f32All = sy;
1129 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
1130
1131 r700->viewport[id].PA_CL_VPORT_ZSCALE.f32All = sz;
1132 r700->viewport[id].PA_CL_VPORT_ZOFFSET.f32All = tz;
1133
1134 r700->viewport[id].enabled = GL_TRUE;
1135
1136 r700SetScissor(context);
1137 }
1138
1139
1140 static void r700Viewport(GLcontext * ctx,
1141 GLint x,
1142 GLint y,
1143 GLsizei width,
1144 GLsizei height) //--------------------
1145 {
1146 r700UpdateWindow(ctx, 0);
1147
1148 radeon_viewport(ctx, x, y, width, height);
1149 }
1150
1151 static void r700DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) //-------------
1152 {
1153 r700UpdateWindow(ctx, 0);
1154 }
1155
1156 static void r700LineWidth(GLcontext * ctx, GLfloat widthf) //---------------
1157 {
1158 context_t *context = R700_CONTEXT(ctx);
1159 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1160 uint32_t lineWidth = (uint32_t)((widthf * 0.5) * (1 << 4));
1161
1162 R600_STATECHANGE(context, su);
1163
1164 if (lineWidth > 0xFFFF)
1165 lineWidth = 0xFFFF;
1166 SETfield(r700->PA_SU_LINE_CNTL.u32All,(uint16_t)lineWidth,
1167 PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
1168 }
1169
1170 static void r700LineStipple(GLcontext *ctx, GLint factor, GLushort pattern)
1171 {
1172 context_t *context = R700_CONTEXT(ctx);
1173 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1174
1175 R600_STATECHANGE(context, sc);
1176
1177 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, pattern, LINE_PATTERN_shift, LINE_PATTERN_mask);
1178 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, (factor-1), REPEAT_COUNT_shift, REPEAT_COUNT_mask);
1179 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, 1, AUTO_RESET_CNTL_shift, AUTO_RESET_CNTL_mask);
1180 }
1181
1182 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state)
1183 {
1184 context_t *context = R700_CONTEXT(ctx);
1185 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1186
1187 R600_STATECHANGE(context, su);
1188
1189 if (state) {
1190 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1191 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1192 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1193 } else {
1194 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1195 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1196 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1197 }
1198 }
1199
1200 static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) //--------------
1201 {
1202 context_t *context = R700_CONTEXT(ctx);
1203 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1204 GLfloat constant = units;
1205
1206 switch (ctx->Visual.depthBits) {
1207 case 16:
1208 constant *= 4.0;
1209 break;
1210 case 24:
1211 constant *= 2.0;
1212 break;
1213 }
1214
1215 factor *= 12.0;
1216
1217 R600_STATECHANGE(context, poly);
1218
1219 r700->PA_SU_POLY_OFFSET_FRONT_SCALE.f32All = factor;
1220 r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.f32All = constant;
1221 r700->PA_SU_POLY_OFFSET_BACK_SCALE.f32All = factor;
1222 r700->PA_SU_POLY_OFFSET_BACK_OFFSET.f32All = constant;
1223 }
1224
1225 static void r700UpdatePolygonMode(GLcontext * ctx)
1226 {
1227 context_t *context = R700_CONTEXT(ctx);
1228 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1229
1230 R600_STATECHANGE(context, su);
1231
1232 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DISABLE_POLY_MODE, POLY_MODE_shift, POLY_MODE_mask);
1233
1234 /* Only do something if a polygon mode is wanted, default is GL_FILL */
1235 if (ctx->Polygon.FrontMode != GL_FILL ||
1236 ctx->Polygon.BackMode != GL_FILL) {
1237 GLenum f, b;
1238
1239 /* Handle GL_CW (clock wise and GL_CCW (counter clock wise)
1240 * correctly by selecting the correct front and back face
1241 */
1242 if (ctx->Polygon.FrontFace == GL_CCW) {
1243 f = ctx->Polygon.FrontMode;
1244 b = ctx->Polygon.BackMode;
1245 } else {
1246 f = ctx->Polygon.BackMode;
1247 b = ctx->Polygon.FrontMode;
1248 }
1249
1250 /* Enable polygon mode */
1251 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DUAL_MODE, POLY_MODE_shift, POLY_MODE_mask);
1252
1253 switch (f) {
1254 case GL_LINE:
1255 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1256 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1257 break;
1258 case GL_POINT:
1259 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1260 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1261 break;
1262 case GL_FILL:
1263 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1264 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1265 break;
1266 }
1267
1268 switch (b) {
1269 case GL_LINE:
1270 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1271 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1272 break;
1273 case GL_POINT:
1274 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1275 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1276 break;
1277 case GL_FILL:
1278 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1279 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1280 break;
1281 }
1282 }
1283 }
1284
1285 static void r700PolygonMode(GLcontext * ctx, GLenum face, GLenum mode) //------------------
1286 {
1287 (void)face;
1288 (void)mode;
1289
1290 r700UpdatePolygonMode(ctx);
1291 }
1292
1293 static void r700RenderMode(GLcontext * ctx, GLenum mode) //---------------------
1294 {
1295 }
1296
1297 static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
1298 {
1299 context_t *context = R700_CONTEXT(ctx);
1300 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1301 GLint p;
1302 GLint *ip;
1303
1304 p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
1305 ip = (GLint *)ctx->Transform._ClipUserPlane[p];
1306
1307 R600_STATECHANGE(context, ucp);
1308
1309 r700->ucp[p].PA_CL_UCP_0_X.u32All = ip[0];
1310 r700->ucp[p].PA_CL_UCP_0_Y.u32All = ip[1];
1311 r700->ucp[p].PA_CL_UCP_0_Z.u32All = ip[2];
1312 r700->ucp[p].PA_CL_UCP_0_W.u32All = ip[3];
1313 }
1314
1315 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state)
1316 {
1317 context_t *context = R700_CONTEXT(ctx);
1318 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1319 GLuint p;
1320
1321 p = cap - GL_CLIP_PLANE0;
1322
1323 R600_STATECHANGE(context, cl);
1324
1325 if (state) {
1326 r700->PA_CL_CLIP_CNTL.u32All |= (UCP_ENA_0_bit << p);
1327 r700->ucp[p].enabled = GL_TRUE;
1328 r700ClipPlane(ctx, cap, NULL);
1329 } else {
1330 r700->PA_CL_CLIP_CNTL.u32All &= ~(UCP_ENA_0_bit << p);
1331 r700->ucp[p].enabled = GL_FALSE;
1332 }
1333 }
1334
1335 void r700SetScissor(context_t *context) //---------------
1336 {
1337 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1338 unsigned x1, y1, x2, y2;
1339 int id = 0;
1340 struct radeon_renderbuffer *rrb;
1341
1342 rrb = radeon_get_colorbuffer(&context->radeon);
1343 if (!rrb || !rrb->bo) {
1344 return;
1345 }
1346 if (context->radeon.state.scissor.enabled) {
1347 x1 = context->radeon.state.scissor.rect.x1;
1348 y1 = context->radeon.state.scissor.rect.y1;
1349 x2 = context->radeon.state.scissor.rect.x2 - 1;
1350 y2 = context->radeon.state.scissor.rect.y2 - 1;
1351 } else {
1352 x1 = rrb->dPriv->x;
1353 y1 = rrb->dPriv->y;
1354 x2 = rrb->dPriv->x + rrb->dPriv->w;
1355 y2 = rrb->dPriv->y + rrb->dPriv->h;
1356 }
1357
1358 R600_STATECHANGE(context, scissor);
1359
1360 /* window */
1361 SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1362 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, x1,
1363 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask);
1364 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, y1,
1365 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask);
1366
1367 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, x2,
1368 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask);
1369 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, y2,
1370 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask);
1371
1372
1373 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, x1,
1374 PA_SC_CLIPRECT_0_TL__TL_X_shift, PA_SC_CLIPRECT_0_TL__TL_X_mask);
1375 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, y1,
1376 PA_SC_CLIPRECT_0_TL__TL_Y_shift, PA_SC_CLIPRECT_0_TL__TL_Y_mask);
1377 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, x2,
1378 PA_SC_CLIPRECT_0_BR__BR_X_shift, PA_SC_CLIPRECT_0_BR__BR_X_mask);
1379 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, y2,
1380 PA_SC_CLIPRECT_0_BR__BR_Y_shift, PA_SC_CLIPRECT_0_BR__BR_Y_mask);
1381
1382 r700->PA_SC_CLIPRECT_1_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1383 r700->PA_SC_CLIPRECT_1_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1384 r700->PA_SC_CLIPRECT_2_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1385 r700->PA_SC_CLIPRECT_2_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1386 r700->PA_SC_CLIPRECT_3_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1387 r700->PA_SC_CLIPRECT_3_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1388
1389 /* more....2d clip */
1390 SETbit(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1391 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, x1,
1392 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask);
1393 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, y1,
1394 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask);
1395 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, x2,
1396 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask);
1397 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, y2,
1398 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask);
1399
1400 SETbit(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1401 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, x1,
1402 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask);
1403 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, y1,
1404 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask);
1405 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, x2,
1406 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask);
1407 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, y2,
1408 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask);
1409
1410 r700->viewport[id].PA_SC_VPORT_ZMIN_0.u32All = 0;
1411 r700->viewport[id].PA_SC_VPORT_ZMAX_0.u32All = 0x3F800000;
1412 r700->viewport[id].enabled = GL_TRUE;
1413 }
1414
1415 static void r700SetRenderTarget(context_t *context, int id)
1416 {
1417 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1418
1419 struct radeon_renderbuffer *rrb;
1420 unsigned int nPitchInPixel;
1421
1422 rrb = radeon_get_colorbuffer(&context->radeon);
1423 if (!rrb || !rrb->bo) {
1424 return;
1425 }
1426
1427 R600_STATECHANGE(context, cb_target);
1428 R600_STATECHANGE(context, cb);
1429
1430 /* screen/window/view */
1431 SETfield(r700->CB_TARGET_MASK.u32All, 0xF, (4 * id), TARGET0_ENABLE_mask);
1432
1433 /* color buffer */
1434 r700->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset;
1435
1436 nPitchInPixel = rrb->pitch/rrb->cpp;
1437 SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1,
1438 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
1439 SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
1440 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
1441 r700->render_target[id].CB_COLOR0_BASE.u32All = 0;
1442 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
1443 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL,
1444 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
1445 if(4 == rrb->cpp)
1446 {
1447 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_8_8_8_8,
1448 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
1449 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT, COMP_SWAP_shift, COMP_SWAP_mask);
1450 }
1451 else
1452 {
1453 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_5_6_5,
1454 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
1455 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT_REV,
1456 COMP_SWAP_shift, COMP_SWAP_mask);
1457 }
1458 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
1459 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit);
1460 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
1461
1462 r700->render_target[id].enabled = GL_TRUE;
1463 }
1464
1465 static void r700SetDepthTarget(context_t *context)
1466 {
1467 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1468
1469 struct radeon_renderbuffer *rrb;
1470 unsigned int nPitchInPixel;
1471
1472 rrb = radeon_get_depthbuffer(&context->radeon);
1473 if (!rrb)
1474 return;
1475
1476 R600_STATECHANGE(context, db_target);
1477
1478 /* depth buf */
1479 r700->DB_DEPTH_SIZE.u32All = 0;
1480 r700->DB_DEPTH_BASE.u32All = 0;
1481 r700->DB_DEPTH_INFO.u32All = 0;
1482 r700->DB_DEPTH_VIEW.u32All = 0;
1483
1484 nPitchInPixel = rrb->pitch/rrb->cpp;
1485
1486 SETfield(r700->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1,
1487 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
1488 SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
1489 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */
1490
1491 if(4 == rrb->cpp)
1492 {
1493 switch (GL_CONTEXT(context)->Visual.depthBits)
1494 {
1495 case 16:
1496 case 24:
1497 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_8_24,
1498 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
1499 break;
1500 default:
1501 fprintf(stderr, "Error: Unsupported depth %d... exiting\n",
1502 GL_CONTEXT(context)->Visual.depthBits);
1503 _mesa_exit(-1);
1504 }
1505 }
1506 else
1507 {
1508 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16,
1509 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
1510 }
1511 SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_2D_TILED_THIN1,
1512 DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask);
1513 /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */
1514 }
1515
1516 static void r700InitSQConfig(GLcontext * ctx)
1517 {
1518 context_t *context = R700_CONTEXT(ctx);
1519 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1520 int ps_prio;
1521 int vs_prio;
1522 int gs_prio;
1523 int es_prio;
1524 int num_ps_gprs;
1525 int num_vs_gprs;
1526 int num_gs_gprs;
1527 int num_es_gprs;
1528 int num_temp_gprs;
1529 int num_ps_threads;
1530 int num_vs_threads;
1531 int num_gs_threads;
1532 int num_es_threads;
1533 int num_ps_stack_entries;
1534 int num_vs_stack_entries;
1535 int num_gs_stack_entries;
1536 int num_es_stack_entries;
1537
1538 R600_STATECHANGE(context, sq);
1539
1540 // SQ
1541 ps_prio = 0;
1542 vs_prio = 1;
1543 gs_prio = 2;
1544 es_prio = 3;
1545 switch (context->radeon.radeonScreen->chip_family) {
1546 case CHIP_FAMILY_R600:
1547 num_ps_gprs = 192;
1548 num_vs_gprs = 56;
1549 num_temp_gprs = 4;
1550 num_gs_gprs = 0;
1551 num_es_gprs = 0;
1552 num_ps_threads = 136;
1553 num_vs_threads = 48;
1554 num_gs_threads = 4;
1555 num_es_threads = 4;
1556 num_ps_stack_entries = 128;
1557 num_vs_stack_entries = 128;
1558 num_gs_stack_entries = 0;
1559 num_es_stack_entries = 0;
1560 break;
1561 case CHIP_FAMILY_RV630:
1562 case CHIP_FAMILY_RV635:
1563 num_ps_gprs = 84;
1564 num_vs_gprs = 36;
1565 num_temp_gprs = 4;
1566 num_gs_gprs = 0;
1567 num_es_gprs = 0;
1568 num_ps_threads = 144;
1569 num_vs_threads = 40;
1570 num_gs_threads = 4;
1571 num_es_threads = 4;
1572 num_ps_stack_entries = 40;
1573 num_vs_stack_entries = 40;
1574 num_gs_stack_entries = 32;
1575 num_es_stack_entries = 16;
1576 break;
1577 case CHIP_FAMILY_RV610:
1578 case CHIP_FAMILY_RV620:
1579 case CHIP_FAMILY_RS780:
1580 case CHIP_FAMILY_RS880:
1581 default:
1582 num_ps_gprs = 84;
1583 num_vs_gprs = 36;
1584 num_temp_gprs = 4;
1585 num_gs_gprs = 0;
1586 num_es_gprs = 0;
1587 num_ps_threads = 136;
1588 num_vs_threads = 48;
1589 num_gs_threads = 4;
1590 num_es_threads = 4;
1591 num_ps_stack_entries = 40;
1592 num_vs_stack_entries = 40;
1593 num_gs_stack_entries = 32;
1594 num_es_stack_entries = 16;
1595 break;
1596 case CHIP_FAMILY_RV670:
1597 num_ps_gprs = 144;
1598 num_vs_gprs = 40;
1599 num_temp_gprs = 4;
1600 num_gs_gprs = 0;
1601 num_es_gprs = 0;
1602 num_ps_threads = 136;
1603 num_vs_threads = 48;
1604 num_gs_threads = 4;
1605 num_es_threads = 4;
1606 num_ps_stack_entries = 40;
1607 num_vs_stack_entries = 40;
1608 num_gs_stack_entries = 32;
1609 num_es_stack_entries = 16;
1610 break;
1611 case CHIP_FAMILY_RV770:
1612 num_ps_gprs = 192;
1613 num_vs_gprs = 56;
1614 num_temp_gprs = 4;
1615 num_gs_gprs = 0;
1616 num_es_gprs = 0;
1617 num_ps_threads = 188;
1618 num_vs_threads = 60;
1619 num_gs_threads = 0;
1620 num_es_threads = 0;
1621 num_ps_stack_entries = 256;
1622 num_vs_stack_entries = 256;
1623 num_gs_stack_entries = 0;
1624 num_es_stack_entries = 0;
1625 break;
1626 case CHIP_FAMILY_RV730:
1627 case CHIP_FAMILY_RV740:
1628 num_ps_gprs = 84;
1629 num_vs_gprs = 36;
1630 num_temp_gprs = 4;
1631 num_gs_gprs = 0;
1632 num_es_gprs = 0;
1633 num_ps_threads = 188;
1634 num_vs_threads = 60;
1635 num_gs_threads = 0;
1636 num_es_threads = 0;
1637 num_ps_stack_entries = 128;
1638 num_vs_stack_entries = 128;
1639 num_gs_stack_entries = 0;
1640 num_es_stack_entries = 0;
1641 break;
1642 case CHIP_FAMILY_RV710:
1643 num_ps_gprs = 192;
1644 num_vs_gprs = 56;
1645 num_temp_gprs = 4;
1646 num_gs_gprs = 0;
1647 num_es_gprs = 0;
1648 num_ps_threads = 144;
1649 num_vs_threads = 48;
1650 num_gs_threads = 0;
1651 num_es_threads = 0;
1652 num_ps_stack_entries = 128;
1653 num_vs_stack_entries = 128;
1654 num_gs_stack_entries = 0;
1655 num_es_stack_entries = 0;
1656 break;
1657 }
1658
1659 r700->sq_config.SQ_CONFIG.u32All = 0;
1660 if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
1661 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
1662 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
1663 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) ||
1664 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
1665 CLEARbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1666 else
1667 SETbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1668 SETbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit);
1669 SETbit(r700->sq_config.SQ_CONFIG.u32All, ALU_INST_PREFER_VECTOR_bit);
1670 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, PS_PRIO_shift, PS_PRIO_mask);
1671 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, VS_PRIO_shift, VS_PRIO_mask);
1672 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, GS_PRIO_shift, GS_PRIO_mask);
1673 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, ES_PRIO_shift, ES_PRIO_mask);
1674
1675 r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All = 0;
1676 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_ps_gprs, NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
1677 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_vs_gprs, NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
1678 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_temp_gprs,
1679 NUM_CLAUSE_TEMP_GPRS_shift, NUM_CLAUSE_TEMP_GPRS_mask);
1680
1681 r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All = 0;
1682 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_gs_gprs, NUM_GS_GPRS_shift, NUM_GS_GPRS_mask);
1683 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_es_gprs, NUM_ES_GPRS_shift, NUM_ES_GPRS_mask);
1684
1685 r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All = 0;
1686 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_ps_threads,
1687 NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
1688 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_vs_threads,
1689 NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
1690 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_gs_threads,
1691 NUM_GS_THREADS_shift, NUM_GS_THREADS_mask);
1692 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_es_threads,
1693 NUM_ES_THREADS_shift, NUM_ES_THREADS_mask);
1694
1695 r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All = 0;
1696 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_ps_stack_entries,
1697 NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
1698 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_vs_stack_entries,
1699 NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
1700
1701 r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All = 0;
1702 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_gs_stack_entries,
1703 NUM_GS_STACK_ENTRIES_shift, NUM_GS_STACK_ENTRIES_mask);
1704 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_es_stack_entries,
1705 NUM_ES_STACK_ENTRIES_shift, NUM_ES_STACK_ENTRIES_mask);
1706
1707 }
1708
1709 /**
1710 * Calculate initial hardware state and register state functions.
1711 * Assumes that the command buffer and state atoms have been
1712 * initialized already.
1713 */
1714 void r700InitState(GLcontext * ctx) //-------------------
1715 {
1716 context_t *context = R700_CONTEXT(ctx);
1717 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1718
1719 radeon_firevertices(&context->radeon);
1720
1721 r700->TA_CNTL_AUX.u32All = 0;
1722 SETfield(r700->TA_CNTL_AUX.u32All, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask);
1723 r700->VC_ENHANCE.u32All = 0;
1724 r700->DB_WATERMARKS.u32All = 0;
1725 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_FREE_shift, DEPTH_FREE_mask);
1726 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_FLUSH_shift, DEPTH_FLUSH_mask);
1727 SETfield(r700->DB_WATERMARKS.u32All, 0, FORCE_SUMMARIZE_shift, FORCE_SUMMARIZE_mask);
1728 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_PENDING_FREE_shift, DEPTH_PENDING_FREE_mask);
1729 r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All = 0;
1730 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1731 SETfield(r700->TA_CNTL_AUX.u32All, 3, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1732 r700->DB_DEBUG.u32All = 0x82000000;
1733 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1734 } else {
1735 SETfield(r700->TA_CNTL_AUX.u32All, 2, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1736 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1737 SETbit(r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All, VS_PC_LIMIT_ENABLE_bit);
1738 }
1739
1740 /* Turn off vgt reuse */
1741 r700->VGT_REUSE_OFF.u32All = 0;
1742 SETbit(r700->VGT_REUSE_OFF.u32All, REUSE_OFF_bit);
1743
1744 /* Specify offsetting and clamp values for vertices */
1745 r700->VGT_MAX_VTX_INDX.u32All = 0xFFFFFF;
1746 r700->VGT_MIN_VTX_INDX.u32All = 0;
1747 r700->VGT_INDX_OFFSET.u32All = 0;
1748
1749 /* default shader connections. */
1750 r700->SPI_VS_OUT_ID_0.u32All = 0x03020100;
1751 r700->SPI_VS_OUT_ID_1.u32All = 0x07060504;
1752 r700->SPI_VS_OUT_ID_2.u32All = 0x0b0a0908;
1753 r700->SPI_VS_OUT_ID_3.u32All = 0x0f0e0d0c;
1754
1755 r700->SPI_THREAD_GROUPING.u32All = 0;
1756 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
1757 SETfield(r700->SPI_THREAD_GROUPING.u32All, 1, PS_GROUPING_shift, PS_GROUPING_mask);
1758
1759 /* screen */
1760 r700->PA_SC_SCREEN_SCISSOR_TL.u32All = 0x0;
1761
1762 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All,
1763 ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->width,
1764 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask);
1765 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All,
1766 ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->height,
1767 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask);
1768
1769 /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
1770 r700->PA_SC_CLIPRECT_RULE.u32All = 0;
1771 SETfield(r700->PA_SC_CLIPRECT_RULE.u32All, CLIP_RULE_mask, CLIP_RULE_shift, CLIP_RULE_mask);
1772
1773 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1774 r700->PA_SC_EDGERULE.u32All = 0;
1775 else
1776 r700->PA_SC_EDGERULE.u32All = 0xAAAAAAAA;
1777
1778 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1779 r700->PA_SC_MODE_CNTL.u32All = 0;
1780 SETbit(r700->PA_SC_MODE_CNTL.u32All, WALK_ORDER_ENABLE_bit);
1781 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1782 } else {
1783 r700->PA_SC_MODE_CNTL.u32All = 0x00500000;
1784 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_REZ_ENABLE_bit);
1785 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1786 }
1787
1788 /* Do scale XY and Z by 1/W0. */
1789 r700->bEnablePerspective = GL_TRUE;
1790 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
1791 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
1792 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
1793
1794 /* Enable viewport scaling for all three axis */
1795 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_SCALE_ENA_bit);
1796 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_OFFSET_ENA_bit);
1797 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_SCALE_ENA_bit);
1798 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_OFFSET_ENA_bit);
1799 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_SCALE_ENA_bit);
1800 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_OFFSET_ENA_bit);
1801
1802 /* GL uses last vtx for flat shading components */
1803 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
1804
1805 /* Set up vertex control */
1806 r700->PA_SU_VTX_CNTL.u32All = 0;
1807 CLEARfield(r700->PA_SU_VTX_CNTL.u32All, QUANT_MODE_mask);
1808 SETbit(r700->PA_SU_VTX_CNTL.u32All, PIX_CENTER_bit);
1809 SETfield(r700->PA_SU_VTX_CNTL.u32All, X_ROUND_TO_EVEN,
1810 PA_SU_VTX_CNTL__ROUND_MODE_shift, PA_SU_VTX_CNTL__ROUND_MODE_mask);
1811
1812 /* to 1.0 = no guard band */
1813 r700->PA_CL_GB_VERT_CLIP_ADJ.u32All = 0x3F800000; /* 1.0 */
1814 r700->PA_CL_GB_VERT_DISC_ADJ.u32All = 0x3F800000;
1815 r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All = 0x3F800000;
1816 r700->PA_CL_GB_HORZ_DISC_ADJ.u32All = 0x3F800000;
1817
1818 /* Enable all samples for multi-sample anti-aliasing */
1819 r700->PA_SC_AA_MASK.u32All = 0xFFFFFFFF;
1820 /* Turn off AA */
1821 r700->PA_SC_AA_CONFIG.u32All = 0;
1822
1823 r700->SX_MISC.u32All = 0;
1824
1825 r700InitSQConfig(ctx);
1826
1827 r700ColorMask(ctx,
1828 ctx->Color.ColorMask[RCOMP],
1829 ctx->Color.ColorMask[GCOMP],
1830 ctx->Color.ColorMask[BCOMP],
1831 ctx->Color.ColorMask[ACOMP]);
1832
1833 r700Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test);
1834 r700DepthMask(ctx, ctx->Depth.Mask);
1835 r700DepthFunc(ctx, ctx->Depth.Func);
1836 SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
1837
1838 r700->DB_DEPTH_CLEAR.u32All = 0x3F800000;
1839
1840 r700->DB_RENDER_CONTROL.u32All = 0;
1841 SETbit(r700->DB_RENDER_CONTROL.u32All, STENCIL_COMPRESS_DISABLE_bit);
1842 SETbit(r700->DB_RENDER_CONTROL.u32All, DEPTH_COMPRESS_DISABLE_bit);
1843 r700->DB_RENDER_OVERRIDE.u32All = 0;
1844 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1845 SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit);
1846 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
1847 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
1848 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
1849
1850 r700->DB_ALPHA_TO_MASK.u32All = 0;
1851 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask);
1852 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET1_shift, ALPHA_TO_MASK_OFFSET1_mask);
1853 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET2_shift, ALPHA_TO_MASK_OFFSET2_mask);
1854 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET3_shift, ALPHA_TO_MASK_OFFSET3_mask);
1855
1856 /* stencil */
1857 r700Enable(ctx, GL_STENCIL_TEST, ctx->Stencil._Enabled);
1858 r700StencilMaskSeparate(ctx, 0, ctx->Stencil.WriteMask[0]);
1859 r700StencilFuncSeparate(ctx, 0, ctx->Stencil.Function[0],
1860 ctx->Stencil.Ref[0], ctx->Stencil.ValueMask[0]);
1861 r700StencilOpSeparate(ctx, 0, ctx->Stencil.FailFunc[0],
1862 ctx->Stencil.ZFailFunc[0],
1863 ctx->Stencil.ZPassFunc[0]);
1864
1865 r700UpdateCulling(ctx);
1866
1867 r700SetBlendState(ctx);
1868 r700SetLogicOpState(ctx);
1869
1870 r700AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef);
1871 r700Enable(ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled);
1872
1873 r700PointSize(ctx, 1.0);
1874
1875 CLEARfield(r700->PA_SU_POINT_MINMAX.u32All, MIN_SIZE_mask);
1876 SETfield(r700->PA_SU_POINT_MINMAX.u32All, 0x8000, MAX_SIZE_shift, MAX_SIZE_mask);
1877
1878 r700LineWidth(ctx, 1.0);
1879
1880 r700->PA_SC_LINE_CNTL.u32All = 0;
1881 CLEARbit(r700->PA_SC_LINE_CNTL.u32All, EXPAND_LINE_WIDTH_bit);
1882 SETbit(r700->PA_SC_LINE_CNTL.u32All, LAST_PIXEL_bit);
1883
1884 r700ShadeModel(ctx, ctx->Light.ShadeModel);
1885 r700PolygonMode(ctx, GL_FRONT, ctx->Polygon.FrontMode);
1886 r700PolygonMode(ctx, GL_BACK, ctx->Polygon.BackMode);
1887 r700PolygonOffset(ctx, ctx->Polygon.OffsetFactor,
1888 ctx->Polygon.OffsetUnits);
1889 r700Enable(ctx, GL_POLYGON_OFFSET_POINT, ctx->Polygon.OffsetPoint);
1890 r700Enable(ctx, GL_POLYGON_OFFSET_LINE, ctx->Polygon.OffsetLine);
1891 r700Enable(ctx, GL_POLYGON_OFFSET_FILL, ctx->Polygon.OffsetFill);
1892
1893 /* CB */
1894 r700BlendColor(ctx, ctx->Color.BlendColor);
1895
1896 r700->CB_CLEAR_RED_R6XX.f32All = 1.0; //r6xx only
1897 r700->CB_CLEAR_GREEN_R6XX.f32All = 0.0; //r6xx only
1898 r700->CB_CLEAR_BLUE_R6XX.f32All = 1.0; //r6xx only
1899 r700->CB_CLEAR_ALPHA_R6XX.f32All = 1.0; //r6xx only
1900 r700->CB_FOG_RED_R6XX.u32All = 0; //r6xx only
1901 r700->CB_FOG_GREEN_R6XX.u32All = 0; //r6xx only
1902 r700->CB_FOG_BLUE_R6XX.u32All = 0; //r6xx only
1903
1904 /* Disable color compares */
1905 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1906 CLRCMP_FCN_SRC_shift, CLRCMP_FCN_SRC_mask);
1907 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1908 CLRCMP_FCN_DST_shift, CLRCMP_FCN_DST_mask);
1909 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_SEL_SRC,
1910 CLRCMP_FCN_SEL_shift, CLRCMP_FCN_SEL_mask);
1911
1912 /* Zero out source */
1913 r700->CB_CLRCMP_SRC.u32All = 0x00000000;
1914
1915 /* Put a compare color in for error checking */
1916 r700->CB_CLRCMP_DST.u32All = 0x000000FF;
1917
1918 /* Set up color compare mask */
1919 r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF;
1920
1921 context->radeon.hw.all_dirty = GL_TRUE;
1922
1923 }
1924
1925 void r700InitStateFuncs(struct dd_function_table *functions) //-----------------
1926 {
1927 functions->UpdateState = r700InvalidateState;
1928 functions->AlphaFunc = r700AlphaFunc;
1929 functions->BlendColor = r700BlendColor;
1930 functions->BlendEquationSeparate = r700BlendEquationSeparate;
1931 functions->BlendFuncSeparate = r700BlendFuncSeparate;
1932 functions->Enable = r700Enable;
1933 functions->ColorMask = r700ColorMask;
1934 functions->DepthFunc = r700DepthFunc;
1935 functions->DepthMask = r700DepthMask;
1936 functions->CullFace = r700CullFace;
1937 functions->Fogfv = r700Fogfv;
1938 functions->FrontFace = r700FrontFace;
1939 functions->ShadeModel = r700ShadeModel;
1940 functions->LogicOpcode = r700LogicOpcode;
1941
1942 /* ARB_point_parameters */
1943 functions->PointParameterfv = r700PointParameter;
1944
1945 /* Stencil related */
1946 functions->StencilFuncSeparate = r700StencilFuncSeparate;
1947 functions->StencilMaskSeparate = r700StencilMaskSeparate;
1948 functions->StencilOpSeparate = r700StencilOpSeparate;
1949
1950 /* Viewport related */
1951 functions->Viewport = r700Viewport;
1952 functions->DepthRange = r700DepthRange;
1953 functions->PointSize = r700PointSize;
1954 functions->LineWidth = r700LineWidth;
1955 functions->LineStipple = r700LineStipple;
1956
1957 functions->PolygonOffset = r700PolygonOffset;
1958 functions->PolygonMode = r700PolygonMode;
1959
1960 functions->RenderMode = r700RenderMode;
1961
1962 functions->ClipPlane = r700ClipPlane;
1963
1964 functions->Scissor = radeonScissor;
1965
1966 functions->DrawBuffer = radeonDrawBuffer;
1967 functions->ReadBuffer = radeonReadBuffer;
1968
1969 }
1970