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R6xx, add edge rules for triangles
[mesa.git] / src / mesa / drivers / dri / r600 / r700_state.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/dd.h"
34 #include "main/simple_list.h"
35
36 #include "tnl/tnl.h"
37 #include "tnl/t_pipeline.h"
38 #include "tnl/t_vp_build.h"
39 #include "swrast/swrast.h"
40 #include "swrast_setup/swrast_setup.h"
41 #include "main/api_arrayelt.h"
42 #include "main/state.h"
43 #include "main/framebuffer.h"
44
45 #include "shader/prog_parameter.h"
46 #include "shader/prog_statevars.h"
47 #include "vbo/vbo.h"
48 #include "main/texformat.h"
49
50 #include "r600_context.h"
51
52 #include "r700_chip.h"
53 #include "r700_state.h"
54
55 #include "r700_fragprog.h"
56 #include "r700_vertprog.h"
57
58
59 void r700SetDefaultStates(context_t *context) //--------------------
60 {
61
62 }
63
64 void r700UpdateShaders (GLcontext * ctx) //----------------------------------
65 {
66 context_t *context = R700_CONTEXT(ctx);
67
68 GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
69 GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
70
71 struct r700_vertex_program *vp;
72 int i;
73
74 if (context->radeon.NewGLState)
75 {
76 context->radeon.NewGLState = 0;
77
78 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++)
79 {
80 /* mat states from state var not array for sw */
81 dummy_attrib[i].stride = 0;
82
83 temp_attrib[i] = TNL_CONTEXT(ctx)->vb.AttribPtr[i];
84 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = &(dummy_attrib[i]);
85 }
86
87 _tnl_UpdateFixedFunctionProgram(ctx);
88
89 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++)
90 {
91 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = temp_attrib[i];
92 }
93
94 r700SelectVertexShader(ctx);
95 vp = (struct r700_vertex_program *)ctx->VertexProgram._Current;
96
97 if (vp->translated == GL_FALSE)
98 {
99 // TODO
100 //fprintf(stderr, "Failing back to sw-tcl\n");
101 //hw_tcl_on = future_hw_tcl_on = 0;
102 //r300ResetHwState(rmesa);
103 //
104 r700UpdateStateParameters(ctx, _NEW_PROGRAM);
105 return;
106 }
107 }
108
109 r700UpdateStateParameters(ctx, _NEW_PROGRAM);
110 }
111
112 /*
113 * To correctly position primitives:
114 */
115 void r700UpdateViewportOffset(GLcontext * ctx) //------------------
116 {
117 return;
118 }
119
120 /**
121 * Tell the card where to render (offset, pitch).
122 * Effected by glDrawBuffer, etc
123 */
124 void r700UpdateDrawBuffer(GLcontext * ctx) /* TODO */ //---------------------
125 {
126 #if 0 /* to be enabled */
127 context_t *context = R700_CONTEXT(ctx);
128
129 switch (ctx->DrawBuffer->_ColorDrawBufferIndexes[0])
130 {
131 case BUFFER_FRONT_LEFT:
132 context->target.rt = context->screen->frontBuffer;
133 break;
134 case BUFFER_BACK_LEFT:
135 context->target.rt = context->screen->backBuffer;
136 break;
137 default:
138 memset (&context->target.rt, sizeof(context->target.rt), 0);
139 }
140 #endif /* to be enabled */
141 }
142
143 static void r700FetchStateParameter(GLcontext * ctx,
144 const gl_state_index state[STATE_LENGTH],
145 GLfloat * value)
146 {
147 context_t *context = R700_CONTEXT(ctx);
148
149 /* TODO */
150 }
151
152 void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state) //--------------------
153 {
154 struct r700_fragment_program *fp;
155 struct gl_program_parameter_list *paramList;
156 GLuint i;
157
158 if (!(new_state & (_NEW_BUFFERS | _NEW_PROGRAM)))
159 return;
160
161 fp = (struct r700_fragment_program *)ctx->FragmentProgram._Current;
162 if (!fp)
163 {
164 return;
165 }
166
167 paramList = fp->mesa_program.Base.Parameters;
168
169 if (!paramList)
170 {
171 return;
172 }
173
174 for (i = 0; i < paramList->NumParameters; i++)
175 {
176 if (paramList->Parameters[i].Type == PROGRAM_STATE_VAR)
177 {
178 r700FetchStateParameter(ctx,
179 paramList->Parameters[i].
180 StateIndexes,
181 paramList->ParameterValues[i]);
182 }
183 }
184 }
185
186 /**
187 * Called by Mesa after an internal state update.
188 */
189 static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //-------------------
190 {
191 context_t *context = R700_CONTEXT(ctx);
192
193 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj);
194
195 _swrast_InvalidateState(ctx, new_state);
196 _swsetup_InvalidateState(ctx, new_state);
197 _vbo_InvalidateState(ctx, new_state);
198 _tnl_InvalidateState(ctx, new_state);
199 _ae_invalidate_state(ctx, new_state);
200
201 if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL))
202 {
203 _mesa_update_framebuffer(ctx);
204 /* this updates the DrawBuffer's Width/Height if it's a FBO */
205 _mesa_update_draw_buffer_bounds(ctx);
206
207 r700UpdateDrawBuffer(ctx);
208 }
209
210 r700UpdateStateParameters(ctx, new_state);
211
212 if(GL_TRUE == r700->bEnablePerspective)
213 {
214 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
215 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
216 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
217
218 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
219
220 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
221 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
222 }
223 else
224 {
225 /* For orthogonal case. */
226 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
227 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
228
229 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
230
231 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
232 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
233 }
234
235 context->radeon.NewGLState |= new_state;
236 }
237
238 static void r700SetDepthState(GLcontext * ctx)
239 {
240 context_t *context = R700_CONTEXT(ctx);
241
242 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj);
243
244 if (ctx->Depth.Test)
245 {
246 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
247 if (ctx->Depth.Mask)
248 {
249 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
250 }
251 else
252 {
253 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
254 }
255
256 switch (ctx->Depth.Func)
257 {
258 case GL_NEVER:
259 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NEVER,
260 ZFUNC_shift, ZFUNC_mask);
261 break;
262 case GL_LESS:
263 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LESS,
264 ZFUNC_shift, ZFUNC_mask);
265 break;
266 case GL_EQUAL:
267 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_EQUAL,
268 ZFUNC_shift, ZFUNC_mask);
269 break;
270 case GL_LEQUAL:
271 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LEQUAL,
272 ZFUNC_shift, ZFUNC_mask);
273 break;
274 case GL_GREATER:
275 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GREATER,
276 ZFUNC_shift, ZFUNC_mask);
277 break;
278 case GL_NOTEQUAL:
279 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NOTEQUAL,
280 ZFUNC_shift, ZFUNC_mask);
281 break;
282 case GL_GEQUAL:
283 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GEQUAL,
284 ZFUNC_shift, ZFUNC_mask);
285 break;
286 case GL_ALWAYS:
287 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
288 ZFUNC_shift, ZFUNC_mask);
289 break;
290 default:
291 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
292 ZFUNC_shift, ZFUNC_mask);
293 break;
294 }
295 }
296 else
297 {
298 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
299 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
300 }
301 }
302
303 static void r700AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref) //---------------
304 {
305 }
306
307
308 static void r700BlendColor(GLcontext * ctx, const GLfloat cf[4]) //----------------
309 {
310 }
311
312 static void r700BlendEquationSeparate(GLcontext * ctx,
313 GLenum modeRGB, GLenum modeA) //-----------------
314 {
315 }
316
317 static void r700BlendFuncSeparate(GLcontext * ctx,
318 GLenum sfactorRGB, GLenum dfactorRGB,
319 GLenum sfactorA, GLenum dfactorA) //------------------------
320 {
321 }
322
323 static void r700UpdateCulling(GLcontext * ctx)
324 {
325 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(R700_CONTEXT(ctx)->chipobj.pvChipObj);
326
327 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
328 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
329 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
330
331 if (ctx->Polygon.CullFlag)
332 {
333 switch (ctx->Polygon.CullFaceMode)
334 {
335 case GL_FRONT:
336 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
337 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
338 break;
339 case GL_BACK:
340 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
341 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
342 break;
343 case GL_FRONT_AND_BACK:
344 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
345 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
346 break;
347 default:
348 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
349 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
350 break;
351 }
352 }
353
354 switch (ctx->Polygon.FrontFace)
355 {
356 case GL_CW:
357 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
358 break;
359 case GL_CCW:
360 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
361 break;
362 default:
363 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); /* default: ccw */
364 break;
365 }
366 }
367
368 static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //------------------
369 {
370 switch (cap)
371 {
372 case GL_TEXTURE_1D:
373 case GL_TEXTURE_2D:
374 case GL_TEXTURE_3D:
375 break;
376 case GL_FOG:
377 break;
378 case GL_ALPHA_TEST:
379 break;
380 case GL_COLOR_LOGIC_OP:
381 case GL_BLEND:
382 break;
383 case GL_CLIP_PLANE0:
384 case GL_CLIP_PLANE1:
385 case GL_CLIP_PLANE2:
386 case GL_CLIP_PLANE3:
387 case GL_CLIP_PLANE4:
388 case GL_CLIP_PLANE5:
389 break;
390 case GL_DEPTH_TEST:
391 r700SetDepthState(ctx);
392 break;
393 case GL_STENCIL_TEST:
394 break;
395 case GL_CULL_FACE:
396 r700UpdateCulling(ctx);
397 break;
398 case GL_POLYGON_OFFSET_POINT:
399 case GL_POLYGON_OFFSET_LINE:
400 case GL_POLYGON_OFFSET_FILL:
401 break;
402 default:
403 break;
404 }
405 }
406
407 /**
408 * Handle glColorMask()
409 */
410 static void r700ColorMask(GLcontext * ctx,
411 GLboolean r, GLboolean g, GLboolean b, GLboolean a) //------------------
412 {
413 }
414
415 /**
416 * Change the depth testing function.
417 *
418 * \note Mesa already filters redundant calls to this function.
419 */
420 static void r700DepthFunc(GLcontext * ctx, GLenum func) //--------------------
421 {
422 r700SetDepthState(ctx);
423 }
424
425 /**
426 * Enable/Disable depth writing.
427 *
428 * \note Mesa already filters redundant calls to this function.
429 */
430 static void r700DepthMask(GLcontext * ctx, GLboolean mask) //------------------
431 {
432 r700SetDepthState(ctx);
433 }
434
435 /**
436 * Change the culling mode.
437 *
438 * \note Mesa already filters redundant calls to this function.
439 */
440 static void r700CullFace(GLcontext * ctx, GLenum mode) //-----------------
441 {
442 r700UpdateCulling(ctx);
443 }
444
445 /* =============================================================
446 * Fog
447 */
448 static void r700Fogfv(GLcontext * ctx, GLenum pname, const GLfloat * param) //--------------
449 {
450 }
451
452 /**
453 * Change the polygon orientation.
454 *
455 * \note Mesa already filters redundant calls to this function.
456 */
457 static void r700FrontFace(GLcontext * ctx, GLenum mode) //------------------
458 {
459 r700UpdateCulling(ctx);
460 }
461
462 static void r700ShadeModel(GLcontext * ctx, GLenum mode) //--------------------
463 {
464 }
465
466 static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * param) //---------------
467 {
468 }
469
470 static void r700StencilFuncSeparate(GLcontext * ctx, GLenum face,
471 GLenum func, GLint ref, GLuint mask) //---------------------
472 {
473 }
474
475
476 static void r700StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) //--------------
477 {
478 }
479
480 static void r700StencilOpSeparate(GLcontext * ctx, GLenum face,
481 GLenum fail, GLenum zfail, GLenum zpass) //--------------------
482 {
483 }
484
485 #define SUBPIXEL_X 0.125
486 #define SUBPIXEL_Y 0.125
487
488 static void r700Viewport(GLcontext * ctx,
489 GLint x,
490 GLint y,
491 GLsizei width,
492 GLsizei height) //--------------------
493 {
494 context_t *context = R700_CONTEXT(ctx);
495
496 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj);
497
498 __DRIdrawablePrivate *dPriv = context->radeon.dri.drawable;
499
500 GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
501 GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
502
503 const GLfloat *v = ctx->Viewport._WindowMap.m;
504
505 GLfloat sx, tx, sy, ty, sz, tz;
506 GLfloat scale;
507
508 switch (ctx->Visual.depthBits)
509 {
510 case 16:
511 scale = 1.0 / (GLfloat) 0xffff;
512 break;
513 case 24:
514 scale = 1.0 / (GLfloat) 0xffffff;
515 break;
516 default:
517 fprintf(stderr, "Error: Unsupported depth %d... exiting\n",
518 ctx->Visual.depthBits);
519 _mesa_exit(-1);
520 }
521
522 sx = v[MAT_SX];
523 tx = v[MAT_TX] + xoffset + SUBPIXEL_X;
524 sy = -v[MAT_SY];
525 ty = (-v[MAT_TY]) + yoffset + SUBPIXEL_Y;
526 sz = v[MAT_SZ] * scale;
527 tz = v[MAT_TZ] * scale;
528
529 /* TODO : Need DMA flush as well. */
530 #if 0 /* to be enabled */
531 if(context->cmdbuf.count_used > 0)
532 {
533 (context->chipobj.FlushCmdBuffer)(context);
534 }
535 #endif /* to be enabled */
536 r700->PA_CL_VPORT_XSCALE.u32All = *((unsigned int*)(&sx));
537 r700->PA_CL_VPORT_XOFFSET.u32All = *((unsigned int*)(&tx));
538
539 r700->PA_CL_VPORT_YSCALE.u32All = *((unsigned int*)(&sy));
540 r700->PA_CL_VPORT_YOFFSET.u32All = *((unsigned int*)(&ty));
541
542 r700->PA_CL_VPORT_ZSCALE.u32All = *((unsigned int*)(&sz));
543 r700->PA_CL_VPORT_ZOFFSET.u32All = *((unsigned int*)(&tz));
544 }
545
546
547 static void r700DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) //-------------
548 {
549 }
550
551 static void r700PointSize(GLcontext * ctx, GLfloat size) //-------------------
552 {
553 }
554
555 static void r700LineWidth(GLcontext * ctx, GLfloat widthf) //---------------
556 {
557 }
558
559 static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) //--------------
560 {
561 }
562
563
564 static void r700PolygonMode(GLcontext * ctx, GLenum face, GLenum mode) //------------------
565 {
566 }
567
568 static void r700RenderMode(GLcontext * ctx, GLenum mode) //---------------------
569 {
570 }
571
572 static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq ) //-----------------
573 {
574 }
575
576 static void r700Scissor(GLcontext* ctx, GLint x, GLint y, GLsizei w, GLsizei h) //---------------
577 {
578 if (ctx->Scissor.Enabled)
579 {
580 /* We don't pipeline cliprect changes */
581 /* r700Flush(ctx); */
582
583 //__DRIdrawablePrivate *dPriv = radeon->dri.drawable;
584 //int x1 = dPriv->x + ctx->Scissor.X;
585 //int y1 = dPriv->y + dPriv->h - (ctx->Scissor.Y + ctx->Scissor.Height);
586
587 //radeon->state.scissor.rect.x1 = x1;
588 //radeon->state.scissor.rect.y1 = y1;
589 //radeon->state.scissor.rect.x2 = x1 + ctx->Scissor.Width;
590 //radeon->state.scissor.rect.y2 = y1 + ctx->Scissor.Height;
591 /* radeonRecalcScissorRects(radeon); */
592 }
593 }
594
595 void r700SetRenderTarget(context_t *context)
596 {
597 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj);
598
599 struct radeon_renderbuffer *rrb;
600 unsigned int nPitchInPixel;
601
602 /* screen/window/view */
603 SETfield(r700->CB_TARGET_MASK.u32All, 0xF, TARGET0_ENABLE_shift, TARGET0_ENABLE_mask);
604 SETfield(r700->CB_SHADER_MASK.u32All, 0xF, OUTPUT0_ENABLE_shift, OUTPUT0_ENABLE_mask);
605
606 /* screen */
607 r700->PA_SC_SCREEN_SCISSOR_TL.u32All = 0x0;
608
609 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->width,
610 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask);
611 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All, ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->height,
612 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask);
613
614 /* window */
615 SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
616 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, context->radeon.dri.drawable->x,
617 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask);
618 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, context->radeon.dri.drawable->y,
619 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask);
620
621 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, context->radeon.dri.drawable->x + context->radeon.dri.drawable->w,
622 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask);
623 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, context->radeon.dri.drawable->y + context->radeon.dri.drawable->h,
624 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask);
625
626 /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
627 r700->PA_SC_CLIPRECT_RULE.u32All = 0x0000FFFF;
628
629 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, context->radeon.dri.drawable->x,
630 PA_SC_CLIPRECT_0_TL__TL_X_shift, PA_SC_CLIPRECT_0_TL__TL_X_mask);
631 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, context->radeon.dri.drawable->y,
632 PA_SC_CLIPRECT_0_TL__TL_Y_shift, PA_SC_CLIPRECT_0_TL__TL_Y_mask);
633 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, context->radeon.dri.drawable->x + context->radeon.dri.drawable->w,
634 PA_SC_CLIPRECT_0_BR__BR_X_shift, PA_SC_CLIPRECT_0_BR__BR_X_mask);
635 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, context->radeon.dri.drawable->y + context->radeon.dri.drawable->h,
636 PA_SC_CLIPRECT_0_BR__BR_Y_shift, PA_SC_CLIPRECT_0_BR__BR_Y_mask);
637
638 r700->PA_SC_CLIPRECT_1_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
639 r700->PA_SC_CLIPRECT_1_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
640 r700->PA_SC_CLIPRECT_2_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
641 r700->PA_SC_CLIPRECT_2_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
642 r700->PA_SC_CLIPRECT_3_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
643 r700->PA_SC_CLIPRECT_3_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
644
645 /* edgerule for triangles, points, recs, lines */
646 r700->PA_SC_EDGERULE.u32All = 0x555AA96A;
647
648 /* more....2d clip */
649 SETbit(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
650 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, context->radeon.dri.drawable->x,
651 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask);
652 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, context->radeon.dri.drawable->y,
653 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask);
654 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, context->radeon.dri.drawable->x + context->radeon.dri.drawable->w,
655 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask);
656 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, context->radeon.dri.drawable->y + context->radeon.dri.drawable->h,
657 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask);
658
659 SETbit(r700->PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
660 SETfield(r700->PA_SC_VPORT_SCISSOR_0_TL.u32All, context->radeon.dri.drawable->x,
661 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask);
662 SETfield(r700->PA_SC_VPORT_SCISSOR_0_TL.u32All, context->radeon.dri.drawable->y,
663 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask);
664 SETfield(r700->PA_SC_VPORT_SCISSOR_0_BR.u32All, context->radeon.dri.drawable->x + context->radeon.dri.drawable->w,
665 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask);
666 SETfield(r700->PA_SC_VPORT_SCISSOR_0_BR.u32All, context->radeon.dri.drawable->y + context->radeon.dri.drawable->h,
667 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask);
668
669 SETbit(r700->PA_SC_VPORT_SCISSOR_1_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
670 SETfield(r700->PA_SC_VPORT_SCISSOR_1_TL.u32All, context->radeon.dri.drawable->x,
671 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask);
672 SETfield(r700->PA_SC_VPORT_SCISSOR_1_TL.u32All, context->radeon.dri.drawable->y,
673 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask);
674 SETfield(r700->PA_SC_VPORT_SCISSOR_1_BR.u32All, context->radeon.dri.drawable->x + context->radeon.dri.drawable->w,
675 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask);
676 SETfield(r700->PA_SC_VPORT_SCISSOR_1_BR.u32All, context->radeon.dri.drawable->y + context->radeon.dri.drawable->h,
677 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask);
678
679 /* setup viewport */
680 r700Viewport(GL_CONTEXT(context),
681 0,
682 0,
683 context->radeon.dri.drawable->w,
684 context->radeon.dri.drawable->h);
685
686 rrb = radeon_get_colorbuffer(&context->radeon);
687 if (!rrb || !rrb->bo) {
688 fprintf(stderr, "no rrb\n");
689 return;
690 }
691
692 /* color buffer */
693 r700->CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset;
694
695 nPitchInPixel = rrb->pitch/rrb->cpp;
696 SETfield(r700->CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1,
697 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
698 SETfield(r700->CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
699 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
700 r700->CB_COLOR0_BASE.u32All = 0;
701 SETfield(r700->CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
702 SETfield(r700->CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL,
703 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
704 if(4 == rrb->cpp)
705 {
706 SETfield(r700->CB_COLOR0_INFO.u32All, COLOR_8_8_8_8,
707 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
708 SETfield(r700->CB_COLOR0_INFO.u32All, SWAP_ALT, COMP_SWAP_shift, COMP_SWAP_mask);
709 }
710 else
711 {
712 SETfield(r700->CB_COLOR0_INFO.u32All, COLOR_5_6_5,
713 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
714 SETfield(r700->CB_COLOR0_INFO.u32All, SWAP_ALT_REV,
715 COMP_SWAP_shift, COMP_SWAP_mask);
716 }
717 SETbit(r700->CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
718 SETbit(r700->CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit);
719 SETfield(r700->CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
720
721 /* depth buf */
722 r700->DB_DEPTH_SIZE.u32All = 0;
723 r700->DB_DEPTH_BASE.u32All = 0;
724 r700->DB_DEPTH_INFO.u32All = 0;
725
726 r700->DB_DEPTH_CONTROL.u32All = 0;
727 r700->DB_DEPTH_CLEAR.u32All = 0x3F800000;
728 r700->DB_DEPTH_VIEW.u32All = 0;
729 r700->DB_RENDER_CONTROL.u32All = 0;
730 r700->DB_RENDER_OVERRIDE.u32All = 0;
731 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
732 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
733 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
734
735 rrb = radeon_get_depthbuffer(&context->radeon);
736 if (!rrb)
737 return;
738
739 nPitchInPixel = rrb->pitch/rrb->cpp;
740
741 SETfield(r700->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1,
742 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
743 SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
744 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */
745
746 if(4 == rrb->cpp)
747 {
748 switch (GL_CONTEXT(context)->Visual.depthBits)
749 {
750 case 16:
751 case 24:
752 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_8_24,
753 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
754 break;
755 default:
756 fprintf(stderr, "Error: Unsupported depth %d... exiting\n",
757 GL_CONTEXT(context)->Visual.depthBits);
758 _mesa_exit(-1);
759 }
760 }
761 else
762 {
763 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16,
764 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
765 }
766 SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_2D_TILED_THIN1,
767 DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask);
768 /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */
769 }
770
771 /**
772 * Calculate initial hardware state and register state functions.
773 * Assumes that the command buffer and state atoms have been
774 * initialized already.
775 */
776 void r700InitState(GLcontext * ctx) //-------------------
777 {
778 context_t *context = R700_CONTEXT(ctx);
779
780 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(context->chipobj.pvChipObj);
781
782 /* Turn off vgt reuse */
783 r700->VGT_REUSE_OFF.u32All = 0;
784 SETbit(r700->VGT_REUSE_OFF.u32All, REUSE_OFF_bit);
785
786 /* Specify offsetting and clamp values for vertices */
787 r700->VGT_MAX_VTX_INDX.u32All = 0xFFFFFF;
788 r700->VGT_MIN_VTX_INDX.u32All = 0;
789 r700->VGT_INDX_OFFSET.u32All = 0;
790
791 /* Specify the number of instances */
792 r700->VGT_DMA_NUM_INSTANCES.u32All = 1;
793
794 /* not alpha blend */
795 CLEARfield(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_FUNC_mask);
796 CLEARbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
797
798 /* defualt shader connections. */
799 r700->SPI_VS_OUT_ID_0.u32All = 0x03020100;
800 r700->SPI_VS_OUT_ID_1.u32All = 0x07060504;
801
802 r700->SPI_PS_INPUT_CNTL_0.u32All = 0x00000800;
803 r700->SPI_PS_INPUT_CNTL_1.u32All = 0x00000801;
804 r700->SPI_PS_INPUT_CNTL_2.u32All = 0x00000802;
805
806 SETfield(r700->CB_COLOR_CONTROL.u32All, 0xCC, ROP3_shift, ROP3_mask);
807 CLEARbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit);
808 CLEARfield(r700->CB_BLEND0_CONTROL.u32All, COLOR_SRCBLEND_mask); /* no dst blend */
809 CLEARfield(r700->CB_BLEND0_CONTROL.u32All, ALPHA_SRCBLEND_mask); /* no dst blend */
810
811 r700->DB_SHADER_CONTROL.u32All = 0;
812 SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
813
814 /* Set up the culling control register */
815 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
816 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
817 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
818 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
819
820 /* Do scale XY and Z by 1/W0. */
821 r700->bEnablePerspective = GL_TRUE;
822 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
823 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
824 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
825
826 /* Enable viewport scaling for all three axis */
827 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_SCALE_ENA_bit);
828 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_OFFSET_ENA_bit);
829 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_SCALE_ENA_bit);
830 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_OFFSET_ENA_bit);
831 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_SCALE_ENA_bit);
832 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_OFFSET_ENA_bit);
833
834 /* Set up point sizes and min/max values */
835 SETfield(r700->PA_SU_POINT_SIZE.u32All, 0x8,
836 PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask);
837 SETfield(r700->PA_SU_POINT_SIZE.u32All, 0x8,
838 PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask);
839 CLEARfield(r700->PA_SU_POINT_MINMAX.u32All, MIN_SIZE_mask);
840 SETfield(r700->PA_SU_POINT_MINMAX.u32All, 0x8000, MAX_SIZE_shift, MAX_SIZE_mask);
841
842 /* Set up line control */
843 SETfield(r700->PA_SU_LINE_CNTL.u32All, 0x8,
844 PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
845
846 r700->PA_SC_LINE_CNTL.u32All = 0;
847 CLEARbit(r700->PA_SC_LINE_CNTL.u32All, EXPAND_LINE_WIDTH_bit);
848 SETbit(r700->PA_SC_LINE_CNTL.u32All, LAST_PIXEL_bit);
849
850 /* Set up vertex control */
851 r700->PA_SU_VTX_CNTL.u32All = 0;
852 CLEARfield(r700->PA_SU_VTX_CNTL.u32All, QUANT_MODE_mask);
853 SETbit(r700->PA_SU_VTX_CNTL.u32All, PIX_CENTER_bit);
854 SETfield(r700->PA_SU_VTX_CNTL.u32All, X_ROUND_TO_EVEN,
855 PA_SU_VTX_CNTL__ROUND_MODE_shift, PA_SU_VTX_CNTL__ROUND_MODE_mask);
856
857 /* to 1.0 = no guard band */
858 r700->PA_CL_GB_VERT_CLIP_ADJ.u32All = 0x3F800000; /* 1.0 */
859 r700->PA_CL_GB_VERT_DISC_ADJ.u32All = 0x3F800000;
860 r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All = 0x3F800000;
861 r700->PA_CL_GB_HORZ_DISC_ADJ.u32All = 0x3F800000;
862
863 /* Disble color compares */
864 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
865 CLRCMP_FCN_SRC_shift, CLRCMP_FCN_SRC_mask);
866 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
867 CLRCMP_FCN_DST_shift, CLRCMP_FCN_DST_mask);
868 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_SEL_SRC,
869 CLRCMP_FCN_SEL_shift, CLRCMP_FCN_SEL_mask);
870
871 /* Zero out source */
872 r700->CB_CLRCMP_SRC.u32All = 0x00000000;
873
874 /* Put a compare color in for error checking */
875 r700->CB_CLRCMP_DST.u32All = 0x000000FF;
876
877 /* Set up color compare mask */
878 r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF;
879
880 /* Enable all samples for multi-sample anti-aliasing */
881 r700->PA_SC_AA_MASK.u32All = 0xFFFFFFFF;
882 /* Turn off AA */
883 r700->PA_SC_AA_CONFIG.u32All = 0;
884
885 SETfield(r700->VGT_OUT_DEALLOC_CNTL.u32All, 16, DEALLOC_DIST_shift, DEALLOC_DIST_mask);
886 SETfield(r700->VGT_VERTEX_REUSE_BLOCK_CNTL.u32All, 14, VTX_REUSE_DEPTH_shift, VTX_REUSE_DEPTH_mask);
887
888 r700->SX_MISC.u32All = 0;
889
890 /* depth buf */
891 r700->DB_DEPTH_SIZE.u32All = 0;
892 r700->DB_DEPTH_BASE.u32All = 0;
893 r700->DB_DEPTH_INFO.u32All = 0;
894 r700->DB_DEPTH_CONTROL.u32All = 0;
895 r700->DB_DEPTH_CLEAR.u32All = 0x3F800000;
896 r700->DB_DEPTH_VIEW.u32All = 0;
897 r700->DB_RENDER_CONTROL.u32All = 0;
898 r700->DB_RENDER_OVERRIDE.u32All = 0;
899 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
900 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
901 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
902
903 /* color buffer */
904 r700->CB_COLOR0_SIZE.u32All = 0;
905 r700->CB_COLOR0_BASE.u32All = 0;
906 r700->CB_COLOR0_INFO.u32All = 0;
907 SETbit(r700->CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
908 SETbit(r700->CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit);
909 SETfield(r700->CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
910 r700->CB_COLOR0_VIEW.u32All = 0;
911 r700->CB_COLOR0_TILE.u32All = 0;
912 r700->CB_COLOR0_FRAG.u32All = 0;
913 r700->CB_COLOR0_MASK.u32All = 0;
914
915 r700->PA_SC_VPORT_ZMAX_0.u32All = 0x3F800000;
916 }
917
918 void r700InitStateFuncs(struct dd_function_table *functions) //-----------------
919 {
920 functions->UpdateState = r700InvalidateState;
921 functions->AlphaFunc = r700AlphaFunc;
922 functions->BlendColor = r700BlendColor;
923 functions->BlendEquationSeparate = r700BlendEquationSeparate;
924 functions->BlendFuncSeparate = r700BlendFuncSeparate;
925 functions->Enable = r700Enable;
926 functions->ColorMask = r700ColorMask;
927 functions->DepthFunc = r700DepthFunc;
928 functions->DepthMask = r700DepthMask;
929 functions->CullFace = r700CullFace;
930 functions->Fogfv = r700Fogfv;
931 functions->FrontFace = r700FrontFace;
932 functions->ShadeModel = r700ShadeModel;
933
934 /* ARB_point_parameters */
935 functions->PointParameterfv = r700PointParameter;
936
937 /* Stencil related */
938 functions->StencilFuncSeparate = r700StencilFuncSeparate;
939 functions->StencilMaskSeparate = r700StencilMaskSeparate;
940 functions->StencilOpSeparate = r700StencilOpSeparate;
941
942 /* Viewport related */
943 functions->Viewport = r700Viewport;
944 functions->DepthRange = r700DepthRange;
945 functions->PointSize = r700PointSize;
946 functions->LineWidth = r700LineWidth;
947
948 functions->PolygonOffset = r700PolygonOffset;
949 functions->PolygonMode = r700PolygonMode;
950
951 functions->RenderMode = r700RenderMode;
952
953 functions->ClipPlane = r700ClipPlane;
954
955 functions->Scissor = r700Scissor;
956 }
957