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r600: fix typo in blend code
[mesa.git] / src / mesa / drivers / dri / r600 / r700_state.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/context.h"
34 #include "main/dd.h"
35 #include "main/simple_list.h"
36
37 #include "tnl/tnl.h"
38 #include "tnl/t_pipeline.h"
39 #include "tnl/t_vp_build.h"
40 #include "swrast/swrast.h"
41 #include "swrast_setup/swrast_setup.h"
42 #include "main/api_arrayelt.h"
43 #include "main/state.h"
44 #include "main/framebuffer.h"
45
46 #include "shader/prog_parameter.h"
47 #include "shader/prog_statevars.h"
48 #include "vbo/vbo.h"
49 #include "main/texformat.h"
50
51 #include "r600_context.h"
52
53 #include "r700_state.h"
54
55 #include "r700_fragprog.h"
56 #include "r700_vertprog.h"
57
58
59 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state);
60
61 void r700SetDefaultStates(context_t *context) //--------------------
62 {
63
64 }
65
66 void r700UpdateShaders (GLcontext * ctx) //----------------------------------
67 {
68 context_t *context = R700_CONTEXT(ctx);
69
70 GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
71 GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
72
73 struct r700_vertex_program *vp;
74 int i;
75
76 if (context->radeon.NewGLState)
77 {
78 context->radeon.NewGLState = 0;
79
80 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++)
81 {
82 /* mat states from state var not array for sw */
83 dummy_attrib[i].stride = 0;
84
85 temp_attrib[i] = TNL_CONTEXT(ctx)->vb.AttribPtr[i];
86 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = &(dummy_attrib[i]);
87 }
88
89 _tnl_UpdateFixedFunctionProgram(ctx);
90
91 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++)
92 {
93 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = temp_attrib[i];
94 }
95
96 r700SelectVertexShader(ctx);
97 vp = (struct r700_vertex_program *)ctx->VertexProgram._Current;
98
99 if (vp->translated == GL_FALSE)
100 {
101 // TODO
102 //fprintf(stderr, "Failing back to sw-tcl\n");
103 //hw_tcl_on = future_hw_tcl_on = 0;
104 //r300ResetHwState(rmesa);
105 //
106 r700UpdateStateParameters(ctx, _NEW_PROGRAM);
107 return;
108 }
109 }
110
111 r700UpdateStateParameters(ctx, _NEW_PROGRAM);
112 }
113
114 /*
115 * To correctly position primitives:
116 */
117 void r700UpdateViewportOffset(GLcontext * ctx) //------------------
118 {
119
120 //radeonUpdateScissor(ctx);
121
122 return;
123 }
124
125 /**
126 * Tell the card where to render (offset, pitch).
127 * Effected by glDrawBuffer, etc
128 */
129 void r700UpdateDrawBuffer(GLcontext * ctx) /* TODO */ //---------------------
130 {
131 #if 0 /* to be enabled */
132 context_t *context = R700_CONTEXT(ctx);
133
134 switch (ctx->DrawBuffer->_ColorDrawBufferIndexes[0])
135 {
136 case BUFFER_FRONT_LEFT:
137 context->target.rt = context->screen->frontBuffer;
138 break;
139 case BUFFER_BACK_LEFT:
140 context->target.rt = context->screen->backBuffer;
141 break;
142 default:
143 memset (&context->target.rt, sizeof(context->target.rt), 0);
144 }
145 #endif /* to be enabled */
146 }
147
148 static void r700FetchStateParameter(GLcontext * ctx,
149 const gl_state_index state[STATE_LENGTH],
150 GLfloat * value)
151 {
152 context_t *context = R700_CONTEXT(ctx);
153
154 /* TODO */
155 }
156
157 void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state) //--------------------
158 {
159 struct r700_fragment_program *fp;
160 struct gl_program_parameter_list *paramList;
161 GLuint i;
162
163 if (!(new_state & (_NEW_BUFFERS | _NEW_PROGRAM)))
164 return;
165
166 fp = (struct r700_fragment_program *)ctx->FragmentProgram._Current;
167 if (!fp)
168 {
169 return;
170 }
171
172 paramList = fp->mesa_program.Base.Parameters;
173
174 if (!paramList)
175 {
176 return;
177 }
178
179 for (i = 0; i < paramList->NumParameters; i++)
180 {
181 if (paramList->Parameters[i].Type == PROGRAM_STATE_VAR)
182 {
183 r700FetchStateParameter(ctx,
184 paramList->Parameters[i].
185 StateIndexes,
186 paramList->ParameterValues[i]);
187 }
188 }
189 }
190
191 /**
192 * Called by Mesa after an internal state update.
193 */
194 static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //-------------------
195 {
196 context_t *context = R700_CONTEXT(ctx);
197
198 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
199
200 _swrast_InvalidateState(ctx, new_state);
201 _swsetup_InvalidateState(ctx, new_state);
202 _vbo_InvalidateState(ctx, new_state);
203 _tnl_InvalidateState(ctx, new_state);
204 _ae_invalidate_state(ctx, new_state);
205
206 if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL))
207 {
208 _mesa_update_framebuffer(ctx);
209 /* this updates the DrawBuffer's Width/Height if it's a FBO */
210 _mesa_update_draw_buffer_bounds(ctx);
211
212 r700UpdateDrawBuffer(ctx);
213 }
214
215 r700UpdateStateParameters(ctx, new_state);
216
217 if(GL_TRUE == r700->bEnablePerspective)
218 {
219 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
220 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
221 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
222
223 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
224
225 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
226 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
227 }
228 else
229 {
230 /* For orthogonal case. */
231 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
232 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
233
234 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
235
236 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
237 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
238 }
239
240 context->radeon.NewGLState |= new_state;
241 }
242
243 static void r700SetDepthState(GLcontext * ctx)
244 {
245 context_t *context = R700_CONTEXT(ctx);
246
247 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
248
249 if (ctx->Depth.Test)
250 {
251 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
252 if (ctx->Depth.Mask)
253 {
254 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
255 }
256 else
257 {
258 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
259 }
260
261 switch (ctx->Depth.Func)
262 {
263 case GL_NEVER:
264 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NEVER,
265 ZFUNC_shift, ZFUNC_mask);
266 break;
267 case GL_LESS:
268 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LESS,
269 ZFUNC_shift, ZFUNC_mask);
270 break;
271 case GL_EQUAL:
272 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_EQUAL,
273 ZFUNC_shift, ZFUNC_mask);
274 break;
275 case GL_LEQUAL:
276 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LEQUAL,
277 ZFUNC_shift, ZFUNC_mask);
278 break;
279 case GL_GREATER:
280 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GREATER,
281 ZFUNC_shift, ZFUNC_mask);
282 break;
283 case GL_NOTEQUAL:
284 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NOTEQUAL,
285 ZFUNC_shift, ZFUNC_mask);
286 break;
287 case GL_GEQUAL:
288 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GEQUAL,
289 ZFUNC_shift, ZFUNC_mask);
290 break;
291 case GL_ALWAYS:
292 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
293 ZFUNC_shift, ZFUNC_mask);
294 break;
295 default:
296 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
297 ZFUNC_shift, ZFUNC_mask);
298 break;
299 }
300 }
301 else
302 {
303 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
304 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
305 }
306 }
307
308 static void r700AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref) //---------------
309 {
310 }
311
312
313 static void r700BlendColor(GLcontext * ctx, const GLfloat cf[4]) //----------------
314 {
315 context_t *context = R700_CONTEXT(ctx);
316 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
317
318 r700->CB_BLEND_RED.f32All = cf[0];
319 r700->CB_BLEND_GREEN.f32All = cf[1];
320 r700->CB_BLEND_BLUE.f32All = cf[2];
321 r700->CB_BLEND_ALPHA.f32All = cf[3];
322 }
323
324 static int blend_factor(GLenum factor, GLboolean is_src)
325 {
326 switch (factor) {
327 case GL_ZERO:
328 return BLEND_ZERO;
329 break;
330 case GL_ONE:
331 return BLEND_ONE;
332 break;
333 case GL_DST_COLOR:
334 return BLEND_DST_COLOR;
335 break;
336 case GL_ONE_MINUS_DST_COLOR:
337 return BLEND_ONE_MINUS_DST_COLOR;
338 break;
339 case GL_SRC_COLOR:
340 return BLEND_SRC_COLOR;
341 break;
342 case GL_ONE_MINUS_SRC_COLOR:
343 return BLEND_ONE_MINUS_SRC_COLOR;
344 break;
345 case GL_SRC_ALPHA:
346 return BLEND_SRC_ALPHA;
347 break;
348 case GL_ONE_MINUS_SRC_ALPHA:
349 return BLEND_ONE_MINUS_SRC_ALPHA;
350 break;
351 case GL_DST_ALPHA:
352 return BLEND_DST_ALPHA;
353 break;
354 case GL_ONE_MINUS_DST_ALPHA:
355 return BLEND_ONE_MINUS_DST_ALPHA;
356 break;
357 case GL_SRC_ALPHA_SATURATE:
358 return (is_src) ? BLEND_SRC_ALPHA_SATURATE : BLEND_ZERO;
359 break;
360 case GL_CONSTANT_COLOR:
361 return BLEND_CONSTANT_COLOR;
362 break;
363 case GL_ONE_MINUS_CONSTANT_COLOR:
364 return BLEND_ONE_MINUS_CONSTANT_COLOR;
365 break;
366 case GL_CONSTANT_ALPHA:
367 return BLEND_CONSTANT_ALPHA;
368 break;
369 case GL_ONE_MINUS_CONSTANT_ALPHA:
370 return BLEND_ONE_MINUS_CONSTANT_ALPHA;
371 break;
372 default:
373 fprintf(stderr, "unknown blend factor %x\n", factor);
374 return (is_src) ? BLEND_ONE : BLEND_ZERO;
375 break;
376 }
377 }
378
379 static void r700SetBlendState(GLcontext * ctx)
380 {
381 context_t *context = R700_CONTEXT(ctx);
382 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
383 int id = 0;
384 uint32_t blend_reg = 0, eqn, eqnA;
385
386 if (RGBA_LOGICOP_ENABLED(ctx) || !ctx->Color.BlendEnabled) {
387 SETfield(blend_reg,
388 BLEND_ONE, COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
389 SETfield(blend_reg,
390 BLEND_ZERO, COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
391 SETfield(blend_reg,
392 COMB_DST_PLUS_SRC, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
393 SETfield(blend_reg,
394 BLEND_ONE, ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
395 SETfield(blend_reg,
396 BLEND_ZERO, ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
397 SETfield(blend_reg,
398 COMB_DST_PLUS_SRC, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
399 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
400 r700->CB_BLEND_CONTROL.u32All = blend_reg;
401 else
402 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
403 return;
404 }
405
406 SETfield(blend_reg,
407 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
408 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
409 SETfield(blend_reg,
410 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
411 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
412
413 switch (ctx->Color.BlendEquationRGB) {
414 case GL_FUNC_ADD:
415 eqn = COMB_DST_PLUS_SRC;
416 break;
417 case GL_FUNC_SUBTRACT:
418 eqn = COMB_SRC_MINUS_DST;
419 break;
420 case GL_FUNC_REVERSE_SUBTRACT:
421 eqn = COMB_DST_MINUS_SRC;
422 break;
423 case GL_MIN:
424 eqn = COMB_MIN_DST_SRC;
425 SETfield(blend_reg,
426 BLEND_ONE,
427 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
428 SETfield(blend_reg,
429 BLEND_ONE,
430 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
431 break;
432 case GL_MAX:
433 eqn = COMB_MAX_DST_SRC;
434 SETfield(blend_reg,
435 BLEND_ONE,
436 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
437 SETfield(blend_reg,
438 BLEND_ONE,
439 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
440 break;
441
442 default:
443 fprintf(stderr,
444 "[%s:%u] Invalid RGB blend equation (0x%04x).\n",
445 __FUNCTION__, __LINE__, ctx->Color.BlendEquationRGB);
446 return;
447 }
448 SETfield(blend_reg,
449 eqn, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
450
451 SETfield(blend_reg,
452 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
453 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
454 SETfield(blend_reg,
455 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
456 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
457
458 switch (ctx->Color.BlendEquationA) {
459 case GL_FUNC_ADD:
460 eqnA = COMB_DST_PLUS_SRC;
461 break;
462 case GL_FUNC_SUBTRACT:
463 eqnA = COMB_SRC_MINUS_DST;
464 break;
465 case GL_FUNC_REVERSE_SUBTRACT:
466 eqnA = COMB_DST_MINUS_SRC;
467 break;
468 case GL_MIN:
469 eqnA = COMB_MIN_DST_SRC;
470 SETfield(blend_reg,
471 BLEND_ONE,
472 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
473 SETfield(blend_reg,
474 BLEND_ONE,
475 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
476 break;
477 case GL_MAX:
478 eqnA = COMB_MAX_DST_SRC;
479 SETfield(blend_reg,
480 BLEND_ONE,
481 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
482 SETfield(blend_reg,
483 BLEND_ONE,
484 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
485 break;
486 default:
487 fprintf(stderr,
488 "[%s:%u] Invalid A blend equation (0x%04x).\n",
489 __FUNCTION__, __LINE__, ctx->Color.BlendEquationA);
490 return;
491 }
492
493 SETfield(blend_reg,
494 eqnA, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
495
496 SETbit(blend_reg, SEPARATE_ALPHA_BLEND_bit);
497
498 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
499 r700->CB_BLEND_CONTROL.u32All = blend_reg;
500 else {
501 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
502 SETbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit);
503 }
504 SETfield(r700->CB_COLOR_CONTROL.u32All, (1 << id),
505 TARGET_BLEND_ENABLE_shift, TARGET_BLEND_ENABLE_mask);
506
507 }
508
509 static void r700BlendEquationSeparate(GLcontext * ctx,
510 GLenum modeRGB, GLenum modeA) //-----------------
511 {
512 r700SetBlendState(ctx);
513 }
514
515 static void r700BlendFuncSeparate(GLcontext * ctx,
516 GLenum sfactorRGB, GLenum dfactorRGB,
517 GLenum sfactorA, GLenum dfactorA) //------------------------
518 {
519 r700SetBlendState(ctx);
520 }
521
522 /**
523 * Translate LogicOp enums into hardware representation.
524 * Both use a very logical bit-wise layout, but unfortunately the order
525 * of bits is reversed.
526 */
527 static GLuint translate_logicop(GLenum logicop)
528 {
529 GLuint bits = logicop - GL_CLEAR;
530 bits = ((bits & 1) << 3) | ((bits & 2) << 1) | ((bits & 4) >> 1) | ((bits & 8) >> 3);
531 return bits;
532 }
533
534 /**
535 * Used internally to update the r300->hw hardware state to match the
536 * current OpenGL state.
537 */
538 static void r700SetLogicOpState(GLcontext *ctx)
539 {
540 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
541
542 if (RGBA_LOGICOP_ENABLED(ctx))
543 SETfield(r700->CB_COLOR_CONTROL.u32All,
544 translate_logicop(ctx->Color.LogicOp), ROP3_shift, ROP3_mask);
545 else
546 SETfield(r700->CB_COLOR_CONTROL.u32All, 0xCC, ROP3_shift, ROP3_mask);
547 }
548
549 /**
550 * Called by Mesa when an application program changes the LogicOp state
551 * via glLogicOp.
552 */
553 static void r700LogicOpcode(GLcontext *ctx, GLenum logicop)
554 {
555 if (RGBA_LOGICOP_ENABLED(ctx))
556 r700SetLogicOpState(ctx);
557 }
558
559 static void r700UpdateCulling(GLcontext * ctx)
560 {
561 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
562
563 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
564 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
565 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
566
567 if (ctx->Polygon.CullFlag)
568 {
569 switch (ctx->Polygon.CullFaceMode)
570 {
571 case GL_FRONT:
572 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
573 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
574 break;
575 case GL_BACK:
576 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
577 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
578 break;
579 case GL_FRONT_AND_BACK:
580 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
581 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
582 break;
583 default:
584 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
585 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
586 break;
587 }
588 }
589
590 switch (ctx->Polygon.FrontFace)
591 {
592 case GL_CW:
593 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
594 break;
595 case GL_CCW:
596 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
597 break;
598 default:
599 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); /* default: ccw */
600 break;
601 }
602 }
603
604 static void r700UpdateLineStipple(GLcontext * ctx)
605 {
606 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
607 if (ctx->Line.StippleFlag)
608 {
609 SETbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
610 }
611 else
612 {
613 CLEARbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
614 }
615 }
616
617 static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //------------------
618 {
619 context_t *context = R700_CONTEXT(ctx);
620
621 switch (cap) {
622 case GL_TEXTURE_1D:
623 case GL_TEXTURE_2D:
624 case GL_TEXTURE_3D:
625 /* empty */
626 break;
627 case GL_FOG:
628 /* empty */
629 break;
630 case GL_ALPHA_TEST:
631 //r700SetAlphaState(ctx);
632 break;
633 case GL_COLOR_LOGIC_OP:
634 r700SetLogicOpState(ctx);
635 /* fall-through, because logic op overrides blending */
636 case GL_BLEND:
637 r700SetBlendState(ctx);
638 break;
639 case GL_CLIP_PLANE0:
640 case GL_CLIP_PLANE1:
641 case GL_CLIP_PLANE2:
642 case GL_CLIP_PLANE3:
643 case GL_CLIP_PLANE4:
644 case GL_CLIP_PLANE5:
645 r700SetClipPlaneState(ctx, cap, state);
646 break;
647 case GL_DEPTH_TEST:
648 r700SetDepthState(ctx);
649 break;
650 case GL_STENCIL_TEST:
651 //r700SetStencilState(ctx, state);
652 break;
653 case GL_CULL_FACE:
654 r700UpdateCulling(ctx);
655 break;
656 case GL_POLYGON_OFFSET_POINT:
657 case GL_POLYGON_OFFSET_LINE:
658 case GL_POLYGON_OFFSET_FILL:
659 //r700SetPolygonOffsetState(ctx, state);
660 break;
661 case GL_SCISSOR_TEST:
662 radeon_firevertices(&context->radeon);
663 context->radeon.state.scissor.enabled = state;
664 radeonUpdateScissor(ctx);
665 break;
666 case GL_LINE_STIPPLE:
667 r700UpdateLineStipple(ctx);
668 break;
669 default:
670 break;
671 }
672
673 }
674
675 /**
676 * Handle glColorMask()
677 */
678 static void r700ColorMask(GLcontext * ctx,
679 GLboolean r, GLboolean g, GLboolean b, GLboolean a) //------------------
680 {
681 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
682 unsigned int mask = ((r ? 1 : 0) |
683 (g ? 2 : 0) |
684 (b ? 4 : 0) |
685 (a ? 8 : 0));
686
687 if (mask != r700->CB_SHADER_MASK.u32All)
688 SETfield(r700->CB_SHADER_MASK.u32All, mask, OUTPUT0_ENABLE_shift, OUTPUT0_ENABLE_mask);
689 }
690
691 /**
692 * Change the depth testing function.
693 *
694 * \note Mesa already filters redundant calls to this function.
695 */
696 static void r700DepthFunc(GLcontext * ctx, GLenum func) //--------------------
697 {
698 r700SetDepthState(ctx);
699 }
700
701 /**
702 * Enable/Disable depth writing.
703 *
704 * \note Mesa already filters redundant calls to this function.
705 */
706 static void r700DepthMask(GLcontext * ctx, GLboolean mask) //------------------
707 {
708 r700SetDepthState(ctx);
709 }
710
711 /**
712 * Change the culling mode.
713 *
714 * \note Mesa already filters redundant calls to this function.
715 */
716 static void r700CullFace(GLcontext * ctx, GLenum mode) //-----------------
717 {
718 r700UpdateCulling(ctx);
719 }
720
721 /* =============================================================
722 * Fog
723 */
724 static void r700Fogfv(GLcontext * ctx, GLenum pname, const GLfloat * param) //--------------
725 {
726 }
727
728 /**
729 * Change the polygon orientation.
730 *
731 * \note Mesa already filters redundant calls to this function.
732 */
733 static void r700FrontFace(GLcontext * ctx, GLenum mode) //------------------
734 {
735 r700UpdateCulling(ctx);
736 }
737
738 static void r700ShadeModel(GLcontext * ctx, GLenum mode) //--------------------
739 {
740 context_t *context = R700_CONTEXT(ctx);
741 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
742
743 /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */
744 switch (mode) {
745 case GL_FLAT:
746 SETbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
747 break;
748 case GL_SMOOTH:
749 CLEARbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
750 break;
751 default:
752 return;
753 }
754 }
755
756 static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * param) //---------------
757 {
758 }
759
760 static void r700StencilFuncSeparate(GLcontext * ctx, GLenum face,
761 GLenum func, GLint ref, GLuint mask) //---------------------
762 {
763 }
764
765
766 static void r700StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) //--------------
767 {
768 }
769
770 static void r700StencilOpSeparate(GLcontext * ctx, GLenum face,
771 GLenum fail, GLenum zfail, GLenum zpass) //--------------------
772 {
773 }
774
775 static void r700UpdateWindow(GLcontext * ctx, int id) //--------------------
776 {
777
778 context_t *context = R700_CONTEXT(ctx);
779 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
780 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
781 GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
782 GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
783 const GLfloat *v = ctx->Viewport._WindowMap.m;
784 const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
785 const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
786 GLfloat y_scale, y_bias;
787
788 if (render_to_fbo) {
789 y_scale = 1.0;
790 y_bias = 0;
791 } else {
792 y_scale = -1.0;
793 y_bias = yoffset;
794 }
795
796 GLfloat sx = v[MAT_SX];
797 GLfloat tx = v[MAT_TX] + xoffset;
798 GLfloat sy = v[MAT_SY] * y_scale;
799 GLfloat ty = (v[MAT_TY] * y_scale) + y_bias;
800 GLfloat sz = v[MAT_SZ] * depthScale;
801 GLfloat tz = v[MAT_TZ] * depthScale;
802
803 /* TODO : Need DMA flush as well. */
804
805 r700->viewport[id].PA_CL_VPORT_XSCALE.f32All = sx;
806 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
807
808 r700->viewport[id].PA_CL_VPORT_YSCALE.f32All = sy;
809 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
810
811 r700->viewport[id].PA_CL_VPORT_ZSCALE.f32All = sz;
812 r700->viewport[id].PA_CL_VPORT_ZOFFSET.f32All = tz;
813
814 r700->viewport[id].enabled = GL_TRUE;
815
816 r700SetScissor(context);
817 }
818
819
820 static void r700Viewport(GLcontext * ctx,
821 GLint x,
822 GLint y,
823 GLsizei width,
824 GLsizei height) //--------------------
825 {
826 r700UpdateWindow(ctx, 0);
827
828 radeon_viewport(ctx, x, y, width, height);
829 }
830
831 static void r700DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) //-------------
832 {
833 r700UpdateWindow(ctx, 0);
834 }
835
836 static void r700PointSize(GLcontext * ctx, GLfloat size) //-------------------
837 {
838 }
839
840 static void r700LineWidth(GLcontext * ctx, GLfloat widthf) //---------------
841 {
842 context_t *context = R700_CONTEXT(ctx);
843 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
844 uint32_t lineWidth = (uint32_t)((widthf * 0.5) * (1 << 4));
845 if (lineWidth > 0xFFFF)
846 lineWidth = 0xFFFF;
847 SETfield(r700->PA_SU_LINE_CNTL.u32All,(uint16_t)lineWidth,
848 PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
849 }
850
851 static void r700LineStipple(GLcontext *ctx, GLint factor, GLushort pattern)
852 {
853 context_t *context = R700_CONTEXT(ctx);
854 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
855
856 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, pattern, LINE_PATTERN_shift, LINE_PATTERN_mask);
857 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, (factor-1), REPEAT_COUNT_shift, REPEAT_COUNT_mask);
858 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, 1, AUTO_RESET_CNTL_shift, AUTO_RESET_CNTL_mask);
859 }
860
861 static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) //--------------
862 {
863 }
864
865
866 static void r700PolygonMode(GLcontext * ctx, GLenum face, GLenum mode) //------------------
867 {
868 }
869
870 static void r700RenderMode(GLcontext * ctx, GLenum mode) //---------------------
871 {
872 }
873
874 static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
875 {
876 context_t *context = R700_CONTEXT(ctx);
877 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
878 GLint p;
879 GLint *ip;
880
881 p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
882 ip = (GLint *)ctx->Transform._ClipUserPlane[p];
883
884 r700->ucp[p].PA_CL_UCP_0_X.u32All = ip[0];
885 r700->ucp[p].PA_CL_UCP_0_Y.u32All = ip[1];
886 r700->ucp[p].PA_CL_UCP_0_Z.u32All = ip[2];
887 r700->ucp[p].PA_CL_UCP_0_W.u32All = ip[3];
888 }
889
890 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state)
891 {
892 context_t *context = R700_CONTEXT(ctx);
893 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
894 GLuint p;
895
896 p = cap - GL_CLIP_PLANE0;
897 if (state) {
898 r700->PA_CL_CLIP_CNTL.u32All |= (UCP_ENA_0_bit << p);
899 r700->ucp[p].enabled = GL_TRUE;
900 r700ClipPlane(ctx, cap, NULL);
901 } else {
902 r700->PA_CL_CLIP_CNTL.u32All &= ~(UCP_ENA_0_bit << p);
903 r700->ucp[p].enabled = GL_FALSE;
904 }
905 }
906
907 void r700SetScissor(context_t *context) //---------------
908 {
909 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
910 unsigned x1, y1, x2, y2;
911 int id = 0;
912 struct radeon_renderbuffer *rrb;
913
914 rrb = radeon_get_colorbuffer(&context->radeon);
915 if (!rrb || !rrb->bo) {
916 return;
917 }
918 if (context->radeon.state.scissor.enabled) {
919 x1 = context->radeon.state.scissor.rect.x1;
920 y1 = context->radeon.state.scissor.rect.y1;
921 x2 = context->radeon.state.scissor.rect.x2 - 1;
922 y2 = context->radeon.state.scissor.rect.y2 - 1;
923 } else {
924 x1 = rrb->dPriv->x;
925 y1 = rrb->dPriv->y;
926 x2 = rrb->dPriv->x + rrb->dPriv->w;
927 y2 = rrb->dPriv->y + rrb->dPriv->h;
928 }
929
930 /* window */
931 SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
932 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, x1,
933 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask);
934 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, y1,
935 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask);
936
937 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, x2,
938 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask);
939 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, y2,
940 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask);
941
942
943 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, x1,
944 PA_SC_CLIPRECT_0_TL__TL_X_shift, PA_SC_CLIPRECT_0_TL__TL_X_mask);
945 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, y1,
946 PA_SC_CLIPRECT_0_TL__TL_Y_shift, PA_SC_CLIPRECT_0_TL__TL_Y_mask);
947 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, x2,
948 PA_SC_CLIPRECT_0_BR__BR_X_shift, PA_SC_CLIPRECT_0_BR__BR_X_mask);
949 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, y2,
950 PA_SC_CLIPRECT_0_BR__BR_Y_shift, PA_SC_CLIPRECT_0_BR__BR_Y_mask);
951
952 r700->PA_SC_CLIPRECT_1_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
953 r700->PA_SC_CLIPRECT_1_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
954 r700->PA_SC_CLIPRECT_2_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
955 r700->PA_SC_CLIPRECT_2_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
956 r700->PA_SC_CLIPRECT_3_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
957 r700->PA_SC_CLIPRECT_3_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
958
959 /* more....2d clip */
960 SETbit(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
961 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, x1,
962 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask);
963 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, y1,
964 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask);
965 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, x2,
966 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask);
967 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, y2,
968 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask);
969
970 SETbit(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
971 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, x1,
972 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask);
973 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, y1,
974 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask);
975 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, x2,
976 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask);
977 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, y2,
978 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask);
979
980 r700->viewport[id].PA_SC_VPORT_ZMIN_0.u32All = 0;
981 r700->viewport[id].PA_SC_VPORT_ZMAX_0.u32All = 0x3F800000;
982 r700->viewport[id].enabled = GL_TRUE;
983 }
984
985 void r700SetRenderTarget(context_t *context, int id)
986 {
987 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
988
989 struct radeon_renderbuffer *rrb;
990 unsigned int nPitchInPixel;
991
992 /* screen/window/view */
993 SETfield(r700->CB_TARGET_MASK.u32All, 0xF, (4 * id), TARGET0_ENABLE_mask);
994
995 rrb = radeon_get_colorbuffer(&context->radeon);
996 if (!rrb || !rrb->bo) {
997 fprintf(stderr, "no rrb\n");
998 return;
999 }
1000
1001 /* color buffer */
1002 r700->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset;
1003
1004 nPitchInPixel = rrb->pitch/rrb->cpp;
1005 SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1,
1006 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
1007 SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
1008 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
1009 r700->render_target[id].CB_COLOR0_BASE.u32All = 0;
1010 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
1011 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL,
1012 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
1013 if(4 == rrb->cpp)
1014 {
1015 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_8_8_8_8,
1016 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
1017 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT, COMP_SWAP_shift, COMP_SWAP_mask);
1018 }
1019 else
1020 {
1021 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_5_6_5,
1022 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
1023 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT_REV,
1024 COMP_SWAP_shift, COMP_SWAP_mask);
1025 }
1026 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
1027 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit);
1028 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
1029
1030 r700->render_target[id].enabled = GL_TRUE;
1031 }
1032
1033 void r700SetDepthTarget(context_t *context)
1034 {
1035 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1036
1037 struct radeon_renderbuffer *rrb;
1038 unsigned int nPitchInPixel;
1039
1040 /* depth buf */
1041 r700->DB_DEPTH_SIZE.u32All = 0;
1042 r700->DB_DEPTH_BASE.u32All = 0;
1043 r700->DB_DEPTH_INFO.u32All = 0;
1044
1045 r700->DB_DEPTH_CLEAR.u32All = 0x3F800000;
1046 r700->DB_DEPTH_VIEW.u32All = 0;
1047 r700->DB_RENDER_CONTROL.u32All = 0;
1048 SETbit(r700->DB_RENDER_CONTROL.u32All, STENCIL_COMPRESS_DISABLE_bit);
1049 SETbit(r700->DB_RENDER_CONTROL.u32All, DEPTH_COMPRESS_DISABLE_bit);
1050 r700->DB_RENDER_OVERRIDE.u32All = 0;
1051 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1052 SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit);
1053 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
1054 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
1055 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
1056
1057 r700->DB_ALPHA_TO_MASK.u32All = 0;
1058 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask);
1059 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET1_shift, ALPHA_TO_MASK_OFFSET1_mask);
1060 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET2_shift, ALPHA_TO_MASK_OFFSET2_mask);
1061 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET3_shift, ALPHA_TO_MASK_OFFSET3_mask);
1062
1063 rrb = radeon_get_depthbuffer(&context->radeon);
1064 if (!rrb)
1065 return;
1066
1067 nPitchInPixel = rrb->pitch/rrb->cpp;
1068
1069 SETfield(r700->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1,
1070 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
1071 SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
1072 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */
1073
1074 if(4 == rrb->cpp)
1075 {
1076 switch (GL_CONTEXT(context)->Visual.depthBits)
1077 {
1078 case 16:
1079 case 24:
1080 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_8_24,
1081 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
1082 break;
1083 default:
1084 fprintf(stderr, "Error: Unsupported depth %d... exiting\n",
1085 GL_CONTEXT(context)->Visual.depthBits);
1086 _mesa_exit(-1);
1087 }
1088 }
1089 else
1090 {
1091 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16,
1092 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
1093 }
1094 SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_2D_TILED_THIN1,
1095 DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask);
1096 /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */
1097 }
1098
1099 static void r700InitSQConfig(GLcontext * ctx)
1100 {
1101 context_t *context = R700_CONTEXT(ctx);
1102 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1103 int ps_prio;
1104 int vs_prio;
1105 int gs_prio;
1106 int es_prio;
1107 int num_ps_gprs;
1108 int num_vs_gprs;
1109 int num_gs_gprs;
1110 int num_es_gprs;
1111 int num_temp_gprs;
1112 int num_ps_threads;
1113 int num_vs_threads;
1114 int num_gs_threads;
1115 int num_es_threads;
1116 int num_ps_stack_entries;
1117 int num_vs_stack_entries;
1118 int num_gs_stack_entries;
1119 int num_es_stack_entries;
1120
1121 // SQ
1122 ps_prio = 0;
1123 vs_prio = 1;
1124 gs_prio = 2;
1125 es_prio = 3;
1126 switch (context->radeon.radeonScreen->chip_family) {
1127 case CHIP_FAMILY_R600:
1128 num_ps_gprs = 192;
1129 num_vs_gprs = 56;
1130 num_temp_gprs = 4;
1131 num_gs_gprs = 0;
1132 num_es_gprs = 0;
1133 num_ps_threads = 136;
1134 num_vs_threads = 48;
1135 num_gs_threads = 4;
1136 num_es_threads = 4;
1137 num_ps_stack_entries = 128;
1138 num_vs_stack_entries = 128;
1139 num_gs_stack_entries = 0;
1140 num_es_stack_entries = 0;
1141 break;
1142 case CHIP_FAMILY_RV630:
1143 case CHIP_FAMILY_RV635:
1144 num_ps_gprs = 84;
1145 num_vs_gprs = 36;
1146 num_temp_gprs = 4;
1147 num_gs_gprs = 0;
1148 num_es_gprs = 0;
1149 num_ps_threads = 144;
1150 num_vs_threads = 40;
1151 num_gs_threads = 4;
1152 num_es_threads = 4;
1153 num_ps_stack_entries = 40;
1154 num_vs_stack_entries = 40;
1155 num_gs_stack_entries = 32;
1156 num_es_stack_entries = 16;
1157 break;
1158 case CHIP_FAMILY_RV610:
1159 case CHIP_FAMILY_RV620:
1160 case CHIP_FAMILY_RS780:
1161 default:
1162 num_ps_gprs = 84;
1163 num_vs_gprs = 36;
1164 num_temp_gprs = 4;
1165 num_gs_gprs = 0;
1166 num_es_gprs = 0;
1167 num_ps_threads = 136;
1168 num_vs_threads = 48;
1169 num_gs_threads = 4;
1170 num_es_threads = 4;
1171 num_ps_stack_entries = 40;
1172 num_vs_stack_entries = 40;
1173 num_gs_stack_entries = 32;
1174 num_es_stack_entries = 16;
1175 break;
1176 case CHIP_FAMILY_RV670:
1177 num_ps_gprs = 144;
1178 num_vs_gprs = 40;
1179 num_temp_gprs = 4;
1180 num_gs_gprs = 0;
1181 num_es_gprs = 0;
1182 num_ps_threads = 136;
1183 num_vs_threads = 48;
1184 num_gs_threads = 4;
1185 num_es_threads = 4;
1186 num_ps_stack_entries = 40;
1187 num_vs_stack_entries = 40;
1188 num_gs_stack_entries = 32;
1189 num_es_stack_entries = 16;
1190 break;
1191 case CHIP_FAMILY_RV770:
1192 num_ps_gprs = 192;
1193 num_vs_gprs = 56;
1194 num_temp_gprs = 4;
1195 num_gs_gprs = 0;
1196 num_es_gprs = 0;
1197 num_ps_threads = 188;
1198 num_vs_threads = 60;
1199 num_gs_threads = 0;
1200 num_es_threads = 0;
1201 num_ps_stack_entries = 256;
1202 num_vs_stack_entries = 256;
1203 num_gs_stack_entries = 0;
1204 num_es_stack_entries = 0;
1205 break;
1206 case CHIP_FAMILY_RV730:
1207 case CHIP_FAMILY_RV740:
1208 num_ps_gprs = 84;
1209 num_vs_gprs = 36;
1210 num_temp_gprs = 4;
1211 num_gs_gprs = 0;
1212 num_es_gprs = 0;
1213 num_ps_threads = 188;
1214 num_vs_threads = 60;
1215 num_gs_threads = 0;
1216 num_es_threads = 0;
1217 num_ps_stack_entries = 128;
1218 num_vs_stack_entries = 128;
1219 num_gs_stack_entries = 0;
1220 num_es_stack_entries = 0;
1221 break;
1222 case CHIP_FAMILY_RV710:
1223 num_ps_gprs = 192;
1224 num_vs_gprs = 56;
1225 num_temp_gprs = 4;
1226 num_gs_gprs = 0;
1227 num_es_gprs = 0;
1228 num_ps_threads = 144;
1229 num_vs_threads = 48;
1230 num_gs_threads = 0;
1231 num_es_threads = 0;
1232 num_ps_stack_entries = 128;
1233 num_vs_stack_entries = 128;
1234 num_gs_stack_entries = 0;
1235 num_es_stack_entries = 0;
1236 break;
1237 }
1238
1239 r700->sq_config.SQ_CONFIG.u32All = 0;
1240 if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
1241 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
1242 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
1243 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
1244 CLEARbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1245 else
1246 SETbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1247 SETbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit);
1248 SETbit(r700->sq_config.SQ_CONFIG.u32All, ALU_INST_PREFER_VECTOR_bit);
1249 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, PS_PRIO_shift, PS_PRIO_mask);
1250 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, VS_PRIO_shift, VS_PRIO_mask);
1251 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, GS_PRIO_shift, GS_PRIO_mask);
1252 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, ES_PRIO_shift, ES_PRIO_mask);
1253
1254 r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All = 0;
1255 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_ps_gprs, NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
1256 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_vs_gprs, NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
1257 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_temp_gprs,
1258 NUM_CLAUSE_TEMP_GPRS_shift, NUM_CLAUSE_TEMP_GPRS_mask);
1259
1260 r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All = 0;
1261 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_gs_gprs, NUM_GS_GPRS_shift, NUM_GS_GPRS_mask);
1262 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_es_gprs, NUM_ES_GPRS_shift, NUM_ES_GPRS_mask);
1263
1264 r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All = 0;
1265 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_ps_threads,
1266 NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
1267 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_vs_threads,
1268 NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
1269 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_gs_threads,
1270 NUM_GS_THREADS_shift, NUM_GS_THREADS_mask);
1271 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_es_threads,
1272 NUM_ES_THREADS_shift, NUM_ES_THREADS_mask);
1273
1274 r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All = 0;
1275 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_ps_stack_entries,
1276 NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
1277 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_vs_stack_entries,
1278 NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
1279
1280 r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All = 0;
1281 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_gs_stack_entries,
1282 NUM_GS_STACK_ENTRIES_shift, NUM_GS_STACK_ENTRIES_mask);
1283 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_es_stack_entries,
1284 NUM_ES_STACK_ENTRIES_shift, NUM_ES_STACK_ENTRIES_mask);
1285
1286 }
1287
1288 /**
1289 * Calculate initial hardware state and register state functions.
1290 * Assumes that the command buffer and state atoms have been
1291 * initialized already.
1292 */
1293 void r700InitState(GLcontext * ctx) //-------------------
1294 {
1295 context_t *context = R700_CONTEXT(ctx);
1296
1297 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1298
1299 r700->TA_CNTL_AUX.u32All = 0;
1300 SETfield(r700->TA_CNTL_AUX.u32All, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask);
1301 r700->VC_ENHANCE.u32All = 0;
1302 r700->DB_WATERMARKS.u32All = 0;
1303 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_FREE_shift, DEPTH_FREE_mask);
1304 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_FLUSH_shift, DEPTH_FLUSH_mask);
1305 SETfield(r700->DB_WATERMARKS.u32All, 0, FORCE_SUMMARIZE_shift, FORCE_SUMMARIZE_mask);
1306 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_PENDING_FREE_shift, DEPTH_PENDING_FREE_mask);
1307 r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All = 0;
1308 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1309 SETfield(r700->TA_CNTL_AUX.u32All, 3, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1310 r700->DB_DEBUG.u32All = 0x82000000;
1311 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1312 } else {
1313 SETfield(r700->TA_CNTL_AUX.u32All, 2, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1314 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1315 SETbit(r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All, VS_PC_LIMIT_ENABLE_bit);
1316 }
1317
1318 /* Turn off vgt reuse */
1319 r700->VGT_REUSE_OFF.u32All = 0;
1320 SETbit(r700->VGT_REUSE_OFF.u32All, REUSE_OFF_bit);
1321
1322 /* Specify offsetting and clamp values for vertices */
1323 r700->VGT_MAX_VTX_INDX.u32All = 0xFFFFFF;
1324 r700->VGT_MIN_VTX_INDX.u32All = 0;
1325 r700->VGT_INDX_OFFSET.u32All = 0;
1326
1327 /* Specify the number of instances */
1328 r700->VGT_DMA_NUM_INSTANCES.u32All = 1;
1329
1330 /* not alpha blend */
1331 CLEARfield(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_FUNC_mask);
1332 CLEARbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
1333
1334 /* default shader connections. */
1335 r700->SPI_VS_OUT_ID_0.u32All = 0x03020100;
1336 r700->SPI_VS_OUT_ID_1.u32All = 0x07060504;
1337
1338 r700->SPI_PS_INPUT_CNTL_0.u32All = 0x00000800;
1339 r700->SPI_PS_INPUT_CNTL_1.u32All = 0x00000801;
1340 r700->SPI_PS_INPUT_CNTL_2.u32All = 0x00000802;
1341
1342 r700->SPI_THREAD_GROUPING.u32All = 0;
1343 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
1344 SETfield(r700->SPI_THREAD_GROUPING.u32All, 1, PS_GROUPING_shift, PS_GROUPING_mask);
1345
1346 r700SetBlendState(ctx);
1347 r700SetLogicOpState(ctx);
1348
1349 r700->DB_SHADER_CONTROL.u32All = 0;
1350 SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
1351
1352 /* Set up the culling control register */
1353 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1354 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1355 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1356 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1357
1358 /* screen */
1359 r700->PA_SC_SCREEN_SCISSOR_TL.u32All = 0x0;
1360
1361 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All,
1362 ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->width,
1363 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask);
1364 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All,
1365 ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->height,
1366 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask);
1367
1368 /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
1369 r700->PA_SC_CLIPRECT_RULE.u32All = 0;
1370 SETfield(r700->PA_SC_CLIPRECT_RULE.u32All, CLIP_RULE_mask, CLIP_RULE_shift, CLIP_RULE_mask);
1371
1372 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1373 r700->PA_SC_EDGERULE.u32All = 0;
1374 else
1375 r700->PA_SC_EDGERULE.u32All = 0xAAAAAAAA;
1376
1377 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1378 r700->PA_SC_MODE_CNTL.u32All = 0;
1379 SETbit(r700->PA_SC_MODE_CNTL.u32All, WALK_ORDER_ENABLE_bit);
1380 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1381 } else {
1382 r700->PA_SC_MODE_CNTL.u32All = 0x00500000;
1383 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_REZ_ENABLE_bit);
1384 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1385 }
1386
1387 /* Do scale XY and Z by 1/W0. */
1388 r700->bEnablePerspective = GL_TRUE;
1389 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
1390 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
1391 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
1392
1393 /* Enable viewport scaling for all three axis */
1394 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_SCALE_ENA_bit);
1395 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_OFFSET_ENA_bit);
1396 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_SCALE_ENA_bit);
1397 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_OFFSET_ENA_bit);
1398 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_SCALE_ENA_bit);
1399 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_OFFSET_ENA_bit);
1400
1401 /* Set up point sizes and min/max values */
1402 SETfield(r700->PA_SU_POINT_SIZE.u32All, 0x8,
1403 PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask);
1404 SETfield(r700->PA_SU_POINT_SIZE.u32All, 0x8,
1405 PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask);
1406 CLEARfield(r700->PA_SU_POINT_MINMAX.u32All, MIN_SIZE_mask);
1407 SETfield(r700->PA_SU_POINT_MINMAX.u32All, 0x8000, MAX_SIZE_shift, MAX_SIZE_mask);
1408
1409 /* Set up line control */
1410 SETfield(r700->PA_SU_LINE_CNTL.u32All, 0x8,
1411 PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
1412
1413 r700->PA_SC_LINE_CNTL.u32All = 0;
1414 CLEARbit(r700->PA_SC_LINE_CNTL.u32All, EXPAND_LINE_WIDTH_bit);
1415 SETbit(r700->PA_SC_LINE_CNTL.u32All, LAST_PIXEL_bit);
1416
1417 /* Set up vertex control */
1418 r700->PA_SU_VTX_CNTL.u32All = 0;
1419 CLEARfield(r700->PA_SU_VTX_CNTL.u32All, QUANT_MODE_mask);
1420 SETbit(r700->PA_SU_VTX_CNTL.u32All, PIX_CENTER_bit);
1421 SETfield(r700->PA_SU_VTX_CNTL.u32All, X_ROUND_TO_EVEN,
1422 PA_SU_VTX_CNTL__ROUND_MODE_shift, PA_SU_VTX_CNTL__ROUND_MODE_mask);
1423
1424 /* to 1.0 = no guard band */
1425 r700->PA_CL_GB_VERT_CLIP_ADJ.u32All = 0x3F800000; /* 1.0 */
1426 r700->PA_CL_GB_VERT_DISC_ADJ.u32All = 0x3F800000;
1427 r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All = 0x3F800000;
1428 r700->PA_CL_GB_HORZ_DISC_ADJ.u32All = 0x3F800000;
1429
1430 /* CB */
1431 r700->CB_CLEAR_RED_R6XX.f32All = 1.0; //r6xx only
1432 r700->CB_CLEAR_GREEN_R6XX.f32All = 0.0; //r6xx only
1433 r700->CB_CLEAR_BLUE_R6XX.f32All = 1.0; //r6xx only
1434 r700->CB_CLEAR_ALPHA_R6XX.f32All = 1.0; //r6xx only
1435 r700->CB_FOG_RED_R6XX.u32All = 0; //r6xx only
1436 r700->CB_FOG_GREEN_R6XX.u32All = 0; //r6xx only
1437 r700->CB_FOG_BLUE_R6XX.u32All = 0; //r6xx only
1438
1439 /* Disable color compares */
1440 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1441 CLRCMP_FCN_SRC_shift, CLRCMP_FCN_SRC_mask);
1442 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1443 CLRCMP_FCN_DST_shift, CLRCMP_FCN_DST_mask);
1444 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_SEL_SRC,
1445 CLRCMP_FCN_SEL_shift, CLRCMP_FCN_SEL_mask);
1446
1447 /* Zero out source */
1448 r700->CB_CLRCMP_SRC.u32All = 0x00000000;
1449
1450 /* Put a compare color in for error checking */
1451 r700->CB_CLRCMP_DST.u32All = 0x000000FF;
1452
1453 /* Set up color compare mask */
1454 r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF;
1455
1456 /* default color mask */
1457 SETfield(r700->CB_SHADER_MASK.u32All, 0xF, OUTPUT0_ENABLE_shift, OUTPUT0_ENABLE_mask);
1458
1459 /* Enable all samples for multi-sample anti-aliasing */
1460 r700->PA_SC_AA_MASK.u32All = 0xFFFFFFFF;
1461 /* Turn off AA */
1462 r700->PA_SC_AA_CONFIG.u32All = 0;
1463
1464 r700->SX_MISC.u32All = 0;
1465
1466 r700InitSQConfig(ctx);
1467 }
1468
1469 void r700InitStateFuncs(struct dd_function_table *functions) //-----------------
1470 {
1471 functions->UpdateState = r700InvalidateState;
1472 functions->AlphaFunc = r700AlphaFunc;
1473 functions->BlendColor = r700BlendColor;
1474 functions->BlendEquationSeparate = r700BlendEquationSeparate;
1475 functions->BlendFuncSeparate = r700BlendFuncSeparate;
1476 functions->Enable = r700Enable;
1477 functions->ColorMask = r700ColorMask;
1478 functions->DepthFunc = r700DepthFunc;
1479 functions->DepthMask = r700DepthMask;
1480 functions->CullFace = r700CullFace;
1481 functions->Fogfv = r700Fogfv;
1482 functions->FrontFace = r700FrontFace;
1483 functions->ShadeModel = r700ShadeModel;
1484 functions->LogicOpcode = r700LogicOpcode;
1485
1486 /* ARB_point_parameters */
1487 functions->PointParameterfv = r700PointParameter;
1488
1489 /* Stencil related */
1490 functions->StencilFuncSeparate = r700StencilFuncSeparate;
1491 functions->StencilMaskSeparate = r700StencilMaskSeparate;
1492 functions->StencilOpSeparate = r700StencilOpSeparate;
1493
1494 /* Viewport related */
1495 functions->Viewport = r700Viewport;
1496 functions->DepthRange = r700DepthRange;
1497 functions->PointSize = r700PointSize;
1498 functions->LineWidth = r700LineWidth;
1499 functions->LineStipple = r700LineStipple;
1500
1501 functions->PolygonOffset = r700PolygonOffset;
1502 functions->PolygonMode = r700PolygonMode;
1503
1504 functions->RenderMode = r700RenderMode;
1505
1506 functions->ClipPlane = r700ClipPlane;
1507
1508 functions->Scissor = radeonScissor;
1509
1510 functions->DrawBuffer = radeonDrawBuffer;
1511 functions->ReadBuffer = radeonReadBuffer;
1512
1513 }
1514