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r600: fix flat shading
[mesa.git] / src / mesa / drivers / dri / r600 / r700_state.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/context.h"
34 #include "main/dd.h"
35 #include "main/simple_list.h"
36
37 #include "tnl/tnl.h"
38 #include "tnl/t_pipeline.h"
39 #include "tnl/t_vp_build.h"
40 #include "swrast/swrast.h"
41 #include "swrast_setup/swrast_setup.h"
42 #include "main/api_arrayelt.h"
43 #include "main/state.h"
44 #include "main/framebuffer.h"
45
46 #include "shader/prog_parameter.h"
47 #include "shader/prog_statevars.h"
48 #include "vbo/vbo.h"
49 #include "main/texformat.h"
50
51 #include "r600_context.h"
52
53 #include "r700_state.h"
54
55 #include "r700_fragprog.h"
56 #include "r700_vertprog.h"
57
58
59 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state);
60 static void r700UpdatePolygonMode(GLcontext * ctx);
61 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state);
62 static void r700SetStencilState(GLcontext * ctx, GLboolean state);
63
64 void r700SetDefaultStates(context_t *context) //--------------------
65 {
66
67 }
68
69 void r700UpdateShaders (GLcontext * ctx) //----------------------------------
70 {
71 context_t *context = R700_CONTEXT(ctx);
72
73 GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
74 GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
75 int i;
76
77 if (ctx->FragmentProgram._Current) {
78 struct r700_fragment_program *fp = (struct r700_fragment_program *)
79 (ctx->FragmentProgram._Current);
80 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
81 {
82 fp->r700AsmCode.bR6xx = 1;
83 }
84
85 if(GL_FALSE == fp->translated)
86 {
87 if( GL_FALSE == r700TranslateFragmentShader(fp, &(fp->mesa_program)) )
88 {
89 //return GL_TRUE;
90 }
91 }
92 }
93
94 if (context->radeon.NewGLState)
95 {
96 struct r700_vertex_program *vp;
97 context->radeon.NewGLState = 0;
98
99 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++)
100 {
101 /* mat states from state var not array for sw */
102 dummy_attrib[i].stride = 0;
103
104 temp_attrib[i] = TNL_CONTEXT(ctx)->vb.AttribPtr[i];
105 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = &(dummy_attrib[i]);
106 }
107
108 _tnl_UpdateFixedFunctionProgram(ctx);
109
110 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++)
111 {
112 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = temp_attrib[i];
113 }
114
115 r700SelectVertexShader(ctx);
116 vp = (struct r700_vertex_program *)ctx->VertexProgram._Current;
117
118 if (vp->translated == GL_FALSE)
119 {
120 // TODO
121 //fprintf(stderr, "Failing back to sw-tcl\n");
122 //hw_tcl_on = future_hw_tcl_on = 0;
123 //r300ResetHwState(rmesa);
124 //
125 r700UpdateStateParameters(ctx, _NEW_PROGRAM);
126 return;
127 }
128 }
129
130 r700UpdateStateParameters(ctx, _NEW_PROGRAM);
131 }
132
133 /*
134 * To correctly position primitives:
135 */
136 void r700UpdateViewportOffset(GLcontext * ctx) //------------------
137 {
138 context_t *context = R700_CONTEXT(ctx);
139 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
140 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
141 GLfloat xoffset = (GLfloat) dPriv->x;
142 GLfloat yoffset = (GLfloat) dPriv->y + dPriv->h;
143 const GLfloat *v = ctx->Viewport._WindowMap.m;
144 int id = 0;
145
146 GLfloat tx = v[MAT_TX] + xoffset;
147 GLfloat ty = (-v[MAT_TY]) + yoffset;
148
149 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
150 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
151
152 radeonUpdateScissor(ctx);
153 }
154
155 /**
156 * Tell the card where to render (offset, pitch).
157 * Effected by glDrawBuffer, etc
158 */
159 void r700UpdateDrawBuffer(GLcontext * ctx) /* TODO */ //---------------------
160 {
161 #if 0 /* to be enabled */
162 context_t *context = R700_CONTEXT(ctx);
163
164 switch (ctx->DrawBuffer->_ColorDrawBufferIndexes[0])
165 {
166 case BUFFER_FRONT_LEFT:
167 context->target.rt = context->screen->frontBuffer;
168 break;
169 case BUFFER_BACK_LEFT:
170 context->target.rt = context->screen->backBuffer;
171 break;
172 default:
173 memset (&context->target.rt, sizeof(context->target.rt), 0);
174 }
175 #endif /* to be enabled */
176 }
177
178 static void r700FetchStateParameter(GLcontext * ctx,
179 const gl_state_index state[STATE_LENGTH],
180 GLfloat * value)
181 {
182 context_t *context = R700_CONTEXT(ctx);
183
184 /* TODO */
185 }
186
187 void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state) //--------------------
188 {
189 struct r700_fragment_program *fp;
190 struct gl_program_parameter_list *paramList;
191 GLuint i;
192
193 if (!(new_state & (_NEW_BUFFERS | _NEW_PROGRAM)))
194 return;
195
196 fp = (struct r700_fragment_program *)ctx->FragmentProgram._Current;
197 if (!fp)
198 {
199 return;
200 }
201
202 paramList = fp->mesa_program.Base.Parameters;
203
204 if (!paramList)
205 {
206 return;
207 }
208
209 for (i = 0; i < paramList->NumParameters; i++)
210 {
211 if (paramList->Parameters[i].Type == PROGRAM_STATE_VAR)
212 {
213 r700FetchStateParameter(ctx,
214 paramList->Parameters[i].
215 StateIndexes,
216 paramList->ParameterValues[i]);
217 }
218 }
219 }
220
221 /**
222 * Called by Mesa after an internal state update.
223 */
224 static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //-------------------
225 {
226 context_t *context = R700_CONTEXT(ctx);
227
228 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
229
230 _swrast_InvalidateState(ctx, new_state);
231 _swsetup_InvalidateState(ctx, new_state);
232 _vbo_InvalidateState(ctx, new_state);
233 _tnl_InvalidateState(ctx, new_state);
234 _ae_invalidate_state(ctx, new_state);
235
236 if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL))
237 {
238 _mesa_update_framebuffer(ctx);
239 /* this updates the DrawBuffer's Width/Height if it's a FBO */
240 _mesa_update_draw_buffer_bounds(ctx);
241
242 r700UpdateDrawBuffer(ctx);
243 }
244
245 r700UpdateStateParameters(ctx, new_state);
246
247 if(GL_TRUE == r700->bEnablePerspective)
248 {
249 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
250 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
251 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
252
253 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
254
255 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
256 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
257 }
258 else
259 {
260 /* For orthogonal case. */
261 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
262 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
263
264 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
265
266 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
267 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
268 }
269
270 context->radeon.NewGLState |= new_state;
271 }
272
273 static void r700SetDepthState(GLcontext * ctx)
274 {
275 context_t *context = R700_CONTEXT(ctx);
276
277 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
278
279 if (ctx->Depth.Test)
280 {
281 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
282 if (ctx->Depth.Mask)
283 {
284 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
285 }
286 else
287 {
288 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
289 }
290
291 switch (ctx->Depth.Func)
292 {
293 case GL_NEVER:
294 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NEVER,
295 ZFUNC_shift, ZFUNC_mask);
296 break;
297 case GL_LESS:
298 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LESS,
299 ZFUNC_shift, ZFUNC_mask);
300 break;
301 case GL_EQUAL:
302 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_EQUAL,
303 ZFUNC_shift, ZFUNC_mask);
304 break;
305 case GL_LEQUAL:
306 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LEQUAL,
307 ZFUNC_shift, ZFUNC_mask);
308 break;
309 case GL_GREATER:
310 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GREATER,
311 ZFUNC_shift, ZFUNC_mask);
312 break;
313 case GL_NOTEQUAL:
314 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NOTEQUAL,
315 ZFUNC_shift, ZFUNC_mask);
316 break;
317 case GL_GEQUAL:
318 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GEQUAL,
319 ZFUNC_shift, ZFUNC_mask);
320 break;
321 case GL_ALWAYS:
322 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
323 ZFUNC_shift, ZFUNC_mask);
324 break;
325 default:
326 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
327 ZFUNC_shift, ZFUNC_mask);
328 break;
329 }
330 }
331 else
332 {
333 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
334 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
335 }
336 }
337
338 static void r700SetAlphaState(GLcontext * ctx)
339 {
340 context_t *context = R700_CONTEXT(ctx);
341 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
342 uint32_t alpha_func = REF_ALWAYS;
343 GLboolean really_enabled = ctx->Color.AlphaEnabled;
344
345 switch (ctx->Color.AlphaFunc) {
346 case GL_NEVER:
347 alpha_func = REF_NEVER;
348 break;
349 case GL_LESS:
350 alpha_func = REF_LESS;
351 break;
352 case GL_EQUAL:
353 alpha_func = REF_EQUAL;
354 break;
355 case GL_LEQUAL:
356 alpha_func = REF_LEQUAL;
357 break;
358 case GL_GREATER:
359 alpha_func = REF_GREATER;
360 break;
361 case GL_NOTEQUAL:
362 alpha_func = REF_NOTEQUAL;
363 break;
364 case GL_GEQUAL:
365 alpha_func = REF_GEQUAL;
366 break;
367 case GL_ALWAYS:
368 /*alpha_func = REF_ALWAYS; */
369 really_enabled = GL_FALSE;
370 break;
371 }
372
373 if (really_enabled) {
374 SETfield(r700->SX_ALPHA_TEST_CONTROL.u32All, alpha_func,
375 ALPHA_FUNC_shift, ALPHA_FUNC_mask);
376 SETbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
377 r700->SX_ALPHA_REF.f32All = ctx->Color.AlphaRef;
378 } else {
379 CLEARbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
380 }
381
382 }
383
384 static void r700AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref) //---------------
385 {
386 (void)func;
387 (void)ref;
388 r700SetAlphaState(ctx);
389 }
390
391
392 static void r700BlendColor(GLcontext * ctx, const GLfloat cf[4]) //----------------
393 {
394 context_t *context = R700_CONTEXT(ctx);
395 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
396
397 r700->CB_BLEND_RED.f32All = cf[0];
398 r700->CB_BLEND_GREEN.f32All = cf[1];
399 r700->CB_BLEND_BLUE.f32All = cf[2];
400 r700->CB_BLEND_ALPHA.f32All = cf[3];
401 }
402
403 static int blend_factor(GLenum factor, GLboolean is_src)
404 {
405 switch (factor) {
406 case GL_ZERO:
407 return BLEND_ZERO;
408 break;
409 case GL_ONE:
410 return BLEND_ONE;
411 break;
412 case GL_DST_COLOR:
413 return BLEND_DST_COLOR;
414 break;
415 case GL_ONE_MINUS_DST_COLOR:
416 return BLEND_ONE_MINUS_DST_COLOR;
417 break;
418 case GL_SRC_COLOR:
419 return BLEND_SRC_COLOR;
420 break;
421 case GL_ONE_MINUS_SRC_COLOR:
422 return BLEND_ONE_MINUS_SRC_COLOR;
423 break;
424 case GL_SRC_ALPHA:
425 return BLEND_SRC_ALPHA;
426 break;
427 case GL_ONE_MINUS_SRC_ALPHA:
428 return BLEND_ONE_MINUS_SRC_ALPHA;
429 break;
430 case GL_DST_ALPHA:
431 return BLEND_DST_ALPHA;
432 break;
433 case GL_ONE_MINUS_DST_ALPHA:
434 return BLEND_ONE_MINUS_DST_ALPHA;
435 break;
436 case GL_SRC_ALPHA_SATURATE:
437 return (is_src) ? BLEND_SRC_ALPHA_SATURATE : BLEND_ZERO;
438 break;
439 case GL_CONSTANT_COLOR:
440 return BLEND_CONSTANT_COLOR;
441 break;
442 case GL_ONE_MINUS_CONSTANT_COLOR:
443 return BLEND_ONE_MINUS_CONSTANT_COLOR;
444 break;
445 case GL_CONSTANT_ALPHA:
446 return BLEND_CONSTANT_ALPHA;
447 break;
448 case GL_ONE_MINUS_CONSTANT_ALPHA:
449 return BLEND_ONE_MINUS_CONSTANT_ALPHA;
450 break;
451 default:
452 fprintf(stderr, "unknown blend factor %x\n", factor);
453 return (is_src) ? BLEND_ONE : BLEND_ZERO;
454 break;
455 }
456 }
457
458 static void r700SetBlendState(GLcontext * ctx)
459 {
460 context_t *context = R700_CONTEXT(ctx);
461 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
462 int id = 0;
463 uint32_t blend_reg = 0, eqn, eqnA;
464
465 if (RGBA_LOGICOP_ENABLED(ctx) || !ctx->Color.BlendEnabled) {
466 SETfield(blend_reg,
467 BLEND_ONE, COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
468 SETfield(blend_reg,
469 BLEND_ZERO, COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
470 SETfield(blend_reg,
471 COMB_DST_PLUS_SRC, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
472 SETfield(blend_reg,
473 BLEND_ONE, ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
474 SETfield(blend_reg,
475 BLEND_ZERO, ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
476 SETfield(blend_reg,
477 COMB_DST_PLUS_SRC, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
478 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
479 r700->CB_BLEND_CONTROL.u32All = blend_reg;
480 else
481 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
482 return;
483 }
484
485 SETfield(blend_reg,
486 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
487 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
488 SETfield(blend_reg,
489 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
490 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
491
492 switch (ctx->Color.BlendEquationRGB) {
493 case GL_FUNC_ADD:
494 eqn = COMB_DST_PLUS_SRC;
495 break;
496 case GL_FUNC_SUBTRACT:
497 eqn = COMB_SRC_MINUS_DST;
498 break;
499 case GL_FUNC_REVERSE_SUBTRACT:
500 eqn = COMB_DST_MINUS_SRC;
501 break;
502 case GL_MIN:
503 eqn = COMB_MIN_DST_SRC;
504 SETfield(blend_reg,
505 BLEND_ONE,
506 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
507 SETfield(blend_reg,
508 BLEND_ONE,
509 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
510 break;
511 case GL_MAX:
512 eqn = COMB_MAX_DST_SRC;
513 SETfield(blend_reg,
514 BLEND_ONE,
515 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
516 SETfield(blend_reg,
517 BLEND_ONE,
518 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
519 break;
520
521 default:
522 fprintf(stderr,
523 "[%s:%u] Invalid RGB blend equation (0x%04x).\n",
524 __FUNCTION__, __LINE__, ctx->Color.BlendEquationRGB);
525 return;
526 }
527 SETfield(blend_reg,
528 eqn, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
529
530 SETfield(blend_reg,
531 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
532 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
533 SETfield(blend_reg,
534 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
535 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
536
537 switch (ctx->Color.BlendEquationA) {
538 case GL_FUNC_ADD:
539 eqnA = COMB_DST_PLUS_SRC;
540 break;
541 case GL_FUNC_SUBTRACT:
542 eqnA = COMB_SRC_MINUS_DST;
543 break;
544 case GL_FUNC_REVERSE_SUBTRACT:
545 eqnA = COMB_DST_MINUS_SRC;
546 break;
547 case GL_MIN:
548 eqnA = COMB_MIN_DST_SRC;
549 SETfield(blend_reg,
550 BLEND_ONE,
551 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
552 SETfield(blend_reg,
553 BLEND_ONE,
554 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
555 break;
556 case GL_MAX:
557 eqnA = COMB_MAX_DST_SRC;
558 SETfield(blend_reg,
559 BLEND_ONE,
560 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
561 SETfield(blend_reg,
562 BLEND_ONE,
563 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
564 break;
565 default:
566 fprintf(stderr,
567 "[%s:%u] Invalid A blend equation (0x%04x).\n",
568 __FUNCTION__, __LINE__, ctx->Color.BlendEquationA);
569 return;
570 }
571
572 SETfield(blend_reg,
573 eqnA, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
574
575 SETbit(blend_reg, SEPARATE_ALPHA_BLEND_bit);
576
577 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
578 r700->CB_BLEND_CONTROL.u32All = blend_reg;
579 else {
580 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
581 SETbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit);
582 }
583 SETfield(r700->CB_COLOR_CONTROL.u32All, (1 << id),
584 TARGET_BLEND_ENABLE_shift, TARGET_BLEND_ENABLE_mask);
585
586 }
587
588 static void r700BlendEquationSeparate(GLcontext * ctx,
589 GLenum modeRGB, GLenum modeA) //-----------------
590 {
591 r700SetBlendState(ctx);
592 }
593
594 static void r700BlendFuncSeparate(GLcontext * ctx,
595 GLenum sfactorRGB, GLenum dfactorRGB,
596 GLenum sfactorA, GLenum dfactorA) //------------------------
597 {
598 r700SetBlendState(ctx);
599 }
600
601 /**
602 * Translate LogicOp enums into hardware representation.
603 * Both use a very logical bit-wise layout, but unfortunately the order
604 * of bits is reversed.
605 */
606 static GLuint translate_logicop(GLenum logicop)
607 {
608 GLuint bits = logicop - GL_CLEAR;
609 bits = ((bits & 1) << 3) | ((bits & 2) << 1) | ((bits & 4) >> 1) | ((bits & 8) >> 3);
610 return bits;
611 }
612
613 /**
614 * Used internally to update the r300->hw hardware state to match the
615 * current OpenGL state.
616 */
617 static void r700SetLogicOpState(GLcontext *ctx)
618 {
619 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
620
621 if (RGBA_LOGICOP_ENABLED(ctx))
622 SETfield(r700->CB_COLOR_CONTROL.u32All,
623 translate_logicop(ctx->Color.LogicOp), ROP3_shift, ROP3_mask);
624 else
625 SETfield(r700->CB_COLOR_CONTROL.u32All, 0xCC, ROP3_shift, ROP3_mask);
626 }
627
628 /**
629 * Called by Mesa when an application program changes the LogicOp state
630 * via glLogicOp.
631 */
632 static void r700LogicOpcode(GLcontext *ctx, GLenum logicop)
633 {
634 if (RGBA_LOGICOP_ENABLED(ctx))
635 r700SetLogicOpState(ctx);
636 }
637
638 static void r700UpdateCulling(GLcontext * ctx)
639 {
640 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
641
642 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
643 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
644 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
645
646 if (ctx->Polygon.CullFlag)
647 {
648 switch (ctx->Polygon.CullFaceMode)
649 {
650 case GL_FRONT:
651 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
652 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
653 break;
654 case GL_BACK:
655 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
656 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
657 break;
658 case GL_FRONT_AND_BACK:
659 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
660 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
661 break;
662 default:
663 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
664 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
665 break;
666 }
667 }
668
669 switch (ctx->Polygon.FrontFace)
670 {
671 case GL_CW:
672 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
673 break;
674 case GL_CCW:
675 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
676 break;
677 default:
678 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); /* default: ccw */
679 break;
680 }
681 }
682
683 static void r700UpdateLineStipple(GLcontext * ctx)
684 {
685 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
686 if (ctx->Line.StippleFlag)
687 {
688 SETbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
689 }
690 else
691 {
692 CLEARbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
693 }
694 }
695
696 static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //------------------
697 {
698 context_t *context = R700_CONTEXT(ctx);
699
700 switch (cap) {
701 case GL_TEXTURE_1D:
702 case GL_TEXTURE_2D:
703 case GL_TEXTURE_3D:
704 /* empty */
705 break;
706 case GL_FOG:
707 /* empty */
708 break;
709 case GL_ALPHA_TEST:
710 r700SetAlphaState(ctx);
711 break;
712 case GL_COLOR_LOGIC_OP:
713 r700SetLogicOpState(ctx);
714 /* fall-through, because logic op overrides blending */
715 case GL_BLEND:
716 r700SetBlendState(ctx);
717 break;
718 case GL_CLIP_PLANE0:
719 case GL_CLIP_PLANE1:
720 case GL_CLIP_PLANE2:
721 case GL_CLIP_PLANE3:
722 case GL_CLIP_PLANE4:
723 case GL_CLIP_PLANE5:
724 r700SetClipPlaneState(ctx, cap, state);
725 break;
726 case GL_DEPTH_TEST:
727 r700SetDepthState(ctx);
728 break;
729 case GL_STENCIL_TEST:
730 r700SetStencilState(ctx, state);
731 break;
732 case GL_CULL_FACE:
733 r700UpdateCulling(ctx);
734 break;
735 case GL_POLYGON_OFFSET_POINT:
736 case GL_POLYGON_OFFSET_LINE:
737 case GL_POLYGON_OFFSET_FILL:
738 r700SetPolygonOffsetState(ctx, state);
739 break;
740 case GL_SCISSOR_TEST:
741 radeon_firevertices(&context->radeon);
742 context->radeon.state.scissor.enabled = state;
743 radeonUpdateScissor(ctx);
744 break;
745 case GL_LINE_STIPPLE:
746 r700UpdateLineStipple(ctx);
747 break;
748 default:
749 break;
750 }
751
752 }
753
754 /**
755 * Handle glColorMask()
756 */
757 static void r700ColorMask(GLcontext * ctx,
758 GLboolean r, GLboolean g, GLboolean b, GLboolean a) //------------------
759 {
760 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
761 unsigned int mask = ((r ? 1 : 0) |
762 (g ? 2 : 0) |
763 (b ? 4 : 0) |
764 (a ? 8 : 0));
765
766 if (mask != r700->CB_SHADER_MASK.u32All)
767 SETfield(r700->CB_SHADER_MASK.u32All, mask, OUTPUT0_ENABLE_shift, OUTPUT0_ENABLE_mask);
768 }
769
770 /**
771 * Change the depth testing function.
772 *
773 * \note Mesa already filters redundant calls to this function.
774 */
775 static void r700DepthFunc(GLcontext * ctx, GLenum func) //--------------------
776 {
777 r700SetDepthState(ctx);
778 }
779
780 /**
781 * Enable/Disable depth writing.
782 *
783 * \note Mesa already filters redundant calls to this function.
784 */
785 static void r700DepthMask(GLcontext * ctx, GLboolean mask) //------------------
786 {
787 r700SetDepthState(ctx);
788 }
789
790 /**
791 * Change the culling mode.
792 *
793 * \note Mesa already filters redundant calls to this function.
794 */
795 static void r700CullFace(GLcontext * ctx, GLenum mode) //-----------------
796 {
797 r700UpdateCulling(ctx);
798 }
799
800 /* =============================================================
801 * Fog
802 */
803 static void r700Fogfv(GLcontext * ctx, GLenum pname, const GLfloat * param) //--------------
804 {
805 }
806
807 /**
808 * Change the polygon orientation.
809 *
810 * \note Mesa already filters redundant calls to this function.
811 */
812 static void r700FrontFace(GLcontext * ctx, GLenum mode) //------------------
813 {
814 r700UpdateCulling(ctx);
815 r700UpdatePolygonMode(ctx);
816 }
817
818 static void r700ShadeModel(GLcontext * ctx, GLenum mode) //--------------------
819 {
820 context_t *context = R700_CONTEXT(ctx);
821 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
822
823 /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */
824 switch (mode) {
825 case GL_FLAT:
826 SETbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
827 break;
828 case GL_SMOOTH:
829 CLEARbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
830 break;
831 default:
832 return;
833 }
834 }
835
836 /* =============================================================
837 * Point state
838 */
839 static void r700PointSize(GLcontext * ctx, GLfloat size)
840 {
841 context_t *context = R700_CONTEXT(ctx);
842 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
843
844 /* We need to clamp to user defined range here, because
845 * the HW clamping happens only for per vertex point size. */
846 size = CLAMP(size, ctx->Point.MinSize, ctx->Point.MaxSize);
847
848 /* same size limits for AA, non-AA points */
849 size = CLAMP(size, ctx->Const.MinPointSize, ctx->Const.MaxPointSize);
850
851 /* format is 12.4 fixed point */
852 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 16),
853 PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask);
854 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 16),
855 PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask);
856
857 }
858
859 static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * param) //---------------
860 {
861 context_t *context = R700_CONTEXT(ctx);
862 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
863
864 /* format is 12.4 fixed point */
865 switch (pname) {
866 case GL_POINT_SIZE_MIN:
867 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MinSize * 16.0),
868 MIN_SIZE_shift, MIN_SIZE_mask);
869 break;
870 case GL_POINT_SIZE_MAX:
871 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MaxSize * 16.0),
872 MAX_SIZE_shift, MAX_SIZE_mask);
873 break;
874 case GL_POINT_DISTANCE_ATTENUATION:
875 break;
876 case GL_POINT_FADE_THRESHOLD_SIZE:
877 break;
878 default:
879 break;
880 }
881 }
882
883 static int translate_stencil_func(int func)
884 {
885 switch (func) {
886 case GL_NEVER:
887 return REF_NEVER;
888 case GL_LESS:
889 return REF_LESS;
890 case GL_EQUAL:
891 return REF_EQUAL;
892 case GL_LEQUAL:
893 return REF_LEQUAL;
894 case GL_GREATER:
895 return REF_GREATER;
896 case GL_NOTEQUAL:
897 return REF_NOTEQUAL;
898 case GL_GEQUAL:
899 return REF_GEQUAL;
900 case GL_ALWAYS:
901 return REF_ALWAYS;
902 }
903 return 0;
904 }
905
906 static int translate_stencil_op(int op)
907 {
908 switch (op) {
909 case GL_KEEP:
910 return STENCIL_KEEP;
911 case GL_ZERO:
912 return STENCIL_ZERO;
913 case GL_REPLACE:
914 return STENCIL_REPLACE;
915 case GL_INCR:
916 return STENCIL_INCR_CLAMP;
917 case GL_DECR:
918 return STENCIL_DECR_CLAMP;
919 case GL_INCR_WRAP_EXT:
920 return STENCIL_INCR_WRAP;
921 case GL_DECR_WRAP_EXT:
922 return STENCIL_DECR_WRAP;
923 case GL_INVERT:
924 return STENCIL_INVERT;
925 default:
926 WARN_ONCE("Do not know how to translate stencil op");
927 return STENCIL_KEEP;
928 }
929 return 0;
930 }
931
932 static void r700SetStencilState(GLcontext * ctx, GLboolean state)
933 {
934 context_t *context = R700_CONTEXT(ctx);
935 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
936 GLboolean hw_stencil = GL_FALSE;
937
938 //fixme
939 //r300CatchStencilFallback(ctx);
940
941 if (ctx->DrawBuffer) {
942 struct radeon_renderbuffer *rrbStencil
943 = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
944 hw_stencil = (rrbStencil && rrbStencil->bo);
945 }
946
947 if (hw_stencil) {
948 if (state)
949 SETbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
950 else
951 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
952 }
953 }
954
955 static void r700StencilFuncSeparate(GLcontext * ctx, GLenum face,
956 GLenum func, GLint ref, GLuint mask) //---------------------
957 {
958 context_t *context = R700_CONTEXT(ctx);
959 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
960 const unsigned back = ctx->Stencil._BackFace;
961
962 //fixme
963 //r300CatchStencilFallback(ctx);
964
965 //front
966 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.Ref[0],
967 STENCILREF_shift, STENCILREF_mask);
968 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.ValueMask[0],
969 STENCILMASK_shift, STENCILMASK_mask);
970
971 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[0]),
972 STENCILFUNC_shift, STENCILFUNC_mask);
973
974 //back
975 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.Ref[back],
976 STENCILREF_BF_shift, STENCILREF_BF_mask);
977 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.ValueMask[back],
978 STENCILMASK_BF_shift, STENCILMASK_BF_mask);
979
980 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[back]),
981 STENCILFUNC_BF_shift, STENCILFUNC_BF_mask);
982
983 }
984
985 static void r700StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) //--------------
986 {
987 context_t *context = R700_CONTEXT(ctx);
988 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
989 const unsigned back = ctx->Stencil._BackFace;
990
991 //fixme
992 //r300CatchStencilFallback(ctx);
993
994 // front
995 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.WriteMask[0],
996 STENCILWRITEMASK_shift, STENCILWRITEMASK_mask);
997
998 // back
999 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.WriteMask[back],
1000 STENCILWRITEMASK_BF_shift, STENCILWRITEMASK_BF_mask);
1001
1002 }
1003
1004 static void r700StencilOpSeparate(GLcontext * ctx, GLenum face,
1005 GLenum fail, GLenum zfail, GLenum zpass) //--------------------
1006 {
1007 context_t *context = R700_CONTEXT(ctx);
1008 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1009 const unsigned back = ctx->Stencil._BackFace;
1010
1011 //fixme
1012 //r300CatchStencilFallback(ctx);
1013
1014 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[0]),
1015 STENCILFAIL_shift, STENCILFAIL_mask);
1016 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[0]),
1017 STENCILZFAIL_shift, STENCILZFAIL_mask);
1018 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[0]),
1019 STENCILZPASS_shift, STENCILZPASS_mask);
1020
1021 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[back]),
1022 STENCILFAIL_BF_shift, STENCILFAIL_BF_mask);
1023 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[back]),
1024 STENCILZFAIL_BF_shift, STENCILZFAIL_BF_mask);
1025 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[back]),
1026 STENCILZPASS_BF_shift, STENCILZPASS_BF_mask);
1027 }
1028
1029 static void r700UpdateWindow(GLcontext * ctx, int id) //--------------------
1030 {
1031 context_t *context = R700_CONTEXT(ctx);
1032 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1033 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
1034 GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
1035 GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
1036 const GLfloat *v = ctx->Viewport._WindowMap.m;
1037 const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
1038 const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
1039 GLfloat y_scale, y_bias;
1040
1041 if (render_to_fbo) {
1042 y_scale = 1.0;
1043 y_bias = 0;
1044 } else {
1045 y_scale = -1.0;
1046 y_bias = yoffset;
1047 }
1048
1049 GLfloat sx = v[MAT_SX];
1050 GLfloat tx = v[MAT_TX] + xoffset;
1051 GLfloat sy = v[MAT_SY] * y_scale;
1052 GLfloat ty = (v[MAT_TY] * y_scale) + y_bias;
1053 GLfloat sz = v[MAT_SZ] * depthScale;
1054 GLfloat tz = v[MAT_TZ] * depthScale;
1055
1056 /* TODO : Need DMA flush as well. */
1057
1058 r700->viewport[id].PA_CL_VPORT_XSCALE.f32All = sx;
1059 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
1060
1061 r700->viewport[id].PA_CL_VPORT_YSCALE.f32All = sy;
1062 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
1063
1064 r700->viewport[id].PA_CL_VPORT_ZSCALE.f32All = sz;
1065 r700->viewport[id].PA_CL_VPORT_ZOFFSET.f32All = tz;
1066
1067 r700->viewport[id].enabled = GL_TRUE;
1068
1069 r700SetScissor(context);
1070 }
1071
1072
1073 static void r700Viewport(GLcontext * ctx,
1074 GLint x,
1075 GLint y,
1076 GLsizei width,
1077 GLsizei height) //--------------------
1078 {
1079 r700UpdateWindow(ctx, 0);
1080
1081 radeon_viewport(ctx, x, y, width, height);
1082 }
1083
1084 static void r700DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) //-------------
1085 {
1086 r700UpdateWindow(ctx, 0);
1087 }
1088
1089 static void r700LineWidth(GLcontext * ctx, GLfloat widthf) //---------------
1090 {
1091 context_t *context = R700_CONTEXT(ctx);
1092 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1093 uint32_t lineWidth = (uint32_t)((widthf * 0.5) * (1 << 4));
1094 if (lineWidth > 0xFFFF)
1095 lineWidth = 0xFFFF;
1096 SETfield(r700->PA_SU_LINE_CNTL.u32All,(uint16_t)lineWidth,
1097 PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
1098 }
1099
1100 static void r700LineStipple(GLcontext *ctx, GLint factor, GLushort pattern)
1101 {
1102 context_t *context = R700_CONTEXT(ctx);
1103 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1104
1105 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, pattern, LINE_PATTERN_shift, LINE_PATTERN_mask);
1106 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, (factor-1), REPEAT_COUNT_shift, REPEAT_COUNT_mask);
1107 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, 1, AUTO_RESET_CNTL_shift, AUTO_RESET_CNTL_mask);
1108 }
1109
1110 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state)
1111 {
1112 context_t *context = R700_CONTEXT(ctx);
1113 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1114
1115 if (state) {
1116 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1117 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1118 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1119 } else {
1120 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1121 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1122 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1123 }
1124 }
1125
1126 static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) //--------------
1127 {
1128 context_t *context = R700_CONTEXT(ctx);
1129 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1130 GLfloat constant = units;
1131
1132 switch (ctx->Visual.depthBits) {
1133 case 16:
1134 constant *= 4.0;
1135 break;
1136 case 24:
1137 constant *= 2.0;
1138 break;
1139 }
1140
1141 factor *= 12.0;
1142
1143 r700->PA_SU_POLY_OFFSET_FRONT_SCALE.f32All = factor;
1144 r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.f32All = constant;
1145 r700->PA_SU_POLY_OFFSET_BACK_SCALE.f32All = factor;
1146 r700->PA_SU_POLY_OFFSET_BACK_OFFSET.f32All = constant;
1147 }
1148
1149 static void r700UpdatePolygonMode(GLcontext * ctx)
1150 {
1151 context_t *context = R700_CONTEXT(ctx);
1152 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1153
1154 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DISABLE_POLY_MODE, POLY_MODE_shift, POLY_MODE_mask);
1155
1156 /* Only do something if a polygon mode is wanted, default is GL_FILL */
1157 if (ctx->Polygon.FrontMode != GL_FILL ||
1158 ctx->Polygon.BackMode != GL_FILL) {
1159 GLenum f, b;
1160
1161 /* Handle GL_CW (clock wise and GL_CCW (counter clock wise)
1162 * correctly by selecting the correct front and back face
1163 */
1164 if (ctx->Polygon.FrontFace == GL_CCW) {
1165 f = ctx->Polygon.FrontMode;
1166 b = ctx->Polygon.BackMode;
1167 } else {
1168 f = ctx->Polygon.BackMode;
1169 b = ctx->Polygon.FrontMode;
1170 }
1171
1172 /* Enable polygon mode */
1173 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DUAL_MODE, POLY_MODE_shift, POLY_MODE_mask);
1174
1175 switch (f) {
1176 case GL_LINE:
1177 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1178 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1179 break;
1180 case GL_POINT:
1181 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1182 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1183 break;
1184 case GL_FILL:
1185 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1186 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1187 break;
1188 }
1189
1190 switch (b) {
1191 case GL_LINE:
1192 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1193 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1194 break;
1195 case GL_POINT:
1196 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1197 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1198 break;
1199 case GL_FILL:
1200 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1201 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1202 break;
1203 }
1204 }
1205 }
1206
1207 static void r700PolygonMode(GLcontext * ctx, GLenum face, GLenum mode) //------------------
1208 {
1209 (void)face;
1210 (void)mode;
1211
1212 r700UpdatePolygonMode(ctx);
1213 }
1214
1215 static void r700RenderMode(GLcontext * ctx, GLenum mode) //---------------------
1216 {
1217 }
1218
1219 static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
1220 {
1221 context_t *context = R700_CONTEXT(ctx);
1222 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1223 GLint p;
1224 GLint *ip;
1225
1226 p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
1227 ip = (GLint *)ctx->Transform._ClipUserPlane[p];
1228
1229 r700->ucp[p].PA_CL_UCP_0_X.u32All = ip[0];
1230 r700->ucp[p].PA_CL_UCP_0_Y.u32All = ip[1];
1231 r700->ucp[p].PA_CL_UCP_0_Z.u32All = ip[2];
1232 r700->ucp[p].PA_CL_UCP_0_W.u32All = ip[3];
1233 }
1234
1235 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state)
1236 {
1237 context_t *context = R700_CONTEXT(ctx);
1238 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1239 GLuint p;
1240
1241 p = cap - GL_CLIP_PLANE0;
1242 if (state) {
1243 r700->PA_CL_CLIP_CNTL.u32All |= (UCP_ENA_0_bit << p);
1244 r700->ucp[p].enabled = GL_TRUE;
1245 r700ClipPlane(ctx, cap, NULL);
1246 } else {
1247 r700->PA_CL_CLIP_CNTL.u32All &= ~(UCP_ENA_0_bit << p);
1248 r700->ucp[p].enabled = GL_FALSE;
1249 }
1250 }
1251
1252 void r700SetScissor(context_t *context) //---------------
1253 {
1254 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1255 unsigned x1, y1, x2, y2;
1256 int id = 0;
1257 struct radeon_renderbuffer *rrb;
1258
1259 rrb = radeon_get_colorbuffer(&context->radeon);
1260 if (!rrb || !rrb->bo) {
1261 return;
1262 }
1263 if (context->radeon.state.scissor.enabled) {
1264 x1 = context->radeon.state.scissor.rect.x1;
1265 y1 = context->radeon.state.scissor.rect.y1;
1266 x2 = context->radeon.state.scissor.rect.x2 - 1;
1267 y2 = context->radeon.state.scissor.rect.y2 - 1;
1268 } else {
1269 x1 = rrb->dPriv->x;
1270 y1 = rrb->dPriv->y;
1271 x2 = rrb->dPriv->x + rrb->dPriv->w;
1272 y2 = rrb->dPriv->y + rrb->dPriv->h;
1273 }
1274
1275 /* window */
1276 SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1277 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, x1,
1278 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask);
1279 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, y1,
1280 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask);
1281
1282 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, x2,
1283 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask);
1284 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, y2,
1285 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask);
1286
1287
1288 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, x1,
1289 PA_SC_CLIPRECT_0_TL__TL_X_shift, PA_SC_CLIPRECT_0_TL__TL_X_mask);
1290 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, y1,
1291 PA_SC_CLIPRECT_0_TL__TL_Y_shift, PA_SC_CLIPRECT_0_TL__TL_Y_mask);
1292 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, x2,
1293 PA_SC_CLIPRECT_0_BR__BR_X_shift, PA_SC_CLIPRECT_0_BR__BR_X_mask);
1294 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, y2,
1295 PA_SC_CLIPRECT_0_BR__BR_Y_shift, PA_SC_CLIPRECT_0_BR__BR_Y_mask);
1296
1297 r700->PA_SC_CLIPRECT_1_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1298 r700->PA_SC_CLIPRECT_1_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1299 r700->PA_SC_CLIPRECT_2_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1300 r700->PA_SC_CLIPRECT_2_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1301 r700->PA_SC_CLIPRECT_3_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1302 r700->PA_SC_CLIPRECT_3_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1303
1304 /* more....2d clip */
1305 SETbit(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1306 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, x1,
1307 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask);
1308 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, y1,
1309 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask);
1310 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, x2,
1311 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask);
1312 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, y2,
1313 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask);
1314
1315 SETbit(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1316 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, x1,
1317 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask);
1318 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, y1,
1319 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask);
1320 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, x2,
1321 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask);
1322 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, y2,
1323 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask);
1324
1325 r700->viewport[id].PA_SC_VPORT_ZMIN_0.u32All = 0;
1326 r700->viewport[id].PA_SC_VPORT_ZMAX_0.u32All = 0x3F800000;
1327 r700->viewport[id].enabled = GL_TRUE;
1328 }
1329
1330 void r700SetRenderTarget(context_t *context, int id)
1331 {
1332 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1333
1334 struct radeon_renderbuffer *rrb;
1335 unsigned int nPitchInPixel;
1336
1337 /* screen/window/view */
1338 SETfield(r700->CB_TARGET_MASK.u32All, 0xF, (4 * id), TARGET0_ENABLE_mask);
1339
1340 rrb = radeon_get_colorbuffer(&context->radeon);
1341 if (!rrb || !rrb->bo) {
1342 fprintf(stderr, "no rrb\n");
1343 return;
1344 }
1345
1346 /* color buffer */
1347 r700->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset;
1348
1349 nPitchInPixel = rrb->pitch/rrb->cpp;
1350 SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1,
1351 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
1352 SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
1353 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
1354 r700->render_target[id].CB_COLOR0_BASE.u32All = 0;
1355 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
1356 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL,
1357 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
1358 if(4 == rrb->cpp)
1359 {
1360 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_8_8_8_8,
1361 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
1362 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT, COMP_SWAP_shift, COMP_SWAP_mask);
1363 }
1364 else
1365 {
1366 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_5_6_5,
1367 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
1368 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT_REV,
1369 COMP_SWAP_shift, COMP_SWAP_mask);
1370 }
1371 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
1372 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit);
1373 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
1374
1375 r700->render_target[id].enabled = GL_TRUE;
1376 }
1377
1378 void r700SetDepthTarget(context_t *context)
1379 {
1380 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1381
1382 struct radeon_renderbuffer *rrb;
1383 unsigned int nPitchInPixel;
1384
1385 /* depth buf */
1386 r700->DB_DEPTH_SIZE.u32All = 0;
1387 r700->DB_DEPTH_BASE.u32All = 0;
1388 r700->DB_DEPTH_INFO.u32All = 0;
1389
1390 r700->DB_DEPTH_CLEAR.u32All = 0x3F800000;
1391 r700->DB_DEPTH_VIEW.u32All = 0;
1392 r700->DB_RENDER_CONTROL.u32All = 0;
1393 SETbit(r700->DB_RENDER_CONTROL.u32All, STENCIL_COMPRESS_DISABLE_bit);
1394 SETbit(r700->DB_RENDER_CONTROL.u32All, DEPTH_COMPRESS_DISABLE_bit);
1395 r700->DB_RENDER_OVERRIDE.u32All = 0;
1396 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1397 SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit);
1398 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
1399 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
1400 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
1401
1402 r700->DB_ALPHA_TO_MASK.u32All = 0;
1403 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask);
1404 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET1_shift, ALPHA_TO_MASK_OFFSET1_mask);
1405 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET2_shift, ALPHA_TO_MASK_OFFSET2_mask);
1406 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET3_shift, ALPHA_TO_MASK_OFFSET3_mask);
1407
1408 rrb = radeon_get_depthbuffer(&context->radeon);
1409 if (!rrb)
1410 return;
1411
1412 nPitchInPixel = rrb->pitch/rrb->cpp;
1413
1414 SETfield(r700->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1,
1415 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
1416 SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
1417 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */
1418
1419 if(4 == rrb->cpp)
1420 {
1421 switch (GL_CONTEXT(context)->Visual.depthBits)
1422 {
1423 case 16:
1424 case 24:
1425 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_8_24,
1426 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
1427 break;
1428 default:
1429 fprintf(stderr, "Error: Unsupported depth %d... exiting\n",
1430 GL_CONTEXT(context)->Visual.depthBits);
1431 _mesa_exit(-1);
1432 }
1433 }
1434 else
1435 {
1436 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16,
1437 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
1438 }
1439 SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_2D_TILED_THIN1,
1440 DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask);
1441 /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */
1442 }
1443
1444 static void r700InitSQConfig(GLcontext * ctx)
1445 {
1446 context_t *context = R700_CONTEXT(ctx);
1447 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1448 int ps_prio;
1449 int vs_prio;
1450 int gs_prio;
1451 int es_prio;
1452 int num_ps_gprs;
1453 int num_vs_gprs;
1454 int num_gs_gprs;
1455 int num_es_gprs;
1456 int num_temp_gprs;
1457 int num_ps_threads;
1458 int num_vs_threads;
1459 int num_gs_threads;
1460 int num_es_threads;
1461 int num_ps_stack_entries;
1462 int num_vs_stack_entries;
1463 int num_gs_stack_entries;
1464 int num_es_stack_entries;
1465
1466 // SQ
1467 ps_prio = 0;
1468 vs_prio = 1;
1469 gs_prio = 2;
1470 es_prio = 3;
1471 switch (context->radeon.radeonScreen->chip_family) {
1472 case CHIP_FAMILY_R600:
1473 num_ps_gprs = 192;
1474 num_vs_gprs = 56;
1475 num_temp_gprs = 4;
1476 num_gs_gprs = 0;
1477 num_es_gprs = 0;
1478 num_ps_threads = 136;
1479 num_vs_threads = 48;
1480 num_gs_threads = 4;
1481 num_es_threads = 4;
1482 num_ps_stack_entries = 128;
1483 num_vs_stack_entries = 128;
1484 num_gs_stack_entries = 0;
1485 num_es_stack_entries = 0;
1486 break;
1487 case CHIP_FAMILY_RV630:
1488 case CHIP_FAMILY_RV635:
1489 num_ps_gprs = 84;
1490 num_vs_gprs = 36;
1491 num_temp_gprs = 4;
1492 num_gs_gprs = 0;
1493 num_es_gprs = 0;
1494 num_ps_threads = 144;
1495 num_vs_threads = 40;
1496 num_gs_threads = 4;
1497 num_es_threads = 4;
1498 num_ps_stack_entries = 40;
1499 num_vs_stack_entries = 40;
1500 num_gs_stack_entries = 32;
1501 num_es_stack_entries = 16;
1502 break;
1503 case CHIP_FAMILY_RV610:
1504 case CHIP_FAMILY_RV620:
1505 case CHIP_FAMILY_RS780:
1506 default:
1507 num_ps_gprs = 84;
1508 num_vs_gprs = 36;
1509 num_temp_gprs = 4;
1510 num_gs_gprs = 0;
1511 num_es_gprs = 0;
1512 num_ps_threads = 136;
1513 num_vs_threads = 48;
1514 num_gs_threads = 4;
1515 num_es_threads = 4;
1516 num_ps_stack_entries = 40;
1517 num_vs_stack_entries = 40;
1518 num_gs_stack_entries = 32;
1519 num_es_stack_entries = 16;
1520 break;
1521 case CHIP_FAMILY_RV670:
1522 num_ps_gprs = 144;
1523 num_vs_gprs = 40;
1524 num_temp_gprs = 4;
1525 num_gs_gprs = 0;
1526 num_es_gprs = 0;
1527 num_ps_threads = 136;
1528 num_vs_threads = 48;
1529 num_gs_threads = 4;
1530 num_es_threads = 4;
1531 num_ps_stack_entries = 40;
1532 num_vs_stack_entries = 40;
1533 num_gs_stack_entries = 32;
1534 num_es_stack_entries = 16;
1535 break;
1536 case CHIP_FAMILY_RV770:
1537 num_ps_gprs = 192;
1538 num_vs_gprs = 56;
1539 num_temp_gprs = 4;
1540 num_gs_gprs = 0;
1541 num_es_gprs = 0;
1542 num_ps_threads = 188;
1543 num_vs_threads = 60;
1544 num_gs_threads = 0;
1545 num_es_threads = 0;
1546 num_ps_stack_entries = 256;
1547 num_vs_stack_entries = 256;
1548 num_gs_stack_entries = 0;
1549 num_es_stack_entries = 0;
1550 break;
1551 case CHIP_FAMILY_RV730:
1552 case CHIP_FAMILY_RV740:
1553 num_ps_gprs = 84;
1554 num_vs_gprs = 36;
1555 num_temp_gprs = 4;
1556 num_gs_gprs = 0;
1557 num_es_gprs = 0;
1558 num_ps_threads = 188;
1559 num_vs_threads = 60;
1560 num_gs_threads = 0;
1561 num_es_threads = 0;
1562 num_ps_stack_entries = 128;
1563 num_vs_stack_entries = 128;
1564 num_gs_stack_entries = 0;
1565 num_es_stack_entries = 0;
1566 break;
1567 case CHIP_FAMILY_RV710:
1568 num_ps_gprs = 192;
1569 num_vs_gprs = 56;
1570 num_temp_gprs = 4;
1571 num_gs_gprs = 0;
1572 num_es_gprs = 0;
1573 num_ps_threads = 144;
1574 num_vs_threads = 48;
1575 num_gs_threads = 0;
1576 num_es_threads = 0;
1577 num_ps_stack_entries = 128;
1578 num_vs_stack_entries = 128;
1579 num_gs_stack_entries = 0;
1580 num_es_stack_entries = 0;
1581 break;
1582 }
1583
1584 r700->sq_config.SQ_CONFIG.u32All = 0;
1585 if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
1586 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
1587 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
1588 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
1589 CLEARbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1590 else
1591 SETbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1592 SETbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit);
1593 SETbit(r700->sq_config.SQ_CONFIG.u32All, ALU_INST_PREFER_VECTOR_bit);
1594 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, PS_PRIO_shift, PS_PRIO_mask);
1595 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, VS_PRIO_shift, VS_PRIO_mask);
1596 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, GS_PRIO_shift, GS_PRIO_mask);
1597 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, ES_PRIO_shift, ES_PRIO_mask);
1598
1599 r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All = 0;
1600 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_ps_gprs, NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
1601 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_vs_gprs, NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
1602 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_temp_gprs,
1603 NUM_CLAUSE_TEMP_GPRS_shift, NUM_CLAUSE_TEMP_GPRS_mask);
1604
1605 r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All = 0;
1606 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_gs_gprs, NUM_GS_GPRS_shift, NUM_GS_GPRS_mask);
1607 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_es_gprs, NUM_ES_GPRS_shift, NUM_ES_GPRS_mask);
1608
1609 r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All = 0;
1610 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_ps_threads,
1611 NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
1612 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_vs_threads,
1613 NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
1614 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_gs_threads,
1615 NUM_GS_THREADS_shift, NUM_GS_THREADS_mask);
1616 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_es_threads,
1617 NUM_ES_THREADS_shift, NUM_ES_THREADS_mask);
1618
1619 r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All = 0;
1620 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_ps_stack_entries,
1621 NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
1622 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_vs_stack_entries,
1623 NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
1624
1625 r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All = 0;
1626 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_gs_stack_entries,
1627 NUM_GS_STACK_ENTRIES_shift, NUM_GS_STACK_ENTRIES_mask);
1628 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_es_stack_entries,
1629 NUM_ES_STACK_ENTRIES_shift, NUM_ES_STACK_ENTRIES_mask);
1630
1631 }
1632
1633 /**
1634 * Calculate initial hardware state and register state functions.
1635 * Assumes that the command buffer and state atoms have been
1636 * initialized already.
1637 */
1638 void r700InitState(GLcontext * ctx) //-------------------
1639 {
1640 context_t *context = R700_CONTEXT(ctx);
1641
1642 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1643
1644 r700->TA_CNTL_AUX.u32All = 0;
1645 SETfield(r700->TA_CNTL_AUX.u32All, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask);
1646 r700->VC_ENHANCE.u32All = 0;
1647 r700->DB_WATERMARKS.u32All = 0;
1648 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_FREE_shift, DEPTH_FREE_mask);
1649 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_FLUSH_shift, DEPTH_FLUSH_mask);
1650 SETfield(r700->DB_WATERMARKS.u32All, 0, FORCE_SUMMARIZE_shift, FORCE_SUMMARIZE_mask);
1651 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_PENDING_FREE_shift, DEPTH_PENDING_FREE_mask);
1652 r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All = 0;
1653 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1654 SETfield(r700->TA_CNTL_AUX.u32All, 3, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1655 r700->DB_DEBUG.u32All = 0x82000000;
1656 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1657 } else {
1658 SETfield(r700->TA_CNTL_AUX.u32All, 2, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1659 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1660 SETbit(r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All, VS_PC_LIMIT_ENABLE_bit);
1661 }
1662
1663 /* Turn off vgt reuse */
1664 r700->VGT_REUSE_OFF.u32All = 0;
1665 SETbit(r700->VGT_REUSE_OFF.u32All, REUSE_OFF_bit);
1666
1667 /* Specify offsetting and clamp values for vertices */
1668 r700->VGT_MAX_VTX_INDX.u32All = 0xFFFFFF;
1669 r700->VGT_MIN_VTX_INDX.u32All = 0;
1670 r700->VGT_INDX_OFFSET.u32All = 0;
1671
1672 /* default shader connections. */
1673 r700->SPI_VS_OUT_ID_0.u32All = 0x03020100;
1674 r700->SPI_VS_OUT_ID_1.u32All = 0x07060504;
1675
1676 r700->SPI_THREAD_GROUPING.u32All = 0;
1677 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
1678 SETfield(r700->SPI_THREAD_GROUPING.u32All, 1, PS_GROUPING_shift, PS_GROUPING_mask);
1679
1680 /* screen */
1681 r700->PA_SC_SCREEN_SCISSOR_TL.u32All = 0x0;
1682
1683 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All,
1684 ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->width,
1685 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask);
1686 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All,
1687 ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->height,
1688 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask);
1689
1690 /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
1691 r700->PA_SC_CLIPRECT_RULE.u32All = 0;
1692 SETfield(r700->PA_SC_CLIPRECT_RULE.u32All, CLIP_RULE_mask, CLIP_RULE_shift, CLIP_RULE_mask);
1693
1694 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1695 r700->PA_SC_EDGERULE.u32All = 0;
1696 else
1697 r700->PA_SC_EDGERULE.u32All = 0xAAAAAAAA;
1698
1699 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1700 r700->PA_SC_MODE_CNTL.u32All = 0;
1701 SETbit(r700->PA_SC_MODE_CNTL.u32All, WALK_ORDER_ENABLE_bit);
1702 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1703 } else {
1704 r700->PA_SC_MODE_CNTL.u32All = 0x00500000;
1705 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_REZ_ENABLE_bit);
1706 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1707 }
1708
1709 /* Do scale XY and Z by 1/W0. */
1710 r700->bEnablePerspective = GL_TRUE;
1711 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
1712 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
1713 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
1714
1715 /* Enable viewport scaling for all three axis */
1716 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_SCALE_ENA_bit);
1717 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_OFFSET_ENA_bit);
1718 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_SCALE_ENA_bit);
1719 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_OFFSET_ENA_bit);
1720 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_SCALE_ENA_bit);
1721 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_OFFSET_ENA_bit);
1722
1723 /* GL uses last vtx for flat shading components */
1724 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
1725
1726 /* Set up vertex control */
1727 r700->PA_SU_VTX_CNTL.u32All = 0;
1728 CLEARfield(r700->PA_SU_VTX_CNTL.u32All, QUANT_MODE_mask);
1729 SETbit(r700->PA_SU_VTX_CNTL.u32All, PIX_CENTER_bit);
1730 SETfield(r700->PA_SU_VTX_CNTL.u32All, X_ROUND_TO_EVEN,
1731 PA_SU_VTX_CNTL__ROUND_MODE_shift, PA_SU_VTX_CNTL__ROUND_MODE_mask);
1732
1733 /* to 1.0 = no guard band */
1734 r700->PA_CL_GB_VERT_CLIP_ADJ.u32All = 0x3F800000; /* 1.0 */
1735 r700->PA_CL_GB_VERT_DISC_ADJ.u32All = 0x3F800000;
1736 r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All = 0x3F800000;
1737 r700->PA_CL_GB_HORZ_DISC_ADJ.u32All = 0x3F800000;
1738
1739 /* Enable all samples for multi-sample anti-aliasing */
1740 r700->PA_SC_AA_MASK.u32All = 0xFFFFFFFF;
1741 /* Turn off AA */
1742 r700->PA_SC_AA_CONFIG.u32All = 0;
1743
1744 r700->SX_MISC.u32All = 0;
1745
1746 r700InitSQConfig(ctx);
1747
1748 r700ColorMask(ctx,
1749 ctx->Color.ColorMask[RCOMP],
1750 ctx->Color.ColorMask[GCOMP],
1751 ctx->Color.ColorMask[BCOMP],
1752 ctx->Color.ColorMask[ACOMP]);
1753
1754 r700Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test);
1755 r700DepthMask(ctx, ctx->Depth.Mask);
1756 r700DepthFunc(ctx, ctx->Depth.Func);
1757 SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
1758
1759 /* stencil */
1760 r700Enable(ctx, GL_STENCIL_TEST, ctx->Stencil._Enabled);
1761 r700StencilMaskSeparate(ctx, 0, ctx->Stencil.WriteMask[0]);
1762 r700StencilFuncSeparate(ctx, 0, ctx->Stencil.Function[0],
1763 ctx->Stencil.Ref[0], ctx->Stencil.ValueMask[0]);
1764 r700StencilOpSeparate(ctx, 0, ctx->Stencil.FailFunc[0],
1765 ctx->Stencil.ZFailFunc[0],
1766 ctx->Stencil.ZPassFunc[0]);
1767
1768 r700UpdateCulling(ctx);
1769
1770 r700SetBlendState(ctx);
1771 r700SetLogicOpState(ctx);
1772
1773 r700AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef);
1774 r700Enable(ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled);
1775
1776 r700PointSize(ctx, 1.0);
1777
1778 CLEARfield(r700->PA_SU_POINT_MINMAX.u32All, MIN_SIZE_mask);
1779 SETfield(r700->PA_SU_POINT_MINMAX.u32All, 0x8000, MAX_SIZE_shift, MAX_SIZE_mask);
1780
1781 r700LineWidth(ctx, 1.0);
1782
1783 r700->PA_SC_LINE_CNTL.u32All = 0;
1784 CLEARbit(r700->PA_SC_LINE_CNTL.u32All, EXPAND_LINE_WIDTH_bit);
1785 SETbit(r700->PA_SC_LINE_CNTL.u32All, LAST_PIXEL_bit);
1786
1787 r700ShadeModel(ctx, ctx->Light.ShadeModel);
1788 r700PolygonMode(ctx, GL_FRONT, ctx->Polygon.FrontMode);
1789 r700PolygonMode(ctx, GL_BACK, ctx->Polygon.BackMode);
1790 r700PolygonOffset(ctx, ctx->Polygon.OffsetFactor,
1791 ctx->Polygon.OffsetUnits);
1792 r700Enable(ctx, GL_POLYGON_OFFSET_POINT, ctx->Polygon.OffsetPoint);
1793 r700Enable(ctx, GL_POLYGON_OFFSET_LINE, ctx->Polygon.OffsetLine);
1794 r700Enable(ctx, GL_POLYGON_OFFSET_FILL, ctx->Polygon.OffsetFill);
1795
1796 /* CB */
1797 r700BlendColor(ctx, ctx->Color.BlendColor);
1798
1799 r700->CB_CLEAR_RED_R6XX.f32All = 1.0; //r6xx only
1800 r700->CB_CLEAR_GREEN_R6XX.f32All = 0.0; //r6xx only
1801 r700->CB_CLEAR_BLUE_R6XX.f32All = 1.0; //r6xx only
1802 r700->CB_CLEAR_ALPHA_R6XX.f32All = 1.0; //r6xx only
1803 r700->CB_FOG_RED_R6XX.u32All = 0; //r6xx only
1804 r700->CB_FOG_GREEN_R6XX.u32All = 0; //r6xx only
1805 r700->CB_FOG_BLUE_R6XX.u32All = 0; //r6xx only
1806
1807 /* Disable color compares */
1808 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1809 CLRCMP_FCN_SRC_shift, CLRCMP_FCN_SRC_mask);
1810 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1811 CLRCMP_FCN_DST_shift, CLRCMP_FCN_DST_mask);
1812 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_SEL_SRC,
1813 CLRCMP_FCN_SEL_shift, CLRCMP_FCN_SEL_mask);
1814
1815 /* Zero out source */
1816 r700->CB_CLRCMP_SRC.u32All = 0x00000000;
1817
1818 /* Put a compare color in for error checking */
1819 r700->CB_CLRCMP_DST.u32All = 0x000000FF;
1820
1821 /* Set up color compare mask */
1822 r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF;
1823
1824 }
1825
1826 void r700InitStateFuncs(struct dd_function_table *functions) //-----------------
1827 {
1828 functions->UpdateState = r700InvalidateState;
1829 functions->AlphaFunc = r700AlphaFunc;
1830 functions->BlendColor = r700BlendColor;
1831 functions->BlendEquationSeparate = r700BlendEquationSeparate;
1832 functions->BlendFuncSeparate = r700BlendFuncSeparate;
1833 functions->Enable = r700Enable;
1834 functions->ColorMask = r700ColorMask;
1835 functions->DepthFunc = r700DepthFunc;
1836 functions->DepthMask = r700DepthMask;
1837 functions->CullFace = r700CullFace;
1838 functions->Fogfv = r700Fogfv;
1839 functions->FrontFace = r700FrontFace;
1840 functions->ShadeModel = r700ShadeModel;
1841 functions->LogicOpcode = r700LogicOpcode;
1842
1843 /* ARB_point_parameters */
1844 functions->PointParameterfv = r700PointParameter;
1845
1846 /* Stencil related */
1847 functions->StencilFuncSeparate = r700StencilFuncSeparate;
1848 functions->StencilMaskSeparate = r700StencilMaskSeparate;
1849 functions->StencilOpSeparate = r700StencilOpSeparate;
1850
1851 /* Viewport related */
1852 functions->Viewport = r700Viewport;
1853 functions->DepthRange = r700DepthRange;
1854 functions->PointSize = r700PointSize;
1855 functions->LineWidth = r700LineWidth;
1856 functions->LineStipple = r700LineStipple;
1857
1858 functions->PolygonOffset = r700PolygonOffset;
1859 functions->PolygonMode = r700PolygonMode;
1860
1861 functions->RenderMode = r700RenderMode;
1862
1863 functions->ClipPlane = r700ClipPlane;
1864
1865 functions->Scissor = radeonScissor;
1866
1867 functions->DrawBuffer = radeonDrawBuffer;
1868 functions->ReadBuffer = radeonReadBuffer;
1869
1870 }
1871