2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/context.h"
35 #include "main/simple_list.h"
38 #include "tnl/t_pipeline.h"
39 #include "tnl/t_vp_build.h"
40 #include "swrast/swrast.h"
41 #include "swrast_setup/swrast_setup.h"
42 #include "main/api_arrayelt.h"
43 #include "main/state.h"
44 #include "main/framebuffer.h"
46 #include "shader/prog_parameter.h"
47 #include "shader/prog_statevars.h"
49 #include "main/texformat.h"
51 #include "r600_context.h"
53 #include "r700_state.h"
55 #include "r700_fragprog.h"
56 #include "r700_vertprog.h"
59 static void r700SetClipPlaneState(GLcontext
* ctx
, GLenum cap
, GLboolean state
);
60 static void r700UpdatePolygonMode(GLcontext
* ctx
);
61 static void r700SetPolygonOffsetState(GLcontext
* ctx
, GLboolean state
);
62 static void r700SetStencilState(GLcontext
* ctx
, GLboolean state
);
63 static void r700SetRenderTarget(context_t
*context
, int id
);
64 static void r700SetDepthTarget(context_t
*context
);
66 void r700SetDefaultStates(context_t
*context
) //--------------------
71 void r700UpdateShaders (GLcontext
* ctx
) //----------------------------------
73 context_t
*context
= R700_CONTEXT(ctx
);
75 GLvector4f dummy_attrib
[_TNL_ATTRIB_MAX
];
76 GLvector4f
*temp_attrib
[_TNL_ATTRIB_MAX
];
79 if (ctx
->FragmentProgram
._Current
) {
80 struct r700_fragment_program
*fp
= (struct r700_fragment_program
*)
81 (ctx
->FragmentProgram
._Current
);
82 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
)
84 fp
->r700AsmCode
.bR6xx
= 1;
87 if(GL_FALSE
== fp
->translated
)
89 if( GL_FALSE
== r700TranslateFragmentShader(fp
, &(fp
->mesa_program
)) )
96 if (context
->radeon
.NewGLState
)
98 struct r700_vertex_program
*vp
;
99 context
->radeon
.NewGLState
= 0;
101 for (i
= _TNL_FIRST_MAT
; i
<= _TNL_LAST_MAT
; i
++)
103 /* mat states from state var not array for sw */
104 dummy_attrib
[i
].stride
= 0;
106 temp_attrib
[i
] = TNL_CONTEXT(ctx
)->vb
.AttribPtr
[i
];
107 TNL_CONTEXT(ctx
)->vb
.AttribPtr
[i
] = &(dummy_attrib
[i
]);
110 _tnl_UpdateFixedFunctionProgram(ctx
);
112 for (i
= _TNL_FIRST_MAT
; i
<= _TNL_LAST_MAT
; i
++)
114 TNL_CONTEXT(ctx
)->vb
.AttribPtr
[i
] = temp_attrib
[i
];
117 r700SelectVertexShader(ctx
);
118 vp
= (struct r700_vertex_program
*)ctx
->VertexProgram
._Current
;
120 if (vp
->translated
== GL_FALSE
)
123 //fprintf(stderr, "Failing back to sw-tcl\n");
124 //hw_tcl_on = future_hw_tcl_on = 0;
125 //r300ResetHwState(rmesa);
127 r700UpdateStateParameters(ctx
, _NEW_PROGRAM
);
132 r700UpdateStateParameters(ctx
, _NEW_PROGRAM
);
136 * To correctly position primitives:
138 void r700UpdateViewportOffset(GLcontext
* ctx
) //------------------
140 context_t
*context
= R700_CONTEXT(ctx
);
141 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
142 __DRIdrawablePrivate
*dPriv
= radeon_get_drawable(&context
->radeon
);
143 GLfloat xoffset
= (GLfloat
) dPriv
->x
;
144 GLfloat yoffset
= (GLfloat
) dPriv
->y
+ dPriv
->h
;
145 const GLfloat
*v
= ctx
->Viewport
._WindowMap
.m
;
148 GLfloat tx
= v
[MAT_TX
] + xoffset
;
149 GLfloat ty
= (-v
[MAT_TY
]) + yoffset
;
151 if (r700
->viewport
[id
].PA_CL_VPORT_XOFFSET
.f32All
!= tx
||
152 r700
->viewport
[id
].PA_CL_VPORT_YOFFSET
.f32All
!= ty
) {
153 /* Note: this should also modify whatever data the context reset
156 R600_STATECHANGE(context
, vpt
);
157 r700
->viewport
[id
].PA_CL_VPORT_XOFFSET
.f32All
= tx
;
158 r700
->viewport
[id
].PA_CL_VPORT_YOFFSET
.f32All
= ty
;
161 radeonUpdateScissor(ctx
);
165 * Tell the card where to render (offset, pitch).
166 * Effected by glDrawBuffer, etc
168 void r700UpdateDrawBuffer(GLcontext
* ctx
) /* TODO */ //---------------------
170 context_t
*context
= R700_CONTEXT(ctx
);
172 R600_STATECHANGE(context
, cb_target
);
173 R600_STATECHANGE(context
, db_target
);
175 r700SetRenderTarget(context
, 0);
176 r700SetDepthTarget(context
);
179 static void r700FetchStateParameter(GLcontext
* ctx
,
180 const gl_state_index state
[STATE_LENGTH
],
186 void r700UpdateStateParameters(GLcontext
* ctx
, GLuint new_state
) //--------------------
188 struct r700_fragment_program
*fp
;
189 struct gl_program_parameter_list
*paramList
;
192 if (!(new_state
& (_NEW_BUFFERS
| _NEW_PROGRAM
)))
195 fp
= (struct r700_fragment_program
*)ctx
->FragmentProgram
._Current
;
201 paramList
= fp
->mesa_program
.Base
.Parameters
;
208 for (i
= 0; i
< paramList
->NumParameters
; i
++)
210 if (paramList
->Parameters
[i
].Type
== PROGRAM_STATE_VAR
)
212 r700FetchStateParameter(ctx
,
213 paramList
->Parameters
[i
].
215 paramList
->ParameterValues
[i
]);
221 * Called by Mesa after an internal state update.
223 static void r700InvalidateState(GLcontext
* ctx
, GLuint new_state
) //-------------------
225 context_t
*context
= R700_CONTEXT(ctx
);
227 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
229 _swrast_InvalidateState(ctx
, new_state
);
230 _swsetup_InvalidateState(ctx
, new_state
);
231 _vbo_InvalidateState(ctx
, new_state
);
232 _tnl_InvalidateState(ctx
, new_state
);
233 _ae_invalidate_state(ctx
, new_state
);
235 if (new_state
& (_NEW_BUFFERS
| _NEW_COLOR
| _NEW_PIXEL
))
237 _mesa_update_framebuffer(ctx
);
238 /* this updates the DrawBuffer's Width/Height if it's a FBO */
239 _mesa_update_draw_buffer_bounds(ctx
);
241 r700UpdateDrawBuffer(ctx
);
244 r700UpdateStateParameters(ctx
, new_state
);
246 R600_STATECHANGE(context
, cl
);
247 R600_STATECHANGE(context
, spi
);
249 if(GL_TRUE
== r700
->bEnablePerspective
)
251 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
252 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_XY_FMT_bit
);
253 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_Z_FMT_bit
);
255 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_W0_FMT_bit
);
257 SETbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, PERSP_GRADIENT_ENA_bit
);
258 CLEARbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, LINEAR_GRADIENT_ENA_bit
);
262 /* For orthogonal case. */
263 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_XY_FMT_bit
);
264 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_Z_FMT_bit
);
266 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_W0_FMT_bit
);
268 CLEARbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, PERSP_GRADIENT_ENA_bit
);
269 SETbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, LINEAR_GRADIENT_ENA_bit
);
272 context
->radeon
.NewGLState
|= new_state
;
275 static void r700SetDepthState(GLcontext
* ctx
)
277 context_t
*context
= R700_CONTEXT(ctx
);
278 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
280 R600_STATECHANGE(context
, db
);
284 SETbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_ENABLE_bit
);
287 SETbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_WRITE_ENABLE_bit
);
291 CLEARbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_WRITE_ENABLE_bit
);
294 switch (ctx
->Depth
.Func
)
297 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_NEVER
,
298 ZFUNC_shift
, ZFUNC_mask
);
301 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_LESS
,
302 ZFUNC_shift
, ZFUNC_mask
);
305 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_EQUAL
,
306 ZFUNC_shift
, ZFUNC_mask
);
309 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_LEQUAL
,
310 ZFUNC_shift
, ZFUNC_mask
);
313 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_GREATER
,
314 ZFUNC_shift
, ZFUNC_mask
);
317 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_NOTEQUAL
,
318 ZFUNC_shift
, ZFUNC_mask
);
321 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_GEQUAL
,
322 ZFUNC_shift
, ZFUNC_mask
);
325 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_ALWAYS
,
326 ZFUNC_shift
, ZFUNC_mask
);
329 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_ALWAYS
,
330 ZFUNC_shift
, ZFUNC_mask
);
336 CLEARbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_ENABLE_bit
);
337 CLEARbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_WRITE_ENABLE_bit
);
341 static void r700SetAlphaState(GLcontext
* ctx
)
343 context_t
*context
= R700_CONTEXT(ctx
);
344 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
345 uint32_t alpha_func
= REF_ALWAYS
;
346 GLboolean really_enabled
= ctx
->Color
.AlphaEnabled
;
348 R600_STATECHANGE(context
, sx
);
350 switch (ctx
->Color
.AlphaFunc
) {
352 alpha_func
= REF_NEVER
;
355 alpha_func
= REF_LESS
;
358 alpha_func
= REF_EQUAL
;
361 alpha_func
= REF_LEQUAL
;
364 alpha_func
= REF_GREATER
;
367 alpha_func
= REF_NOTEQUAL
;
370 alpha_func
= REF_GEQUAL
;
373 /*alpha_func = REF_ALWAYS; */
374 really_enabled
= GL_FALSE
;
378 if (really_enabled
) {
379 SETfield(r700
->SX_ALPHA_TEST_CONTROL
.u32All
, alpha_func
,
380 ALPHA_FUNC_shift
, ALPHA_FUNC_mask
);
381 SETbit(r700
->SX_ALPHA_TEST_CONTROL
.u32All
, ALPHA_TEST_ENABLE_bit
);
382 r700
->SX_ALPHA_REF
.f32All
= ctx
->Color
.AlphaRef
;
384 CLEARbit(r700
->SX_ALPHA_TEST_CONTROL
.u32All
, ALPHA_TEST_ENABLE_bit
);
389 static void r700AlphaFunc(GLcontext
* ctx
, GLenum func
, GLfloat ref
) //---------------
393 r700SetAlphaState(ctx
);
397 static void r700BlendColor(GLcontext
* ctx
, const GLfloat cf
[4]) //----------------
399 context_t
*context
= R700_CONTEXT(ctx
);
400 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
402 R600_STATECHANGE(context
, blnd_clr
);
404 r700
->CB_BLEND_RED
.f32All
= cf
[0];
405 r700
->CB_BLEND_GREEN
.f32All
= cf
[1];
406 r700
->CB_BLEND_BLUE
.f32All
= cf
[2];
407 r700
->CB_BLEND_ALPHA
.f32All
= cf
[3];
410 static int blend_factor(GLenum factor
, GLboolean is_src
)
420 return BLEND_DST_COLOR
;
422 case GL_ONE_MINUS_DST_COLOR
:
423 return BLEND_ONE_MINUS_DST_COLOR
;
426 return BLEND_SRC_COLOR
;
428 case GL_ONE_MINUS_SRC_COLOR
:
429 return BLEND_ONE_MINUS_SRC_COLOR
;
432 return BLEND_SRC_ALPHA
;
434 case GL_ONE_MINUS_SRC_ALPHA
:
435 return BLEND_ONE_MINUS_SRC_ALPHA
;
438 return BLEND_DST_ALPHA
;
440 case GL_ONE_MINUS_DST_ALPHA
:
441 return BLEND_ONE_MINUS_DST_ALPHA
;
443 case GL_SRC_ALPHA_SATURATE
:
444 return (is_src
) ? BLEND_SRC_ALPHA_SATURATE
: BLEND_ZERO
;
446 case GL_CONSTANT_COLOR
:
447 return BLEND_CONSTANT_COLOR
;
449 case GL_ONE_MINUS_CONSTANT_COLOR
:
450 return BLEND_ONE_MINUS_CONSTANT_COLOR
;
452 case GL_CONSTANT_ALPHA
:
453 return BLEND_CONSTANT_ALPHA
;
455 case GL_ONE_MINUS_CONSTANT_ALPHA
:
456 return BLEND_ONE_MINUS_CONSTANT_ALPHA
;
459 fprintf(stderr
, "unknown blend factor %x\n", factor
);
460 return (is_src
) ? BLEND_ONE
: BLEND_ZERO
;
465 static void r700SetBlendState(GLcontext
* ctx
)
467 context_t
*context
= R700_CONTEXT(ctx
);
468 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
470 uint32_t blend_reg
= 0, eqn
, eqnA
;
472 R600_STATECHANGE(context
, blnd
);
474 if (RGBA_LOGICOP_ENABLED(ctx
) || !ctx
->Color
.BlendEnabled
) {
476 BLEND_ONE
, COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
478 BLEND_ZERO
, COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
480 COMB_DST_PLUS_SRC
, COLOR_COMB_FCN_shift
, COLOR_COMB_FCN_mask
);
482 BLEND_ONE
, ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
484 BLEND_ZERO
, ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
486 COMB_DST_PLUS_SRC
, ALPHA_COMB_FCN_shift
, ALPHA_COMB_FCN_mask
);
487 if (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_R600
)
488 r700
->CB_BLEND_CONTROL
.u32All
= blend_reg
;
490 r700
->render_target
[id
].CB_BLEND0_CONTROL
.u32All
= blend_reg
;
495 blend_factor(ctx
->Color
.BlendSrcRGB
, GL_TRUE
),
496 COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
498 blend_factor(ctx
->Color
.BlendDstRGB
, GL_FALSE
),
499 COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
501 switch (ctx
->Color
.BlendEquationRGB
) {
503 eqn
= COMB_DST_PLUS_SRC
;
505 case GL_FUNC_SUBTRACT
:
506 eqn
= COMB_SRC_MINUS_DST
;
508 case GL_FUNC_REVERSE_SUBTRACT
:
509 eqn
= COMB_DST_MINUS_SRC
;
512 eqn
= COMB_MIN_DST_SRC
;
515 COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
518 COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
521 eqn
= COMB_MAX_DST_SRC
;
524 COLOR_SRCBLEND_shift
, COLOR_SRCBLEND_mask
);
527 COLOR_DESTBLEND_shift
, COLOR_DESTBLEND_mask
);
532 "[%s:%u] Invalid RGB blend equation (0x%04x).\n",
533 __FUNCTION__
, __LINE__
, ctx
->Color
.BlendEquationRGB
);
537 eqn
, COLOR_COMB_FCN_shift
, COLOR_COMB_FCN_mask
);
540 blend_factor(ctx
->Color
.BlendSrcRGB
, GL_TRUE
),
541 ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
543 blend_factor(ctx
->Color
.BlendDstRGB
, GL_FALSE
),
544 ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
546 switch (ctx
->Color
.BlendEquationA
) {
548 eqnA
= COMB_DST_PLUS_SRC
;
550 case GL_FUNC_SUBTRACT
:
551 eqnA
= COMB_SRC_MINUS_DST
;
553 case GL_FUNC_REVERSE_SUBTRACT
:
554 eqnA
= COMB_DST_MINUS_SRC
;
557 eqnA
= COMB_MIN_DST_SRC
;
560 ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
563 ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
566 eqnA
= COMB_MAX_DST_SRC
;
569 ALPHA_SRCBLEND_shift
, ALPHA_SRCBLEND_mask
);
572 ALPHA_DESTBLEND_shift
, ALPHA_DESTBLEND_mask
);
576 "[%s:%u] Invalid A blend equation (0x%04x).\n",
577 __FUNCTION__
, __LINE__
, ctx
->Color
.BlendEquationA
);
582 eqnA
, ALPHA_COMB_FCN_shift
, ALPHA_COMB_FCN_mask
);
584 SETbit(blend_reg
, SEPARATE_ALPHA_BLEND_bit
);
586 if (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_R600
)
587 r700
->CB_BLEND_CONTROL
.u32All
= blend_reg
;
589 r700
->render_target
[id
].CB_BLEND0_CONTROL
.u32All
= blend_reg
;
590 SETbit(r700
->CB_COLOR_CONTROL
.u32All
, PER_MRT_BLEND_bit
);
592 SETfield(r700
->CB_COLOR_CONTROL
.u32All
, (1 << id
),
593 TARGET_BLEND_ENABLE_shift
, TARGET_BLEND_ENABLE_mask
);
597 static void r700BlendEquationSeparate(GLcontext
* ctx
,
598 GLenum modeRGB
, GLenum modeA
) //-----------------
600 r700SetBlendState(ctx
);
603 static void r700BlendFuncSeparate(GLcontext
* ctx
,
604 GLenum sfactorRGB
, GLenum dfactorRGB
,
605 GLenum sfactorA
, GLenum dfactorA
) //------------------------
607 r700SetBlendState(ctx
);
611 * Translate LogicOp enums into hardware representation.
613 static GLuint
translate_logicop(GLenum logicop
)
622 case GL_COPY_INVERTED
:
642 case GL_AND_INVERTED
:
649 fprintf(stderr
, "unknown blend logic operation %x\n", logicop
);
655 * Used internally to update the r300->hw hardware state to match the
656 * current OpenGL state.
658 static void r700SetLogicOpState(GLcontext
*ctx
)
660 context_t
*context
= R700_CONTEXT(ctx
);
661 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&R700_CONTEXT(ctx
)->hw
);
663 R600_STATECHANGE(context
, blnd
);
665 if (RGBA_LOGICOP_ENABLED(ctx
))
666 SETfield(r700
->CB_COLOR_CONTROL
.u32All
,
667 translate_logicop(ctx
->Color
.LogicOp
), ROP3_shift
, ROP3_mask
);
669 SETfield(r700
->CB_COLOR_CONTROL
.u32All
, 0xCC, ROP3_shift
, ROP3_mask
);
673 * Called by Mesa when an application program changes the LogicOp state
676 static void r700LogicOpcode(GLcontext
*ctx
, GLenum logicop
)
678 if (RGBA_LOGICOP_ENABLED(ctx
))
679 r700SetLogicOpState(ctx
);
682 static void r700UpdateCulling(GLcontext
* ctx
)
684 context_t
*context
= R700_CONTEXT(ctx
);
685 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&R700_CONTEXT(ctx
)->hw
);
687 R600_STATECHANGE(context
, su
);
689 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
);
690 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
691 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
693 if (ctx
->Polygon
.CullFlag
)
695 switch (ctx
->Polygon
.CullFaceMode
)
698 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
699 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
702 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
703 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
705 case GL_FRONT_AND_BACK
:
706 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
707 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
710 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
711 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
716 switch (ctx
->Polygon
.FrontFace
)
719 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
);
722 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
);
725 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
); /* default: ccw */
730 static void r700UpdateLineStipple(GLcontext
* ctx
)
732 context_t
*context
= R700_CONTEXT(ctx
);
733 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&R700_CONTEXT(ctx
)->hw
);
735 R600_STATECHANGE(context
, sc
);
737 if (ctx
->Line
.StippleFlag
)
739 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, LINE_STIPPLE_ENABLE_bit
);
743 CLEARbit(r700
->PA_SC_MODE_CNTL
.u32All
, LINE_STIPPLE_ENABLE_bit
);
747 static void r700Enable(GLcontext
* ctx
, GLenum cap
, GLboolean state
) //------------------
749 context_t
*context
= R700_CONTEXT(ctx
);
761 r700SetAlphaState(ctx
);
763 case GL_COLOR_LOGIC_OP
:
764 r700SetLogicOpState(ctx
);
765 /* fall-through, because logic op overrides blending */
767 r700SetBlendState(ctx
);
775 r700SetClipPlaneState(ctx
, cap
, state
);
778 r700SetDepthState(ctx
);
780 case GL_STENCIL_TEST
:
781 r700SetStencilState(ctx
, state
);
784 r700UpdateCulling(ctx
);
786 case GL_POLYGON_OFFSET_POINT
:
787 case GL_POLYGON_OFFSET_LINE
:
788 case GL_POLYGON_OFFSET_FILL
:
789 r700SetPolygonOffsetState(ctx
, state
);
791 case GL_SCISSOR_TEST
:
792 radeon_firevertices(&context
->radeon
);
793 context
->radeon
.state
.scissor
.enabled
= state
;
794 radeonUpdateScissor(ctx
);
796 case GL_LINE_STIPPLE
:
797 r700UpdateLineStipple(ctx
);
806 * Handle glColorMask()
808 static void r700ColorMask(GLcontext
* ctx
,
809 GLboolean r
, GLboolean g
, GLboolean b
, GLboolean a
) //------------------
811 context_t
*context
= R700_CONTEXT(ctx
);
812 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&R700_CONTEXT(ctx
)->hw
);
813 unsigned int mask
= ((r
? 1 : 0) |
818 if (mask
!= r700
->CB_SHADER_MASK
.u32All
) {
819 R600_STATECHANGE(context
, cb
);
820 SETfield(r700
->CB_SHADER_MASK
.u32All
, mask
, OUTPUT0_ENABLE_shift
, OUTPUT0_ENABLE_mask
);
825 * Change the depth testing function.
827 * \note Mesa already filters redundant calls to this function.
829 static void r700DepthFunc(GLcontext
* ctx
, GLenum func
) //--------------------
831 r700SetDepthState(ctx
);
835 * Enable/Disable depth writing.
837 * \note Mesa already filters redundant calls to this function.
839 static void r700DepthMask(GLcontext
* ctx
, GLboolean mask
) //------------------
841 r700SetDepthState(ctx
);
845 * Change the culling mode.
847 * \note Mesa already filters redundant calls to this function.
849 static void r700CullFace(GLcontext
* ctx
, GLenum mode
) //-----------------
851 r700UpdateCulling(ctx
);
854 /* =============================================================
857 static void r700Fogfv(GLcontext
* ctx
, GLenum pname
, const GLfloat
* param
) //--------------
862 * Change the polygon orientation.
864 * \note Mesa already filters redundant calls to this function.
866 static void r700FrontFace(GLcontext
* ctx
, GLenum mode
) //------------------
868 r700UpdateCulling(ctx
);
869 r700UpdatePolygonMode(ctx
);
872 static void r700ShadeModel(GLcontext
* ctx
, GLenum mode
) //--------------------
874 context_t
*context
= R700_CONTEXT(ctx
);
875 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
877 R600_STATECHANGE(context
, spi
);
879 /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */
882 SETbit(r700
->SPI_INTERP_CONTROL_0
.u32All
, FLAT_SHADE_ENA_bit
);
885 CLEARbit(r700
->SPI_INTERP_CONTROL_0
.u32All
, FLAT_SHADE_ENA_bit
);
892 /* =============================================================
895 static void r700PointSize(GLcontext
* ctx
, GLfloat size
)
897 context_t
*context
= R700_CONTEXT(ctx
);
898 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
900 R600_STATECHANGE(context
, su
);
902 /* We need to clamp to user defined range here, because
903 * the HW clamping happens only for per vertex point size. */
904 size
= CLAMP(size
, ctx
->Point
.MinSize
, ctx
->Point
.MaxSize
);
906 /* same size limits for AA, non-AA points */
907 size
= CLAMP(size
, ctx
->Const
.MinPointSize
, ctx
->Const
.MaxPointSize
);
909 /* format is 12.4 fixed point */
910 SETfield(r700
->PA_SU_POINT_SIZE
.u32All
, (int)(size
* 16),
911 PA_SU_POINT_SIZE__HEIGHT_shift
, PA_SU_POINT_SIZE__HEIGHT_mask
);
912 SETfield(r700
->PA_SU_POINT_SIZE
.u32All
, (int)(size
* 16),
913 PA_SU_POINT_SIZE__WIDTH_shift
, PA_SU_POINT_SIZE__WIDTH_mask
);
917 static void r700PointParameter(GLcontext
* ctx
, GLenum pname
, const GLfloat
* param
) //---------------
919 context_t
*context
= R700_CONTEXT(ctx
);
920 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
922 R600_STATECHANGE(context
, su
);
924 /* format is 12.4 fixed point */
926 case GL_POINT_SIZE_MIN
:
927 SETfield(r700
->PA_SU_POINT_MINMAX
.u32All
, (int)(ctx
->Point
.MinSize
* 16.0),
928 MIN_SIZE_shift
, MIN_SIZE_mask
);
930 case GL_POINT_SIZE_MAX
:
931 SETfield(r700
->PA_SU_POINT_MINMAX
.u32All
, (int)(ctx
->Point
.MaxSize
* 16.0),
932 MAX_SIZE_shift
, MAX_SIZE_mask
);
934 case GL_POINT_DISTANCE_ATTENUATION
:
936 case GL_POINT_FADE_THRESHOLD_SIZE
:
943 static int translate_stencil_func(int func
)
966 static int translate_stencil_op(int op
)
974 return STENCIL_REPLACE
;
976 return STENCIL_INCR_CLAMP
;
978 return STENCIL_DECR_CLAMP
;
979 case GL_INCR_WRAP_EXT
:
980 return STENCIL_INCR_WRAP
;
981 case GL_DECR_WRAP_EXT
:
982 return STENCIL_DECR_WRAP
;
984 return STENCIL_INVERT
;
986 WARN_ONCE("Do not know how to translate stencil op");
992 static void r700SetStencilState(GLcontext
* ctx
, GLboolean state
)
994 context_t
*context
= R700_CONTEXT(ctx
);
995 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
996 GLboolean hw_stencil
= GL_FALSE
;
999 //r300CatchStencilFallback(ctx);
1001 if (ctx
->DrawBuffer
) {
1002 struct radeon_renderbuffer
*rrbStencil
1003 = radeon_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_STENCIL
);
1004 hw_stencil
= (rrbStencil
&& rrbStencil
->bo
);
1008 R600_STATECHANGE(context
, db
);
1010 SETbit(r700
->DB_DEPTH_CONTROL
.u32All
, STENCIL_ENABLE_bit
);
1012 CLEARbit(r700
->DB_DEPTH_CONTROL
.u32All
, STENCIL_ENABLE_bit
);
1016 static void r700StencilFuncSeparate(GLcontext
* ctx
, GLenum face
,
1017 GLenum func
, GLint ref
, GLuint mask
) //---------------------
1019 context_t
*context
= R700_CONTEXT(ctx
);
1020 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1021 const unsigned back
= ctx
->Stencil
._BackFace
;
1024 //r300CatchStencilFallback(ctx);
1026 R600_STATECHANGE(context
, stencil
);
1029 SETfield(r700
->DB_STENCILREFMASK
.u32All
, ctx
->Stencil
.Ref
[0],
1030 STENCILREF_shift
, STENCILREF_mask
);
1031 SETfield(r700
->DB_STENCILREFMASK
.u32All
, ctx
->Stencil
.ValueMask
[0],
1032 STENCILMASK_shift
, STENCILMASK_mask
);
1034 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_func(ctx
->Stencil
.Function
[0]),
1035 STENCILFUNC_shift
, STENCILFUNC_mask
);
1038 SETfield(r700
->DB_STENCILREFMASK_BF
.u32All
, ctx
->Stencil
.Ref
[back
],
1039 STENCILREF_BF_shift
, STENCILREF_BF_mask
);
1040 SETfield(r700
->DB_STENCILREFMASK_BF
.u32All
, ctx
->Stencil
.ValueMask
[back
],
1041 STENCILMASK_BF_shift
, STENCILMASK_BF_mask
);
1043 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_func(ctx
->Stencil
.Function
[back
]),
1044 STENCILFUNC_BF_shift
, STENCILFUNC_BF_mask
);
1048 static void r700StencilMaskSeparate(GLcontext
* ctx
, GLenum face
, GLuint mask
) //--------------
1050 context_t
*context
= R700_CONTEXT(ctx
);
1051 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1052 const unsigned back
= ctx
->Stencil
._BackFace
;
1055 //r300CatchStencilFallback(ctx);
1057 R600_STATECHANGE(context
, stencil
);
1060 SETfield(r700
->DB_STENCILREFMASK
.u32All
, ctx
->Stencil
.WriteMask
[0],
1061 STENCILWRITEMASK_shift
, STENCILWRITEMASK_mask
);
1064 SETfield(r700
->DB_STENCILREFMASK_BF
.u32All
, ctx
->Stencil
.WriteMask
[back
],
1065 STENCILWRITEMASK_BF_shift
, STENCILWRITEMASK_BF_mask
);
1069 static void r700StencilOpSeparate(GLcontext
* ctx
, GLenum face
,
1070 GLenum fail
, GLenum zfail
, GLenum zpass
) //--------------------
1072 context_t
*context
= R700_CONTEXT(ctx
);
1073 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1074 const unsigned back
= ctx
->Stencil
._BackFace
;
1077 //r300CatchStencilFallback(ctx);
1079 R600_STATECHANGE(context
, db
);
1081 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.FailFunc
[0]),
1082 STENCILFAIL_shift
, STENCILFAIL_mask
);
1083 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.ZFailFunc
[0]),
1084 STENCILZFAIL_shift
, STENCILZFAIL_mask
);
1085 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.ZPassFunc
[0]),
1086 STENCILZPASS_shift
, STENCILZPASS_mask
);
1088 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.FailFunc
[back
]),
1089 STENCILFAIL_BF_shift
, STENCILFAIL_BF_mask
);
1090 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.ZFailFunc
[back
]),
1091 STENCILZFAIL_BF_shift
, STENCILZFAIL_BF_mask
);
1092 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, translate_stencil_op(ctx
->Stencil
.ZPassFunc
[back
]),
1093 STENCILZPASS_BF_shift
, STENCILZPASS_BF_mask
);
1096 static void r700UpdateWindow(GLcontext
* ctx
, int id
) //--------------------
1098 context_t
*context
= R700_CONTEXT(ctx
);
1099 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1100 __DRIdrawablePrivate
*dPriv
= radeon_get_drawable(&context
->radeon
);
1101 GLfloat xoffset
= dPriv
? (GLfloat
) dPriv
->x
: 0;
1102 GLfloat yoffset
= dPriv
? (GLfloat
) dPriv
->y
+ dPriv
->h
: 0;
1103 const GLfloat
*v
= ctx
->Viewport
._WindowMap
.m
;
1104 const GLfloat depthScale
= 1.0F
/ ctx
->DrawBuffer
->_DepthMaxF
;
1105 const GLboolean render_to_fbo
= (ctx
->DrawBuffer
->Name
!= 0);
1106 GLfloat y_scale
, y_bias
;
1108 if (render_to_fbo
) {
1116 GLfloat sx
= v
[MAT_SX
];
1117 GLfloat tx
= v
[MAT_TX
] + xoffset
;
1118 GLfloat sy
= v
[MAT_SY
] * y_scale
;
1119 GLfloat ty
= (v
[MAT_TY
] * y_scale
) + y_bias
;
1120 GLfloat sz
= v
[MAT_SZ
] * depthScale
;
1121 GLfloat tz
= v
[MAT_TZ
] * depthScale
;
1123 R600_STATECHANGE(context
, vpt
);
1125 r700
->viewport
[id
].PA_CL_VPORT_XSCALE
.f32All
= sx
;
1126 r700
->viewport
[id
].PA_CL_VPORT_XOFFSET
.f32All
= tx
;
1128 r700
->viewport
[id
].PA_CL_VPORT_YSCALE
.f32All
= sy
;
1129 r700
->viewport
[id
].PA_CL_VPORT_YOFFSET
.f32All
= ty
;
1131 r700
->viewport
[id
].PA_CL_VPORT_ZSCALE
.f32All
= sz
;
1132 r700
->viewport
[id
].PA_CL_VPORT_ZOFFSET
.f32All
= tz
;
1134 r700
->viewport
[id
].enabled
= GL_TRUE
;
1136 r700SetScissor(context
);
1140 static void r700Viewport(GLcontext
* ctx
,
1144 GLsizei height
) //--------------------
1146 r700UpdateWindow(ctx
, 0);
1148 radeon_viewport(ctx
, x
, y
, width
, height
);
1151 static void r700DepthRange(GLcontext
* ctx
, GLclampd nearval
, GLclampd farval
) //-------------
1153 r700UpdateWindow(ctx
, 0);
1156 static void r700LineWidth(GLcontext
* ctx
, GLfloat widthf
) //---------------
1158 context_t
*context
= R700_CONTEXT(ctx
);
1159 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1160 uint32_t lineWidth
= (uint32_t)((widthf
* 0.5) * (1 << 4));
1162 R600_STATECHANGE(context
, su
);
1164 if (lineWidth
> 0xFFFF)
1166 SETfield(r700
->PA_SU_LINE_CNTL
.u32All
,(uint16_t)lineWidth
,
1167 PA_SU_LINE_CNTL__WIDTH_shift
, PA_SU_LINE_CNTL__WIDTH_mask
);
1170 static void r700LineStipple(GLcontext
*ctx
, GLint factor
, GLushort pattern
)
1172 context_t
*context
= R700_CONTEXT(ctx
);
1173 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1175 R600_STATECHANGE(context
, sc
);
1177 SETfield(r700
->PA_SC_LINE_STIPPLE
.u32All
, pattern
, LINE_PATTERN_shift
, LINE_PATTERN_mask
);
1178 SETfield(r700
->PA_SC_LINE_STIPPLE
.u32All
, (factor
-1), REPEAT_COUNT_shift
, REPEAT_COUNT_mask
);
1179 SETfield(r700
->PA_SC_LINE_STIPPLE
.u32All
, 1, AUTO_RESET_CNTL_shift
, AUTO_RESET_CNTL_mask
);
1182 static void r700SetPolygonOffsetState(GLcontext
* ctx
, GLboolean state
)
1184 context_t
*context
= R700_CONTEXT(ctx
);
1185 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1187 R600_STATECHANGE(context
, su
);
1190 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_FRONT_ENABLE_bit
);
1191 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_BACK_ENABLE_bit
);
1192 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_PARA_ENABLE_bit
);
1194 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_FRONT_ENABLE_bit
);
1195 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_BACK_ENABLE_bit
);
1196 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, POLY_OFFSET_PARA_ENABLE_bit
);
1200 static void r700PolygonOffset(GLcontext
* ctx
, GLfloat factor
, GLfloat units
) //--------------
1202 context_t
*context
= R700_CONTEXT(ctx
);
1203 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1204 GLfloat constant
= units
;
1206 switch (ctx
->Visual
.depthBits
) {
1217 R600_STATECHANGE(context
, poly
);
1219 r700
->PA_SU_POLY_OFFSET_FRONT_SCALE
.f32All
= factor
;
1220 r700
->PA_SU_POLY_OFFSET_FRONT_OFFSET
.f32All
= constant
;
1221 r700
->PA_SU_POLY_OFFSET_BACK_SCALE
.f32All
= factor
;
1222 r700
->PA_SU_POLY_OFFSET_BACK_OFFSET
.f32All
= constant
;
1225 static void r700UpdatePolygonMode(GLcontext
* ctx
)
1227 context_t
*context
= R700_CONTEXT(ctx
);
1228 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1230 R600_STATECHANGE(context
, su
);
1232 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DISABLE_POLY_MODE
, POLY_MODE_shift
, POLY_MODE_mask
);
1234 /* Only do something if a polygon mode is wanted, default is GL_FILL */
1235 if (ctx
->Polygon
.FrontMode
!= GL_FILL
||
1236 ctx
->Polygon
.BackMode
!= GL_FILL
) {
1239 /* Handle GL_CW (clock wise and GL_CCW (counter clock wise)
1240 * correctly by selecting the correct front and back face
1242 if (ctx
->Polygon
.FrontFace
== GL_CCW
) {
1243 f
= ctx
->Polygon
.FrontMode
;
1244 b
= ctx
->Polygon
.BackMode
;
1246 f
= ctx
->Polygon
.BackMode
;
1247 b
= ctx
->Polygon
.FrontMode
;
1250 /* Enable polygon mode */
1251 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DUAL_MODE
, POLY_MODE_shift
, POLY_MODE_mask
);
1255 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_LINES
,
1256 POLYMODE_FRONT_PTYPE_shift
, POLYMODE_FRONT_PTYPE_mask
);
1259 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_POINTS
,
1260 POLYMODE_FRONT_PTYPE_shift
, POLYMODE_FRONT_PTYPE_mask
);
1263 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_TRIANGLES
,
1264 POLYMODE_FRONT_PTYPE_shift
, POLYMODE_FRONT_PTYPE_mask
);
1270 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_LINES
,
1271 POLYMODE_BACK_PTYPE_shift
, POLYMODE_BACK_PTYPE_mask
);
1274 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_POINTS
,
1275 POLYMODE_BACK_PTYPE_shift
, POLYMODE_BACK_PTYPE_mask
);
1278 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_TRIANGLES
,
1279 POLYMODE_BACK_PTYPE_shift
, POLYMODE_BACK_PTYPE_mask
);
1285 static void r700PolygonMode(GLcontext
* ctx
, GLenum face
, GLenum mode
) //------------------
1290 r700UpdatePolygonMode(ctx
);
1293 static void r700RenderMode(GLcontext
* ctx
, GLenum mode
) //---------------------
1297 static void r700ClipPlane( GLcontext
*ctx
, GLenum plane
, const GLfloat
*eq
)
1299 context_t
*context
= R700_CONTEXT(ctx
);
1300 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1304 p
= (GLint
) plane
- (GLint
) GL_CLIP_PLANE0
;
1305 ip
= (GLint
*)ctx
->Transform
._ClipUserPlane
[p
];
1307 R600_STATECHANGE(context
, ucp
);
1309 r700
->ucp
[p
].PA_CL_UCP_0_X
.u32All
= ip
[0];
1310 r700
->ucp
[p
].PA_CL_UCP_0_Y
.u32All
= ip
[1];
1311 r700
->ucp
[p
].PA_CL_UCP_0_Z
.u32All
= ip
[2];
1312 r700
->ucp
[p
].PA_CL_UCP_0_W
.u32All
= ip
[3];
1315 static void r700SetClipPlaneState(GLcontext
* ctx
, GLenum cap
, GLboolean state
)
1317 context_t
*context
= R700_CONTEXT(ctx
);
1318 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1321 p
= cap
- GL_CLIP_PLANE0
;
1323 R600_STATECHANGE(context
, cl
);
1326 r700
->PA_CL_CLIP_CNTL
.u32All
|= (UCP_ENA_0_bit
<< p
);
1327 r700
->ucp
[p
].enabled
= GL_TRUE
;
1328 r700ClipPlane(ctx
, cap
, NULL
);
1330 r700
->PA_CL_CLIP_CNTL
.u32All
&= ~(UCP_ENA_0_bit
<< p
);
1331 r700
->ucp
[p
].enabled
= GL_FALSE
;
1335 void r700SetScissor(context_t
*context
) //---------------
1337 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1338 unsigned x1
, y1
, x2
, y2
;
1340 struct radeon_renderbuffer
*rrb
;
1342 rrb
= radeon_get_colorbuffer(&context
->radeon
);
1343 if (!rrb
|| !rrb
->bo
) {
1346 if (context
->radeon
.state
.scissor
.enabled
) {
1347 x1
= context
->radeon
.state
.scissor
.rect
.x1
;
1348 y1
= context
->radeon
.state
.scissor
.rect
.y1
;
1349 x2
= context
->radeon
.state
.scissor
.rect
.x2
- 1;
1350 y2
= context
->radeon
.state
.scissor
.rect
.y2
- 1;
1352 if (context
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
1355 x2
= rrb
->base
.Width
- 1;
1356 y2
= rrb
->base
.Height
- 1;
1360 x2
= rrb
->dPriv
->x
+ rrb
->dPriv
->w
;
1361 y2
= rrb
->dPriv
->y
+ rrb
->dPriv
->h
;
1365 R600_STATECHANGE(context
, scissor
);
1368 SETbit(r700
->PA_SC_SCREEN_SCISSOR_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
1369 SETfield(r700
->PA_SC_SCREEN_SCISSOR_TL
.u32All
, x1
,
1370 PA_SC_SCREEN_SCISSOR_TL__TL_X_shift
, PA_SC_SCREEN_SCISSOR_TL__TL_X_mask
);
1371 SETfield(r700
->PA_SC_SCREEN_SCISSOR_TL
.u32All
, y1
,
1372 PA_SC_SCREEN_SCISSOR_TL__TL_Y_shift
, PA_SC_SCREEN_SCISSOR_TL__TL_Y_mask
);
1374 SETfield(r700
->PA_SC_SCREEN_SCISSOR_BR
.u32All
, x2
,
1375 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift
, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask
);
1376 SETfield(r700
->PA_SC_SCREEN_SCISSOR_BR
.u32All
, y2
,
1377 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift
, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask
);
1380 SETbit(r700
->PA_SC_WINDOW_SCISSOR_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
1381 SETfield(r700
->PA_SC_WINDOW_SCISSOR_TL
.u32All
, x1
,
1382 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift
, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask
);
1383 SETfield(r700
->PA_SC_WINDOW_SCISSOR_TL
.u32All
, y1
,
1384 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift
, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask
);
1386 SETfield(r700
->PA_SC_WINDOW_SCISSOR_BR
.u32All
, x2
,
1387 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift
, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask
);
1388 SETfield(r700
->PA_SC_WINDOW_SCISSOR_BR
.u32All
, y2
,
1389 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift
, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask
);
1392 SETfield(r700
->PA_SC_CLIPRECT_0_TL
.u32All
, x1
,
1393 PA_SC_CLIPRECT_0_TL__TL_X_shift
, PA_SC_CLIPRECT_0_TL__TL_X_mask
);
1394 SETfield(r700
->PA_SC_CLIPRECT_0_TL
.u32All
, y1
,
1395 PA_SC_CLIPRECT_0_TL__TL_Y_shift
, PA_SC_CLIPRECT_0_TL__TL_Y_mask
);
1396 SETfield(r700
->PA_SC_CLIPRECT_0_BR
.u32All
, x2
,
1397 PA_SC_CLIPRECT_0_BR__BR_X_shift
, PA_SC_CLIPRECT_0_BR__BR_X_mask
);
1398 SETfield(r700
->PA_SC_CLIPRECT_0_BR
.u32All
, y2
,
1399 PA_SC_CLIPRECT_0_BR__BR_Y_shift
, PA_SC_CLIPRECT_0_BR__BR_Y_mask
);
1401 r700
->PA_SC_CLIPRECT_1_TL
.u32All
= r700
->PA_SC_CLIPRECT_0_TL
.u32All
;
1402 r700
->PA_SC_CLIPRECT_1_BR
.u32All
= r700
->PA_SC_CLIPRECT_0_BR
.u32All
;
1403 r700
->PA_SC_CLIPRECT_2_TL
.u32All
= r700
->PA_SC_CLIPRECT_0_TL
.u32All
;
1404 r700
->PA_SC_CLIPRECT_2_BR
.u32All
= r700
->PA_SC_CLIPRECT_0_BR
.u32All
;
1405 r700
->PA_SC_CLIPRECT_3_TL
.u32All
= r700
->PA_SC_CLIPRECT_0_TL
.u32All
;
1406 r700
->PA_SC_CLIPRECT_3_BR
.u32All
= r700
->PA_SC_CLIPRECT_0_BR
.u32All
;
1408 /* more....2d clip */
1409 SETbit(r700
->PA_SC_GENERIC_SCISSOR_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
1410 SETfield(r700
->PA_SC_GENERIC_SCISSOR_TL
.u32All
, x1
,
1411 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift
, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask
);
1412 SETfield(r700
->PA_SC_GENERIC_SCISSOR_TL
.u32All
, y1
,
1413 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift
, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask
);
1414 SETfield(r700
->PA_SC_GENERIC_SCISSOR_BR
.u32All
, x2
,
1415 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift
, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask
);
1416 SETfield(r700
->PA_SC_GENERIC_SCISSOR_BR
.u32All
, y2
,
1417 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift
, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask
);
1419 SETbit(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
1420 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_TL
.u32All
, x1
,
1421 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift
, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask
);
1422 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_TL
.u32All
, y1
,
1423 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift
, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask
);
1424 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_BR
.u32All
, x2
,
1425 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift
, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask
);
1426 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_BR
.u32All
, y2
,
1427 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift
, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask
);
1429 r700
->viewport
[id
].PA_SC_VPORT_ZMIN_0
.u32All
= 0;
1430 r700
->viewport
[id
].PA_SC_VPORT_ZMAX_0
.u32All
= 0x3F800000;
1431 r700
->viewport
[id
].enabled
= GL_TRUE
;
1434 static void r700SetRenderTarget(context_t
*context
, int id
)
1436 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1438 struct radeon_renderbuffer
*rrb
;
1439 unsigned int nPitchInPixel
;
1441 rrb
= radeon_get_colorbuffer(&context
->radeon
);
1442 if (!rrb
|| !rrb
->bo
) {
1446 R600_STATECHANGE(context
, cb_target
);
1447 R600_STATECHANGE(context
, cb
);
1449 /* screen/window/view */
1450 SETfield(r700
->CB_TARGET_MASK
.u32All
, 0xF, (4 * id
), TARGET0_ENABLE_mask
);
1453 r700
->render_target
[id
].CB_COLOR0_BASE
.u32All
= context
->radeon
.state
.color
.draw_offset
;
1455 nPitchInPixel
= rrb
->pitch
/rrb
->cpp
;
1456 SETfield(r700
->render_target
[id
].CB_COLOR0_SIZE
.u32All
, (nPitchInPixel
/8)-1,
1457 PITCH_TILE_MAX_shift
, PITCH_TILE_MAX_mask
);
1458 SETfield(r700
->render_target
[id
].CB_COLOR0_SIZE
.u32All
, ( (nPitchInPixel
* context
->radeon
.radeonScreen
->driScreen
->fbHeight
)/64 )-1,
1459 SLICE_TILE_MAX_shift
, SLICE_TILE_MAX_mask
);
1460 r700
->render_target
[id
].CB_COLOR0_BASE
.u32All
= 0;
1461 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, ENDIAN_NONE
, ENDIAN_shift
, ENDIAN_mask
);
1462 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, ARRAY_LINEAR_GENERAL
,
1463 CB_COLOR0_INFO__ARRAY_MODE_shift
, CB_COLOR0_INFO__ARRAY_MODE_mask
);
1466 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, COLOR_8_8_8_8
,
1467 CB_COLOR0_INFO__FORMAT_shift
, CB_COLOR0_INFO__FORMAT_mask
);
1468 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, SWAP_ALT
, COMP_SWAP_shift
, COMP_SWAP_mask
);
1472 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, COLOR_5_6_5
,
1473 CB_COLOR0_INFO__FORMAT_shift
, CB_COLOR0_INFO__FORMAT_mask
);
1474 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, SWAP_ALT_REV
,
1475 COMP_SWAP_shift
, COMP_SWAP_mask
);
1477 SETbit(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, SOURCE_FORMAT_bit
);
1478 SETbit(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, BLEND_CLAMP_bit
);
1479 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
1481 r700
->render_target
[id
].enabled
= GL_TRUE
;
1484 static void r700SetDepthTarget(context_t
*context
)
1486 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1488 struct radeon_renderbuffer
*rrb
;
1489 unsigned int nPitchInPixel
;
1491 rrb
= radeon_get_depthbuffer(&context
->radeon
);
1495 R600_STATECHANGE(context
, db_target
);
1498 r700
->DB_DEPTH_SIZE
.u32All
= 0;
1499 r700
->DB_DEPTH_BASE
.u32All
= 0;
1500 r700
->DB_DEPTH_INFO
.u32All
= 0;
1501 r700
->DB_DEPTH_VIEW
.u32All
= 0;
1503 nPitchInPixel
= rrb
->pitch
/rrb
->cpp
;
1505 SETfield(r700
->DB_DEPTH_SIZE
.u32All
, (nPitchInPixel
/8)-1,
1506 PITCH_TILE_MAX_shift
, PITCH_TILE_MAX_mask
);
1507 SETfield(r700
->DB_DEPTH_SIZE
.u32All
, ( (nPitchInPixel
* context
->radeon
.radeonScreen
->driScreen
->fbHeight
)/64 )-1,
1508 SLICE_TILE_MAX_shift
, SLICE_TILE_MAX_mask
); /* size in pixel / 64 - 1 */
1512 switch (GL_CONTEXT(context
)->Visual
.depthBits
)
1516 SETfield(r700
->DB_DEPTH_INFO
.u32All
, DEPTH_8_24
,
1517 DB_DEPTH_INFO__FORMAT_shift
, DB_DEPTH_INFO__FORMAT_mask
);
1520 fprintf(stderr
, "Error: Unsupported depth %d... exiting\n",
1521 GL_CONTEXT(context
)->Visual
.depthBits
);
1527 SETfield(r700
->DB_DEPTH_INFO
.u32All
, DEPTH_16
,
1528 DB_DEPTH_INFO__FORMAT_shift
, DB_DEPTH_INFO__FORMAT_mask
);
1530 SETfield(r700
->DB_DEPTH_INFO
.u32All
, ARRAY_2D_TILED_THIN1
,
1531 DB_DEPTH_INFO__ARRAY_MODE_shift
, DB_DEPTH_INFO__ARRAY_MODE_mask
);
1532 /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */
1535 static void r700InitSQConfig(GLcontext
* ctx
)
1537 context_t
*context
= R700_CONTEXT(ctx
);
1538 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1552 int num_ps_stack_entries
;
1553 int num_vs_stack_entries
;
1554 int num_gs_stack_entries
;
1555 int num_es_stack_entries
;
1557 R600_STATECHANGE(context
, sq
);
1564 switch (context
->radeon
.radeonScreen
->chip_family
) {
1565 case CHIP_FAMILY_R600
:
1571 num_ps_threads
= 136;
1572 num_vs_threads
= 48;
1575 num_ps_stack_entries
= 128;
1576 num_vs_stack_entries
= 128;
1577 num_gs_stack_entries
= 0;
1578 num_es_stack_entries
= 0;
1580 case CHIP_FAMILY_RV630
:
1581 case CHIP_FAMILY_RV635
:
1587 num_ps_threads
= 144;
1588 num_vs_threads
= 40;
1591 num_ps_stack_entries
= 40;
1592 num_vs_stack_entries
= 40;
1593 num_gs_stack_entries
= 32;
1594 num_es_stack_entries
= 16;
1596 case CHIP_FAMILY_RV610
:
1597 case CHIP_FAMILY_RV620
:
1598 case CHIP_FAMILY_RS780
:
1599 case CHIP_FAMILY_RS880
:
1606 num_ps_threads
= 136;
1607 num_vs_threads
= 48;
1610 num_ps_stack_entries
= 40;
1611 num_vs_stack_entries
= 40;
1612 num_gs_stack_entries
= 32;
1613 num_es_stack_entries
= 16;
1615 case CHIP_FAMILY_RV670
:
1621 num_ps_threads
= 136;
1622 num_vs_threads
= 48;
1625 num_ps_stack_entries
= 40;
1626 num_vs_stack_entries
= 40;
1627 num_gs_stack_entries
= 32;
1628 num_es_stack_entries
= 16;
1630 case CHIP_FAMILY_RV770
:
1636 num_ps_threads
= 188;
1637 num_vs_threads
= 60;
1640 num_ps_stack_entries
= 256;
1641 num_vs_stack_entries
= 256;
1642 num_gs_stack_entries
= 0;
1643 num_es_stack_entries
= 0;
1645 case CHIP_FAMILY_RV730
:
1646 case CHIP_FAMILY_RV740
:
1652 num_ps_threads
= 188;
1653 num_vs_threads
= 60;
1656 num_ps_stack_entries
= 128;
1657 num_vs_stack_entries
= 128;
1658 num_gs_stack_entries
= 0;
1659 num_es_stack_entries
= 0;
1661 case CHIP_FAMILY_RV710
:
1667 num_ps_threads
= 144;
1668 num_vs_threads
= 48;
1671 num_ps_stack_entries
= 128;
1672 num_vs_stack_entries
= 128;
1673 num_gs_stack_entries
= 0;
1674 num_es_stack_entries
= 0;
1678 r700
->sq_config
.SQ_CONFIG
.u32All
= 0;
1679 if ((context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV610
) ||
1680 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV620
) ||
1681 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RS780
) ||
1682 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RS880
) ||
1683 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV710
))
1684 CLEARbit(r700
->sq_config
.SQ_CONFIG
.u32All
, VC_ENABLE_bit
);
1686 SETbit(r700
->sq_config
.SQ_CONFIG
.u32All
, VC_ENABLE_bit
);
1687 SETbit(r700
->sq_config
.SQ_CONFIG
.u32All
, DX9_CONSTS_bit
);
1688 SETbit(r700
->sq_config
.SQ_CONFIG
.u32All
, ALU_INST_PREFER_VECTOR_bit
);
1689 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, ps_prio
, PS_PRIO_shift
, PS_PRIO_mask
);
1690 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, ps_prio
, VS_PRIO_shift
, VS_PRIO_mask
);
1691 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, ps_prio
, GS_PRIO_shift
, GS_PRIO_mask
);
1692 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, ps_prio
, ES_PRIO_shift
, ES_PRIO_mask
);
1694 r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
= 0;
1695 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
, num_ps_gprs
, NUM_PS_GPRS_shift
, NUM_PS_GPRS_mask
);
1696 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
, num_vs_gprs
, NUM_VS_GPRS_shift
, NUM_VS_GPRS_mask
);
1697 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
, num_temp_gprs
,
1698 NUM_CLAUSE_TEMP_GPRS_shift
, NUM_CLAUSE_TEMP_GPRS_mask
);
1700 r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_2
.u32All
= 0;
1701 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_2
.u32All
, num_gs_gprs
, NUM_GS_GPRS_shift
, NUM_GS_GPRS_mask
);
1702 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_2
.u32All
, num_es_gprs
, NUM_ES_GPRS_shift
, NUM_ES_GPRS_mask
);
1704 r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
= 0;
1705 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_ps_threads
,
1706 NUM_PS_THREADS_shift
, NUM_PS_THREADS_mask
);
1707 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_vs_threads
,
1708 NUM_VS_THREADS_shift
, NUM_VS_THREADS_mask
);
1709 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_gs_threads
,
1710 NUM_GS_THREADS_shift
, NUM_GS_THREADS_mask
);
1711 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_es_threads
,
1712 NUM_ES_THREADS_shift
, NUM_ES_THREADS_mask
);
1714 r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_1
.u32All
= 0;
1715 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_1
.u32All
, num_ps_stack_entries
,
1716 NUM_PS_STACK_ENTRIES_shift
, NUM_PS_STACK_ENTRIES_mask
);
1717 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_1
.u32All
, num_vs_stack_entries
,
1718 NUM_VS_STACK_ENTRIES_shift
, NUM_VS_STACK_ENTRIES_mask
);
1720 r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_2
.u32All
= 0;
1721 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_2
.u32All
, num_gs_stack_entries
,
1722 NUM_GS_STACK_ENTRIES_shift
, NUM_GS_STACK_ENTRIES_mask
);
1723 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_2
.u32All
, num_es_stack_entries
,
1724 NUM_ES_STACK_ENTRIES_shift
, NUM_ES_STACK_ENTRIES_mask
);
1729 * Calculate initial hardware state and register state functions.
1730 * Assumes that the command buffer and state atoms have been
1731 * initialized already.
1733 void r700InitState(GLcontext
* ctx
) //-------------------
1735 context_t
*context
= R700_CONTEXT(ctx
);
1736 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1738 radeon_firevertices(&context
->radeon
);
1740 r700
->TA_CNTL_AUX
.u32All
= 0;
1741 SETfield(r700
->TA_CNTL_AUX
.u32All
, 28, TD_FIFO_CREDIT_shift
, TD_FIFO_CREDIT_mask
);
1742 r700
->VC_ENHANCE
.u32All
= 0;
1743 r700
->DB_WATERMARKS
.u32All
= 0;
1744 SETfield(r700
->DB_WATERMARKS
.u32All
, 4, DEPTH_FREE_shift
, DEPTH_FREE_mask
);
1745 SETfield(r700
->DB_WATERMARKS
.u32All
, 16, DEPTH_FLUSH_shift
, DEPTH_FLUSH_mask
);
1746 SETfield(r700
->DB_WATERMARKS
.u32All
, 0, FORCE_SUMMARIZE_shift
, FORCE_SUMMARIZE_mask
);
1747 SETfield(r700
->DB_WATERMARKS
.u32All
, 4, DEPTH_PENDING_FREE_shift
, DEPTH_PENDING_FREE_mask
);
1748 r700
->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
.u32All
= 0;
1749 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
) {
1750 SETfield(r700
->TA_CNTL_AUX
.u32All
, 3, GRADIENT_CREDIT_shift
, GRADIENT_CREDIT_mask
);
1751 r700
->DB_DEBUG
.u32All
= 0x82000000;
1752 SETfield(r700
->DB_WATERMARKS
.u32All
, 16, DEPTH_CACHELINE_FREE_shift
, DEPTH_CACHELINE_FREE_mask
);
1754 SETfield(r700
->TA_CNTL_AUX
.u32All
, 2, GRADIENT_CREDIT_shift
, GRADIENT_CREDIT_mask
);
1755 SETfield(r700
->DB_WATERMARKS
.u32All
, 4, DEPTH_CACHELINE_FREE_shift
, DEPTH_CACHELINE_FREE_mask
);
1756 SETbit(r700
->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
.u32All
, VS_PC_LIMIT_ENABLE_bit
);
1759 /* Turn off vgt reuse */
1760 r700
->VGT_REUSE_OFF
.u32All
= 0;
1761 SETbit(r700
->VGT_REUSE_OFF
.u32All
, REUSE_OFF_bit
);
1763 /* Specify offsetting and clamp values for vertices */
1764 r700
->VGT_MAX_VTX_INDX
.u32All
= 0xFFFFFF;
1765 r700
->VGT_MIN_VTX_INDX
.u32All
= 0;
1766 r700
->VGT_INDX_OFFSET
.u32All
= 0;
1768 /* default shader connections. */
1769 r700
->SPI_VS_OUT_ID_0
.u32All
= 0x03020100;
1770 r700
->SPI_VS_OUT_ID_1
.u32All
= 0x07060504;
1771 r700
->SPI_VS_OUT_ID_2
.u32All
= 0x0b0a0908;
1772 r700
->SPI_VS_OUT_ID_3
.u32All
= 0x0f0e0d0c;
1774 r700
->SPI_THREAD_GROUPING
.u32All
= 0;
1775 if (context
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV770
)
1776 SETfield(r700
->SPI_THREAD_GROUPING
.u32All
, 1, PS_GROUPING_shift
, PS_GROUPING_mask
);
1778 /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
1779 r700
->PA_SC_CLIPRECT_RULE
.u32All
= 0;
1780 SETfield(r700
->PA_SC_CLIPRECT_RULE
.u32All
, CLIP_RULE_mask
, CLIP_RULE_shift
, CLIP_RULE_mask
);
1782 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
)
1783 r700
->PA_SC_EDGERULE
.u32All
= 0;
1785 r700
->PA_SC_EDGERULE
.u32All
= 0xAAAAAAAA;
1787 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
) {
1788 r700
->PA_SC_MODE_CNTL
.u32All
= 0;
1789 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, WALK_ORDER_ENABLE_bit
);
1790 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, FORCE_EOV_CNTDWN_ENABLE_bit
);
1792 r700
->PA_SC_MODE_CNTL
.u32All
= 0x00500000;
1793 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, FORCE_EOV_REZ_ENABLE_bit
);
1794 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, FORCE_EOV_CNTDWN_ENABLE_bit
);
1797 /* Do scale XY and Z by 1/W0. */
1798 r700
->bEnablePerspective
= GL_TRUE
;
1799 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_XY_FMT_bit
);
1800 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_Z_FMT_bit
);
1801 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_W0_FMT_bit
);
1803 /* Enable viewport scaling for all three axis */
1804 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_X_SCALE_ENA_bit
);
1805 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_X_OFFSET_ENA_bit
);
1806 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Y_SCALE_ENA_bit
);
1807 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Y_OFFSET_ENA_bit
);
1808 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Z_SCALE_ENA_bit
);
1809 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Z_OFFSET_ENA_bit
);
1811 /* GL uses last vtx for flat shading components */
1812 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, PROVOKING_VTX_LAST_bit
);
1814 /* Set up vertex control */
1815 r700
->PA_SU_VTX_CNTL
.u32All
= 0;
1816 CLEARfield(r700
->PA_SU_VTX_CNTL
.u32All
, QUANT_MODE_mask
);
1817 SETbit(r700
->PA_SU_VTX_CNTL
.u32All
, PIX_CENTER_bit
);
1818 SETfield(r700
->PA_SU_VTX_CNTL
.u32All
, X_ROUND_TO_EVEN
,
1819 PA_SU_VTX_CNTL__ROUND_MODE_shift
, PA_SU_VTX_CNTL__ROUND_MODE_mask
);
1821 /* to 1.0 = no guard band */
1822 r700
->PA_CL_GB_VERT_CLIP_ADJ
.u32All
= 0x3F800000; /* 1.0 */
1823 r700
->PA_CL_GB_VERT_DISC_ADJ
.u32All
= 0x3F800000;
1824 r700
->PA_CL_GB_HORZ_CLIP_ADJ
.u32All
= 0x3F800000;
1825 r700
->PA_CL_GB_HORZ_DISC_ADJ
.u32All
= 0x3F800000;
1827 /* Enable all samples for multi-sample anti-aliasing */
1828 r700
->PA_SC_AA_MASK
.u32All
= 0xFFFFFFFF;
1830 r700
->PA_SC_AA_CONFIG
.u32All
= 0;
1832 r700
->SX_MISC
.u32All
= 0;
1834 r700InitSQConfig(ctx
);
1837 ctx
->Color
.ColorMask
[RCOMP
],
1838 ctx
->Color
.ColorMask
[GCOMP
],
1839 ctx
->Color
.ColorMask
[BCOMP
],
1840 ctx
->Color
.ColorMask
[ACOMP
]);
1842 r700Enable(ctx
, GL_DEPTH_TEST
, ctx
->Depth
.Test
);
1843 r700DepthMask(ctx
, ctx
->Depth
.Mask
);
1844 r700DepthFunc(ctx
, ctx
->Depth
.Func
);
1845 SETbit(r700
->DB_SHADER_CONTROL
.u32All
, DUAL_EXPORT_ENABLE_bit
);
1847 r700
->DB_DEPTH_CLEAR
.u32All
= 0x3F800000;
1849 r700
->DB_RENDER_CONTROL
.u32All
= 0;
1850 SETbit(r700
->DB_RENDER_CONTROL
.u32All
, STENCIL_COMPRESS_DISABLE_bit
);
1851 SETbit(r700
->DB_RENDER_CONTROL
.u32All
, DEPTH_COMPRESS_DISABLE_bit
);
1852 r700
->DB_RENDER_OVERRIDE
.u32All
= 0;
1853 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
)
1854 SETbit(r700
->DB_RENDER_OVERRIDE
.u32All
, FORCE_SHADER_Z_ORDER_bit
);
1855 SETfield(r700
->DB_RENDER_OVERRIDE
.u32All
, FORCE_DISABLE
, FORCE_HIZ_ENABLE_shift
, FORCE_HIZ_ENABLE_mask
);
1856 SETfield(r700
->DB_RENDER_OVERRIDE
.u32All
, FORCE_DISABLE
, FORCE_HIS_ENABLE0_shift
, FORCE_HIS_ENABLE0_mask
);
1857 SETfield(r700
->DB_RENDER_OVERRIDE
.u32All
, FORCE_DISABLE
, FORCE_HIS_ENABLE1_shift
, FORCE_HIS_ENABLE1_mask
);
1859 r700
->DB_ALPHA_TO_MASK
.u32All
= 0;
1860 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET0_shift
, ALPHA_TO_MASK_OFFSET0_mask
);
1861 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET1_shift
, ALPHA_TO_MASK_OFFSET1_mask
);
1862 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET2_shift
, ALPHA_TO_MASK_OFFSET2_mask
);
1863 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET3_shift
, ALPHA_TO_MASK_OFFSET3_mask
);
1866 r700Enable(ctx
, GL_STENCIL_TEST
, ctx
->Stencil
._Enabled
);
1867 r700StencilMaskSeparate(ctx
, 0, ctx
->Stencil
.WriteMask
[0]);
1868 r700StencilFuncSeparate(ctx
, 0, ctx
->Stencil
.Function
[0],
1869 ctx
->Stencil
.Ref
[0], ctx
->Stencil
.ValueMask
[0]);
1870 r700StencilOpSeparate(ctx
, 0, ctx
->Stencil
.FailFunc
[0],
1871 ctx
->Stencil
.ZFailFunc
[0],
1872 ctx
->Stencil
.ZPassFunc
[0]);
1874 r700UpdateCulling(ctx
);
1876 r700SetBlendState(ctx
);
1877 r700SetLogicOpState(ctx
);
1879 r700AlphaFunc(ctx
, ctx
->Color
.AlphaFunc
, ctx
->Color
.AlphaRef
);
1880 r700Enable(ctx
, GL_ALPHA_TEST
, ctx
->Color
.AlphaEnabled
);
1882 r700PointSize(ctx
, 1.0);
1884 CLEARfield(r700
->PA_SU_POINT_MINMAX
.u32All
, MIN_SIZE_mask
);
1885 SETfield(r700
->PA_SU_POINT_MINMAX
.u32All
, 0x8000, MAX_SIZE_shift
, MAX_SIZE_mask
);
1887 r700LineWidth(ctx
, 1.0);
1889 r700
->PA_SC_LINE_CNTL
.u32All
= 0;
1890 CLEARbit(r700
->PA_SC_LINE_CNTL
.u32All
, EXPAND_LINE_WIDTH_bit
);
1891 SETbit(r700
->PA_SC_LINE_CNTL
.u32All
, LAST_PIXEL_bit
);
1893 r700ShadeModel(ctx
, ctx
->Light
.ShadeModel
);
1894 r700PolygonMode(ctx
, GL_FRONT
, ctx
->Polygon
.FrontMode
);
1895 r700PolygonMode(ctx
, GL_BACK
, ctx
->Polygon
.BackMode
);
1896 r700PolygonOffset(ctx
, ctx
->Polygon
.OffsetFactor
,
1897 ctx
->Polygon
.OffsetUnits
);
1898 r700Enable(ctx
, GL_POLYGON_OFFSET_POINT
, ctx
->Polygon
.OffsetPoint
);
1899 r700Enable(ctx
, GL_POLYGON_OFFSET_LINE
, ctx
->Polygon
.OffsetLine
);
1900 r700Enable(ctx
, GL_POLYGON_OFFSET_FILL
, ctx
->Polygon
.OffsetFill
);
1903 r700BlendColor(ctx
, ctx
->Color
.BlendColor
);
1905 r700
->CB_CLEAR_RED_R6XX
.f32All
= 1.0; //r6xx only
1906 r700
->CB_CLEAR_GREEN_R6XX
.f32All
= 0.0; //r6xx only
1907 r700
->CB_CLEAR_BLUE_R6XX
.f32All
= 1.0; //r6xx only
1908 r700
->CB_CLEAR_ALPHA_R6XX
.f32All
= 1.0; //r6xx only
1909 r700
->CB_FOG_RED_R6XX
.u32All
= 0; //r6xx only
1910 r700
->CB_FOG_GREEN_R6XX
.u32All
= 0; //r6xx only
1911 r700
->CB_FOG_BLUE_R6XX
.u32All
= 0; //r6xx only
1913 /* Disable color compares */
1914 SETfield(r700
->CB_CLRCMP_CONTROL
.u32All
, CLRCMP_DRAW_ALWAYS
,
1915 CLRCMP_FCN_SRC_shift
, CLRCMP_FCN_SRC_mask
);
1916 SETfield(r700
->CB_CLRCMP_CONTROL
.u32All
, CLRCMP_DRAW_ALWAYS
,
1917 CLRCMP_FCN_DST_shift
, CLRCMP_FCN_DST_mask
);
1918 SETfield(r700
->CB_CLRCMP_CONTROL
.u32All
, CLRCMP_SEL_SRC
,
1919 CLRCMP_FCN_SEL_shift
, CLRCMP_FCN_SEL_mask
);
1921 /* Zero out source */
1922 r700
->CB_CLRCMP_SRC
.u32All
= 0x00000000;
1924 /* Put a compare color in for error checking */
1925 r700
->CB_CLRCMP_DST
.u32All
= 0x000000FF;
1927 /* Set up color compare mask */
1928 r700
->CB_CLRCMP_MSK
.u32All
= 0xFFFFFFFF;
1930 context
->radeon
.hw
.all_dirty
= GL_TRUE
;
1934 void r700InitStateFuncs(struct dd_function_table
*functions
) //-----------------
1936 functions
->UpdateState
= r700InvalidateState
;
1937 functions
->AlphaFunc
= r700AlphaFunc
;
1938 functions
->BlendColor
= r700BlendColor
;
1939 functions
->BlendEquationSeparate
= r700BlendEquationSeparate
;
1940 functions
->BlendFuncSeparate
= r700BlendFuncSeparate
;
1941 functions
->Enable
= r700Enable
;
1942 functions
->ColorMask
= r700ColorMask
;
1943 functions
->DepthFunc
= r700DepthFunc
;
1944 functions
->DepthMask
= r700DepthMask
;
1945 functions
->CullFace
= r700CullFace
;
1946 functions
->Fogfv
= r700Fogfv
;
1947 functions
->FrontFace
= r700FrontFace
;
1948 functions
->ShadeModel
= r700ShadeModel
;
1949 functions
->LogicOpcode
= r700LogicOpcode
;
1951 /* ARB_point_parameters */
1952 functions
->PointParameterfv
= r700PointParameter
;
1954 /* Stencil related */
1955 functions
->StencilFuncSeparate
= r700StencilFuncSeparate
;
1956 functions
->StencilMaskSeparate
= r700StencilMaskSeparate
;
1957 functions
->StencilOpSeparate
= r700StencilOpSeparate
;
1959 /* Viewport related */
1960 functions
->Viewport
= r700Viewport
;
1961 functions
->DepthRange
= r700DepthRange
;
1962 functions
->PointSize
= r700PointSize
;
1963 functions
->LineWidth
= r700LineWidth
;
1964 functions
->LineStipple
= r700LineStipple
;
1966 functions
->PolygonOffset
= r700PolygonOffset
;
1967 functions
->PolygonMode
= r700PolygonMode
;
1969 functions
->RenderMode
= r700RenderMode
;
1971 functions
->ClipPlane
= r700ClipPlane
;
1973 functions
->Scissor
= radeonScissor
;
1975 functions
->DrawBuffer
= radeonDrawBuffer
;
1976 functions
->ReadBuffer
= radeonReadBuffer
;