2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
34 #include "main/simple_list.h"
37 #include "tnl/t_pipeline.h"
38 #include "tnl/t_vp_build.h"
39 #include "swrast/swrast.h"
40 #include "swrast_setup/swrast_setup.h"
41 #include "main/api_arrayelt.h"
42 #include "main/state.h"
43 #include "main/framebuffer.h"
45 #include "shader/prog_parameter.h"
46 #include "shader/prog_statevars.h"
48 #include "main/texformat.h"
50 #include "r600_context.h"
52 #include "r700_state.h"
54 #include "r700_fragprog.h"
55 #include "r700_vertprog.h"
58 void r700SetDefaultStates(context_t
*context
) //--------------------
63 void r700UpdateShaders (GLcontext
* ctx
) //----------------------------------
65 context_t
*context
= R700_CONTEXT(ctx
);
67 GLvector4f dummy_attrib
[_TNL_ATTRIB_MAX
];
68 GLvector4f
*temp_attrib
[_TNL_ATTRIB_MAX
];
70 struct r700_vertex_program
*vp
;
73 if (context
->radeon
.NewGLState
)
75 context
->radeon
.NewGLState
= 0;
77 for (i
= _TNL_FIRST_MAT
; i
<= _TNL_LAST_MAT
; i
++)
79 /* mat states from state var not array for sw */
80 dummy_attrib
[i
].stride
= 0;
82 temp_attrib
[i
] = TNL_CONTEXT(ctx
)->vb
.AttribPtr
[i
];
83 TNL_CONTEXT(ctx
)->vb
.AttribPtr
[i
] = &(dummy_attrib
[i
]);
86 _tnl_UpdateFixedFunctionProgram(ctx
);
88 for (i
= _TNL_FIRST_MAT
; i
<= _TNL_LAST_MAT
; i
++)
90 TNL_CONTEXT(ctx
)->vb
.AttribPtr
[i
] = temp_attrib
[i
];
93 r700SelectVertexShader(ctx
);
94 vp
= (struct r700_vertex_program
*)ctx
->VertexProgram
._Current
;
96 if (vp
->translated
== GL_FALSE
)
99 //fprintf(stderr, "Failing back to sw-tcl\n");
100 //hw_tcl_on = future_hw_tcl_on = 0;
101 //r300ResetHwState(rmesa);
103 r700UpdateStateParameters(ctx
, _NEW_PROGRAM
);
108 r700UpdateStateParameters(ctx
, _NEW_PROGRAM
);
112 * To correctly position primitives:
114 void r700UpdateViewportOffset(GLcontext
* ctx
) //------------------
117 //radeonUpdateScissor(ctx);
123 * Tell the card where to render (offset, pitch).
124 * Effected by glDrawBuffer, etc
126 void r700UpdateDrawBuffer(GLcontext
* ctx
) /* TODO */ //---------------------
128 #if 0 /* to be enabled */
129 context_t
*context
= R700_CONTEXT(ctx
);
131 switch (ctx
->DrawBuffer
->_ColorDrawBufferIndexes
[0])
133 case BUFFER_FRONT_LEFT
:
134 context
->target
.rt
= context
->screen
->frontBuffer
;
136 case BUFFER_BACK_LEFT
:
137 context
->target
.rt
= context
->screen
->backBuffer
;
140 memset (&context
->target
.rt
, sizeof(context
->target
.rt
), 0);
142 #endif /* to be enabled */
145 static void r700FetchStateParameter(GLcontext
* ctx
,
146 const gl_state_index state
[STATE_LENGTH
],
149 context_t
*context
= R700_CONTEXT(ctx
);
154 void r700UpdateStateParameters(GLcontext
* ctx
, GLuint new_state
) //--------------------
156 struct r700_fragment_program
*fp
;
157 struct gl_program_parameter_list
*paramList
;
160 if (!(new_state
& (_NEW_BUFFERS
| _NEW_PROGRAM
)))
163 fp
= (struct r700_fragment_program
*)ctx
->FragmentProgram
._Current
;
169 paramList
= fp
->mesa_program
.Base
.Parameters
;
176 for (i
= 0; i
< paramList
->NumParameters
; i
++)
178 if (paramList
->Parameters
[i
].Type
== PROGRAM_STATE_VAR
)
180 r700FetchStateParameter(ctx
,
181 paramList
->Parameters
[i
].
183 paramList
->ParameterValues
[i
]);
189 * Called by Mesa after an internal state update.
191 static void r700InvalidateState(GLcontext
* ctx
, GLuint new_state
) //-------------------
193 context_t
*context
= R700_CONTEXT(ctx
);
195 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
197 _swrast_InvalidateState(ctx
, new_state
);
198 _swsetup_InvalidateState(ctx
, new_state
);
199 _vbo_InvalidateState(ctx
, new_state
);
200 _tnl_InvalidateState(ctx
, new_state
);
201 _ae_invalidate_state(ctx
, new_state
);
203 if (new_state
& (_NEW_BUFFERS
| _NEW_COLOR
| _NEW_PIXEL
))
205 _mesa_update_framebuffer(ctx
);
206 /* this updates the DrawBuffer's Width/Height if it's a FBO */
207 _mesa_update_draw_buffer_bounds(ctx
);
209 r700UpdateDrawBuffer(ctx
);
212 r700UpdateStateParameters(ctx
, new_state
);
214 if(GL_TRUE
== r700
->bEnablePerspective
)
216 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
217 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_XY_FMT_bit
);
218 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_Z_FMT_bit
);
220 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_W0_FMT_bit
);
222 SETbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, PERSP_GRADIENT_ENA_bit
);
223 CLEARbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, LINEAR_GRADIENT_ENA_bit
);
227 /* For orthogonal case. */
228 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_XY_FMT_bit
);
229 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_Z_FMT_bit
);
231 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_W0_FMT_bit
);
233 CLEARbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, PERSP_GRADIENT_ENA_bit
);
234 SETbit(r700
->SPI_PS_IN_CONTROL_0
.u32All
, LINEAR_GRADIENT_ENA_bit
);
237 context
->radeon
.NewGLState
|= new_state
;
240 static void r700SetDepthState(GLcontext
* ctx
)
242 context_t
*context
= R700_CONTEXT(ctx
);
244 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
248 SETbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_ENABLE_bit
);
251 SETbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_WRITE_ENABLE_bit
);
255 CLEARbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_WRITE_ENABLE_bit
);
258 switch (ctx
->Depth
.Func
)
261 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_NEVER
,
262 ZFUNC_shift
, ZFUNC_mask
);
265 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_LESS
,
266 ZFUNC_shift
, ZFUNC_mask
);
269 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_EQUAL
,
270 ZFUNC_shift
, ZFUNC_mask
);
273 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_LEQUAL
,
274 ZFUNC_shift
, ZFUNC_mask
);
277 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_GREATER
,
278 ZFUNC_shift
, ZFUNC_mask
);
281 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_NOTEQUAL
,
282 ZFUNC_shift
, ZFUNC_mask
);
285 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_GEQUAL
,
286 ZFUNC_shift
, ZFUNC_mask
);
289 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_ALWAYS
,
290 ZFUNC_shift
, ZFUNC_mask
);
293 SETfield(r700
->DB_DEPTH_CONTROL
.u32All
, FRAG_ALWAYS
,
294 ZFUNC_shift
, ZFUNC_mask
);
300 CLEARbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_ENABLE_bit
);
301 CLEARbit(r700
->DB_DEPTH_CONTROL
.u32All
, Z_WRITE_ENABLE_bit
);
305 static void r700AlphaFunc(GLcontext
* ctx
, GLenum func
, GLfloat ref
) //---------------
310 static void r700BlendColor(GLcontext
* ctx
, const GLfloat cf
[4]) //----------------
314 static void r700BlendEquationSeparate(GLcontext
* ctx
,
315 GLenum modeRGB
, GLenum modeA
) //-----------------
319 static void r700BlendFuncSeparate(GLcontext
* ctx
,
320 GLenum sfactorRGB
, GLenum dfactorRGB
,
321 GLenum sfactorA
, GLenum dfactorA
) //------------------------
325 static void r700UpdateCulling(GLcontext
* ctx
)
327 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&R700_CONTEXT(ctx
)->hw
);
329 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
);
330 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
331 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
333 if (ctx
->Polygon
.CullFlag
)
335 switch (ctx
->Polygon
.CullFaceMode
)
338 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
339 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
342 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
343 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
345 case GL_FRONT_AND_BACK
:
346 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
347 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
350 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_FRONT_bit
);
351 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, CULL_BACK_bit
);
356 switch (ctx
->Polygon
.FrontFace
)
359 SETbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
);
362 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
);
365 CLEARbit(r700
->PA_SU_SC_MODE_CNTL
.u32All
, FACE_bit
); /* default: ccw */
370 static void r700Enable(GLcontext
* ctx
, GLenum cap
, GLboolean state
) //------------------
372 context_t
*context
= R700_CONTEXT(ctx
);
384 //r700SetAlphaState(ctx);
386 case GL_COLOR_LOGIC_OP
:
387 //r700SetLogicOpState(ctx);
388 /* fall-through, because logic op overrides blending */
390 //r700SetBlendState(ctx);
398 //r700SetClipPlaneState(ctx, cap, state);
401 r700SetDepthState(ctx
);
403 case GL_STENCIL_TEST
:
404 //r700SetStencilState(ctx, state);
407 r700UpdateCulling(ctx
);
409 case GL_POLYGON_OFFSET_POINT
:
410 case GL_POLYGON_OFFSET_LINE
:
411 case GL_POLYGON_OFFSET_FILL
:
412 //r700SetPolygonOffsetState(ctx, state);
414 case GL_SCISSOR_TEST
:
415 radeon_firevertices(&context
->radeon
);
416 context
->radeon
.state
.scissor
.enabled
= state
;
417 radeonUpdateScissor(ctx
);
426 * Handle glColorMask()
428 static void r700ColorMask(GLcontext
* ctx
,
429 GLboolean r
, GLboolean g
, GLboolean b
, GLboolean a
) //------------------
431 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&R700_CONTEXT(ctx
)->hw
);
432 unsigned int mask
= ((r
? 1 : 0) |
437 if (mask
!= r700
->CB_SHADER_MASK
.u32All
)
438 SETfield(r700
->CB_SHADER_MASK
.u32All
, mask
, OUTPUT0_ENABLE_shift
, OUTPUT0_ENABLE_mask
);
442 * Change the depth testing function.
444 * \note Mesa already filters redundant calls to this function.
446 static void r700DepthFunc(GLcontext
* ctx
, GLenum func
) //--------------------
448 r700SetDepthState(ctx
);
452 * Enable/Disable depth writing.
454 * \note Mesa already filters redundant calls to this function.
456 static void r700DepthMask(GLcontext
* ctx
, GLboolean mask
) //------------------
458 r700SetDepthState(ctx
);
462 * Change the culling mode.
464 * \note Mesa already filters redundant calls to this function.
466 static void r700CullFace(GLcontext
* ctx
, GLenum mode
) //-----------------
468 r700UpdateCulling(ctx
);
471 /* =============================================================
474 static void r700Fogfv(GLcontext
* ctx
, GLenum pname
, const GLfloat
* param
) //--------------
479 * Change the polygon orientation.
481 * \note Mesa already filters redundant calls to this function.
483 static void r700FrontFace(GLcontext
* ctx
, GLenum mode
) //------------------
485 r700UpdateCulling(ctx
);
488 static void r700ShadeModel(GLcontext
* ctx
, GLenum mode
) //--------------------
490 context_t
*context
= R700_CONTEXT(ctx
);
491 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
493 /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */
496 SETbit(r700
->SPI_INTERP_CONTROL_0
.u32All
, FLAT_SHADE_ENA_bit
);
499 CLEARbit(r700
->SPI_INTERP_CONTROL_0
.u32All
, FLAT_SHADE_ENA_bit
);
506 static void r700PointParameter(GLcontext
* ctx
, GLenum pname
, const GLfloat
* param
) //---------------
510 static void r700StencilFuncSeparate(GLcontext
* ctx
, GLenum face
,
511 GLenum func
, GLint ref
, GLuint mask
) //---------------------
516 static void r700StencilMaskSeparate(GLcontext
* ctx
, GLenum face
, GLuint mask
) //--------------
520 static void r700StencilOpSeparate(GLcontext
* ctx
, GLenum face
,
521 GLenum fail
, GLenum zfail
, GLenum zpass
) //--------------------
525 static void r700UpdateWindow(GLcontext
* ctx
, int id
) //--------------------
528 context_t
*context
= R700_CONTEXT(ctx
);
529 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
530 __DRIdrawablePrivate
*dPriv
= radeon_get_drawable(&context
->radeon
);
531 GLfloat xoffset
= dPriv
? (GLfloat
) dPriv
->x
: 0;
532 GLfloat yoffset
= dPriv
? (GLfloat
) dPriv
->y
+ dPriv
->h
: 0;
533 const GLfloat
*v
= ctx
->Viewport
._WindowMap
.m
;
534 const GLfloat depthScale
= 1.0F
/ ctx
->DrawBuffer
->_DepthMaxF
;
535 const GLboolean render_to_fbo
= (ctx
->DrawBuffer
->Name
!= 0);
536 GLfloat y_scale
, y_bias
;
546 GLfloat sx
= v
[MAT_SX
];
547 GLfloat tx
= v
[MAT_TX
] + xoffset
;
548 GLfloat sy
= v
[MAT_SY
] * y_scale
;
549 GLfloat ty
= (v
[MAT_TY
] * y_scale
) + y_bias
;
550 GLfloat sz
= v
[MAT_SZ
] * depthScale
;
551 GLfloat tz
= v
[MAT_TZ
] * depthScale
;
553 /* TODO : Need DMA flush as well. */
555 r700
->viewport
[id
].PA_CL_VPORT_XSCALE
.f32All
= sx
;
556 r700
->viewport
[id
].PA_CL_VPORT_XOFFSET
.f32All
= tx
;
558 r700
->viewport
[id
].PA_CL_VPORT_YSCALE
.f32All
= sy
;
559 r700
->viewport
[id
].PA_CL_VPORT_YOFFSET
.f32All
= ty
;
561 r700
->viewport
[id
].PA_CL_VPORT_ZSCALE
.f32All
= sz
;
562 r700
->viewport
[id
].PA_CL_VPORT_ZOFFSET
.f32All
= tz
;
564 r700
->viewport
[id
].enabled
= GL_TRUE
;
566 r700SetScissor(context
);
570 static void r700Viewport(GLcontext
* ctx
,
574 GLsizei height
) //--------------------
576 r700UpdateWindow(ctx
, 0);
578 radeon_viewport(ctx
, x
, y
, width
, height
);
581 static void r700DepthRange(GLcontext
* ctx
, GLclampd nearval
, GLclampd farval
) //-------------
583 r700UpdateWindow(ctx
, 0);
586 static void r700PointSize(GLcontext
* ctx
, GLfloat size
) //-------------------
590 static void r700LineWidth(GLcontext
* ctx
, GLfloat widthf
) //---------------
594 static void r700PolygonOffset(GLcontext
* ctx
, GLfloat factor
, GLfloat units
) //--------------
599 static void r700PolygonMode(GLcontext
* ctx
, GLenum face
, GLenum mode
) //------------------
603 static void r700RenderMode(GLcontext
* ctx
, GLenum mode
) //---------------------
607 static void r700ClipPlane( GLcontext
*ctx
, GLenum plane
, const GLfloat
*eq
) //-----------------
611 void r700SetScissor(context_t
*context
) //---------------
613 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
614 unsigned x1
, y1
, x2
, y2
;
616 struct radeon_renderbuffer
*rrb
;
618 rrb
= radeon_get_colorbuffer(&context
->radeon
);
619 if (!rrb
|| !rrb
->bo
) {
622 if (context
->radeon
.state
.scissor
.enabled
) {
623 x1
= context
->radeon
.state
.scissor
.rect
.x1
;
624 y1
= context
->radeon
.state
.scissor
.rect
.y1
;
625 x2
= context
->radeon
.state
.scissor
.rect
.x2
- 1;
626 y2
= context
->radeon
.state
.scissor
.rect
.y2
- 1;
630 x2
= rrb
->dPriv
->x
+ rrb
->dPriv
->w
;
631 y2
= rrb
->dPriv
->y
+ rrb
->dPriv
->h
;
635 SETbit(r700
->PA_SC_WINDOW_SCISSOR_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
636 SETfield(r700
->PA_SC_WINDOW_SCISSOR_TL
.u32All
, x1
,
637 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift
, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask
);
638 SETfield(r700
->PA_SC_WINDOW_SCISSOR_TL
.u32All
, y1
,
639 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift
, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask
);
641 SETfield(r700
->PA_SC_WINDOW_SCISSOR_BR
.u32All
, x2
,
642 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift
, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask
);
643 SETfield(r700
->PA_SC_WINDOW_SCISSOR_BR
.u32All
, y2
,
644 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift
, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask
);
647 SETfield(r700
->PA_SC_CLIPRECT_0_TL
.u32All
, x1
,
648 PA_SC_CLIPRECT_0_TL__TL_X_shift
, PA_SC_CLIPRECT_0_TL__TL_X_mask
);
649 SETfield(r700
->PA_SC_CLIPRECT_0_TL
.u32All
, y1
,
650 PA_SC_CLIPRECT_0_TL__TL_Y_shift
, PA_SC_CLIPRECT_0_TL__TL_Y_mask
);
651 SETfield(r700
->PA_SC_CLIPRECT_0_BR
.u32All
, x2
,
652 PA_SC_CLIPRECT_0_BR__BR_X_shift
, PA_SC_CLIPRECT_0_BR__BR_X_mask
);
653 SETfield(r700
->PA_SC_CLIPRECT_0_BR
.u32All
, y2
,
654 PA_SC_CLIPRECT_0_BR__BR_Y_shift
, PA_SC_CLIPRECT_0_BR__BR_Y_mask
);
656 r700
->PA_SC_CLIPRECT_1_TL
.u32All
= r700
->PA_SC_CLIPRECT_0_TL
.u32All
;
657 r700
->PA_SC_CLIPRECT_1_BR
.u32All
= r700
->PA_SC_CLIPRECT_0_BR
.u32All
;
658 r700
->PA_SC_CLIPRECT_2_TL
.u32All
= r700
->PA_SC_CLIPRECT_0_TL
.u32All
;
659 r700
->PA_SC_CLIPRECT_2_BR
.u32All
= r700
->PA_SC_CLIPRECT_0_BR
.u32All
;
660 r700
->PA_SC_CLIPRECT_3_TL
.u32All
= r700
->PA_SC_CLIPRECT_0_TL
.u32All
;
661 r700
->PA_SC_CLIPRECT_3_BR
.u32All
= r700
->PA_SC_CLIPRECT_0_BR
.u32All
;
663 /* more....2d clip */
664 SETbit(r700
->PA_SC_GENERIC_SCISSOR_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
665 SETfield(r700
->PA_SC_GENERIC_SCISSOR_TL
.u32All
, x1
,
666 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift
, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask
);
667 SETfield(r700
->PA_SC_GENERIC_SCISSOR_TL
.u32All
, y1
,
668 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift
, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask
);
669 SETfield(r700
->PA_SC_GENERIC_SCISSOR_BR
.u32All
, x2
,
670 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift
, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask
);
671 SETfield(r700
->PA_SC_GENERIC_SCISSOR_BR
.u32All
, y2
,
672 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift
, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask
);
674 SETbit(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_TL
.u32All
, WINDOW_OFFSET_DISABLE_bit
);
675 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_TL
.u32All
, x1
,
676 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift
, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask
);
677 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_TL
.u32All
, y1
,
678 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift
, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask
);
679 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_BR
.u32All
, x2
,
680 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift
, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask
);
681 SETfield(r700
->viewport
[id
].PA_SC_VPORT_SCISSOR_0_BR
.u32All
, y2
,
682 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift
, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask
);
684 r700
->viewport
[id
].PA_SC_VPORT_ZMIN_0
.u32All
= 0;
685 r700
->viewport
[id
].PA_SC_VPORT_ZMAX_0
.u32All
= 0x3F800000;
686 r700
->viewport
[id
].enabled
= GL_TRUE
;
689 void r700SetRenderTarget(context_t
*context
, int id
)
691 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
693 struct radeon_renderbuffer
*rrb
;
694 unsigned int nPitchInPixel
;
696 /* screen/window/view */
697 SETfield(r700
->CB_TARGET_MASK
.u32All
, 0xF, (4 * id
), TARGET0_ENABLE_mask
);
699 rrb
= radeon_get_colorbuffer(&context
->radeon
);
700 if (!rrb
|| !rrb
->bo
) {
701 fprintf(stderr
, "no rrb\n");
706 r700
->render_target
[id
].CB_COLOR0_BASE
.u32All
= context
->radeon
.state
.color
.draw_offset
;
708 nPitchInPixel
= rrb
->pitch
/rrb
->cpp
;
709 SETfield(r700
->render_target
[id
].CB_COLOR0_SIZE
.u32All
, (nPitchInPixel
/8)-1,
710 PITCH_TILE_MAX_shift
, PITCH_TILE_MAX_mask
);
711 SETfield(r700
->render_target
[id
].CB_COLOR0_SIZE
.u32All
, ( (nPitchInPixel
* context
->radeon
.radeonScreen
->driScreen
->fbHeight
)/64 )-1,
712 SLICE_TILE_MAX_shift
, SLICE_TILE_MAX_mask
);
713 r700
->render_target
[id
].CB_COLOR0_BASE
.u32All
= 0;
714 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, ENDIAN_NONE
, ENDIAN_shift
, ENDIAN_mask
);
715 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, ARRAY_LINEAR_GENERAL
,
716 CB_COLOR0_INFO__ARRAY_MODE_shift
, CB_COLOR0_INFO__ARRAY_MODE_mask
);
719 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, COLOR_8_8_8_8
,
720 CB_COLOR0_INFO__FORMAT_shift
, CB_COLOR0_INFO__FORMAT_mask
);
721 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, SWAP_ALT
, COMP_SWAP_shift
, COMP_SWAP_mask
);
725 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, COLOR_5_6_5
,
726 CB_COLOR0_INFO__FORMAT_shift
, CB_COLOR0_INFO__FORMAT_mask
);
727 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, SWAP_ALT_REV
,
728 COMP_SWAP_shift
, COMP_SWAP_mask
);
730 SETbit(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, SOURCE_FORMAT_bit
);
731 SETbit(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, BLEND_CLAMP_bit
);
732 SETfield(r700
->render_target
[id
].CB_COLOR0_INFO
.u32All
, NUMBER_UNORM
, NUMBER_TYPE_shift
, NUMBER_TYPE_mask
);
734 CLEARfield(r700
->render_target
[id
].CB_BLEND0_CONTROL
.u32All
, COLOR_SRCBLEND_mask
); /* no dst blend */
735 CLEARfield(r700
->render_target
[id
].CB_BLEND0_CONTROL
.u32All
, ALPHA_SRCBLEND_mask
); /* no dst blend */
737 r700
->render_target
[id
].enabled
= GL_TRUE
;
740 void r700SetDepthTarget(context_t
*context
)
742 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
744 struct radeon_renderbuffer
*rrb
;
745 unsigned int nPitchInPixel
;
748 r700
->DB_DEPTH_SIZE
.u32All
= 0;
749 r700
->DB_DEPTH_BASE
.u32All
= 0;
750 r700
->DB_DEPTH_INFO
.u32All
= 0;
752 r700
->DB_DEPTH_CLEAR
.u32All
= 0x3F800000;
753 r700
->DB_DEPTH_VIEW
.u32All
= 0;
754 r700
->DB_RENDER_CONTROL
.u32All
= 0;
755 r700
->DB_RENDER_OVERRIDE
.u32All
= 0;
756 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
)
757 SETbit(r700
->DB_RENDER_OVERRIDE
.u32All
, FORCE_SHADER_Z_ORDER_bit
);
758 SETfield(r700
->DB_RENDER_OVERRIDE
.u32All
, FORCE_DISABLE
, FORCE_HIZ_ENABLE_shift
, FORCE_HIZ_ENABLE_mask
);
759 SETfield(r700
->DB_RENDER_OVERRIDE
.u32All
, FORCE_DISABLE
, FORCE_HIS_ENABLE0_shift
, FORCE_HIS_ENABLE0_mask
);
760 SETfield(r700
->DB_RENDER_OVERRIDE
.u32All
, FORCE_DISABLE
, FORCE_HIS_ENABLE1_shift
, FORCE_HIS_ENABLE1_mask
);
762 r700
->DB_ALPHA_TO_MASK
.u32All
= 0;
763 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET0_shift
, ALPHA_TO_MASK_OFFSET0_mask
);
764 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET1_shift
, ALPHA_TO_MASK_OFFSET1_mask
);
765 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET2_shift
, ALPHA_TO_MASK_OFFSET2_mask
);
766 SETfield(r700
->DB_ALPHA_TO_MASK
.u32All
, 2, ALPHA_TO_MASK_OFFSET3_shift
, ALPHA_TO_MASK_OFFSET3_mask
);
768 rrb
= radeon_get_depthbuffer(&context
->radeon
);
772 nPitchInPixel
= rrb
->pitch
/rrb
->cpp
;
774 SETfield(r700
->DB_DEPTH_SIZE
.u32All
, (nPitchInPixel
/8)-1,
775 PITCH_TILE_MAX_shift
, PITCH_TILE_MAX_mask
);
776 SETfield(r700
->DB_DEPTH_SIZE
.u32All
, ( (nPitchInPixel
* context
->radeon
.radeonScreen
->driScreen
->fbHeight
)/64 )-1,
777 SLICE_TILE_MAX_shift
, SLICE_TILE_MAX_mask
); /* size in pixel / 64 - 1 */
781 switch (GL_CONTEXT(context
)->Visual
.depthBits
)
785 SETfield(r700
->DB_DEPTH_INFO
.u32All
, DEPTH_8_24
,
786 DB_DEPTH_INFO__FORMAT_shift
, DB_DEPTH_INFO__FORMAT_mask
);
789 fprintf(stderr
, "Error: Unsupported depth %d... exiting\n",
790 GL_CONTEXT(context
)->Visual
.depthBits
);
796 SETfield(r700
->DB_DEPTH_INFO
.u32All
, DEPTH_16
,
797 DB_DEPTH_INFO__FORMAT_shift
, DB_DEPTH_INFO__FORMAT_mask
);
799 SETfield(r700
->DB_DEPTH_INFO
.u32All
, ARRAY_2D_TILED_THIN1
,
800 DB_DEPTH_INFO__ARRAY_MODE_shift
, DB_DEPTH_INFO__ARRAY_MODE_mask
);
801 /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */
804 static void r700InitSQConfig(GLcontext
* ctx
)
806 context_t
*context
= R700_CONTEXT(ctx
);
807 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
821 int num_ps_stack_entries
;
822 int num_vs_stack_entries
;
823 int num_gs_stack_entries
;
824 int num_es_stack_entries
;
831 switch (context
->radeon
.radeonScreen
->chip_family
) {
832 case CHIP_FAMILY_R600
:
838 num_ps_threads
= 136;
842 num_ps_stack_entries
= 128;
843 num_vs_stack_entries
= 128;
844 num_gs_stack_entries
= 0;
845 num_es_stack_entries
= 0;
847 case CHIP_FAMILY_RV630
:
848 case CHIP_FAMILY_RV635
:
854 num_ps_threads
= 144;
858 num_ps_stack_entries
= 40;
859 num_vs_stack_entries
= 40;
860 num_gs_stack_entries
= 32;
861 num_es_stack_entries
= 16;
863 case CHIP_FAMILY_RV610
:
864 case CHIP_FAMILY_RV620
:
865 case CHIP_FAMILY_RS780
:
872 num_ps_threads
= 136;
876 num_ps_stack_entries
= 40;
877 num_vs_stack_entries
= 40;
878 num_gs_stack_entries
= 32;
879 num_es_stack_entries
= 16;
881 case CHIP_FAMILY_RV670
:
887 num_ps_threads
= 136;
891 num_ps_stack_entries
= 40;
892 num_vs_stack_entries
= 40;
893 num_gs_stack_entries
= 32;
894 num_es_stack_entries
= 16;
896 case CHIP_FAMILY_RV770
:
902 num_ps_threads
= 188;
906 num_ps_stack_entries
= 256;
907 num_vs_stack_entries
= 256;
908 num_gs_stack_entries
= 0;
909 num_es_stack_entries
= 0;
911 case CHIP_FAMILY_RV730
:
912 case CHIP_FAMILY_RV740
:
918 num_ps_threads
= 188;
922 num_ps_stack_entries
= 128;
923 num_vs_stack_entries
= 128;
924 num_gs_stack_entries
= 0;
925 num_es_stack_entries
= 0;
927 case CHIP_FAMILY_RV710
:
933 num_ps_threads
= 144;
937 num_ps_stack_entries
= 128;
938 num_vs_stack_entries
= 128;
939 num_gs_stack_entries
= 0;
940 num_es_stack_entries
= 0;
944 r700
->sq_config
.SQ_CONFIG
.u32All
= 0;
945 if ((context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV610
) ||
946 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV620
) ||
947 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RS780
) ||
948 (context
->radeon
.radeonScreen
->chip_family
== CHIP_FAMILY_RV710
))
949 CLEARbit(r700
->sq_config
.SQ_CONFIG
.u32All
, VC_ENABLE_bit
);
951 SETbit(r700
->sq_config
.SQ_CONFIG
.u32All
, VC_ENABLE_bit
);
952 SETbit(r700
->sq_config
.SQ_CONFIG
.u32All
, DX9_CONSTS_bit
);
953 SETbit(r700
->sq_config
.SQ_CONFIG
.u32All
, ALU_INST_PREFER_VECTOR_bit
);
954 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, ps_prio
, PS_PRIO_shift
, PS_PRIO_mask
);
955 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, ps_prio
, VS_PRIO_shift
, VS_PRIO_mask
);
956 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, ps_prio
, GS_PRIO_shift
, GS_PRIO_mask
);
957 SETfield(r700
->sq_config
.SQ_CONFIG
.u32All
, ps_prio
, ES_PRIO_shift
, ES_PRIO_mask
);
959 r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
= 0;
960 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
, num_ps_gprs
, NUM_PS_GPRS_shift
, NUM_PS_GPRS_mask
);
961 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
, num_vs_gprs
, NUM_VS_GPRS_shift
, NUM_VS_GPRS_mask
);
962 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_1
.u32All
, num_temp_gprs
,
963 NUM_CLAUSE_TEMP_GPRS_shift
, NUM_CLAUSE_TEMP_GPRS_mask
);
965 r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_2
.u32All
= 0;
966 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_2
.u32All
, num_gs_gprs
, NUM_GS_GPRS_shift
, NUM_GS_GPRS_mask
);
967 SETfield(r700
->sq_config
.SQ_GPR_RESOURCE_MGMT_2
.u32All
, num_es_gprs
, NUM_ES_GPRS_shift
, NUM_ES_GPRS_mask
);
969 r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
= 0;
970 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_ps_threads
,
971 NUM_PS_THREADS_shift
, NUM_PS_THREADS_mask
);
972 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_vs_threads
,
973 NUM_VS_THREADS_shift
, NUM_VS_THREADS_mask
);
974 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_gs_threads
,
975 NUM_GS_THREADS_shift
, NUM_GS_THREADS_mask
);
976 SETfield(r700
->sq_config
.SQ_THREAD_RESOURCE_MGMT
.u32All
, num_es_threads
,
977 NUM_ES_THREADS_shift
, NUM_ES_THREADS_mask
);
979 r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_1
.u32All
= 0;
980 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_1
.u32All
, num_ps_stack_entries
,
981 NUM_PS_STACK_ENTRIES_shift
, NUM_PS_STACK_ENTRIES_mask
);
982 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_1
.u32All
, num_vs_stack_entries
,
983 NUM_VS_STACK_ENTRIES_shift
, NUM_VS_STACK_ENTRIES_mask
);
985 r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_2
.u32All
= 0;
986 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_2
.u32All
, num_gs_stack_entries
,
987 NUM_GS_STACK_ENTRIES_shift
, NUM_GS_STACK_ENTRIES_mask
);
988 SETfield(r700
->sq_config
.SQ_STACK_RESOURCE_MGMT_2
.u32All
, num_es_stack_entries
,
989 NUM_ES_STACK_ENTRIES_shift
, NUM_ES_STACK_ENTRIES_mask
);
994 * Calculate initial hardware state and register state functions.
995 * Assumes that the command buffer and state atoms have been
996 * initialized already.
998 void r700InitState(GLcontext
* ctx
) //-------------------
1000 context_t
*context
= R700_CONTEXT(ctx
);
1002 R700_CHIP_CONTEXT
*r700
= (R700_CHIP_CONTEXT
*)(&context
->hw
);
1004 r700
->TA_CNTL_AUX
.u32All
= 0;
1005 SETfield(r700
->TA_CNTL_AUX
.u32All
, 28, TD_FIFO_CREDIT_shift
, TD_FIFO_CREDIT_mask
);
1006 r700
->VC_ENHANCE
.u32All
= 0;
1007 r700
->DB_WATERMARKS
.u32All
= 0;
1008 SETfield(r700
->DB_WATERMARKS
.u32All
, 4, DEPTH_FREE_shift
, DEPTH_FREE_mask
);
1009 SETfield(r700
->DB_WATERMARKS
.u32All
, 16, DEPTH_FLUSH_shift
, DEPTH_FLUSH_mask
);
1010 SETfield(r700
->DB_WATERMARKS
.u32All
, 0, FORCE_SUMMARIZE_shift
, FORCE_SUMMARIZE_mask
);
1011 SETfield(r700
->DB_WATERMARKS
.u32All
, 4, DEPTH_PENDING_FREE_shift
, DEPTH_PENDING_FREE_mask
);
1012 r700
->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
.u32All
= 0;
1013 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
) {
1014 SETfield(r700
->TA_CNTL_AUX
.u32All
, 3, GRADIENT_CREDIT_shift
, GRADIENT_CREDIT_mask
);
1015 r700
->DB_DEBUG
.u32All
= 0x82000000;
1016 SETfield(r700
->DB_WATERMARKS
.u32All
, 16, DEPTH_CACHELINE_FREE_shift
, DEPTH_CACHELINE_FREE_mask
);
1018 SETfield(r700
->TA_CNTL_AUX
.u32All
, 2, GRADIENT_CREDIT_shift
, GRADIENT_CREDIT_mask
);
1019 SETfield(r700
->DB_WATERMARKS
.u32All
, 4, DEPTH_CACHELINE_FREE_shift
, DEPTH_CACHELINE_FREE_mask
);
1020 SETbit(r700
->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ
.u32All
, VS_PC_LIMIT_ENABLE_bit
);
1023 /* Turn off vgt reuse */
1024 r700
->VGT_REUSE_OFF
.u32All
= 0;
1025 SETbit(r700
->VGT_REUSE_OFF
.u32All
, REUSE_OFF_bit
);
1027 /* Specify offsetting and clamp values for vertices */
1028 r700
->VGT_MAX_VTX_INDX
.u32All
= 0xFFFFFF;
1029 r700
->VGT_MIN_VTX_INDX
.u32All
= 0;
1030 r700
->VGT_INDX_OFFSET
.u32All
= 0;
1032 /* Specify the number of instances */
1033 r700
->VGT_DMA_NUM_INSTANCES
.u32All
= 1;
1035 /* not alpha blend */
1036 CLEARfield(r700
->SX_ALPHA_TEST_CONTROL
.u32All
, ALPHA_FUNC_mask
);
1037 CLEARbit(r700
->SX_ALPHA_TEST_CONTROL
.u32All
, ALPHA_TEST_ENABLE_bit
);
1039 /* default shader connections. */
1040 r700
->SPI_VS_OUT_ID_0
.u32All
= 0x03020100;
1041 r700
->SPI_VS_OUT_ID_1
.u32All
= 0x07060504;
1043 r700
->SPI_PS_INPUT_CNTL_0
.u32All
= 0x00000800;
1044 r700
->SPI_PS_INPUT_CNTL_1
.u32All
= 0x00000801;
1045 r700
->SPI_PS_INPUT_CNTL_2
.u32All
= 0x00000802;
1047 r700
->SPI_THREAD_GROUPING
.u32All
= 0;
1048 if (context
->radeon
.radeonScreen
->chip_family
>= CHIP_FAMILY_RV770
)
1049 SETfield(r700
->SPI_THREAD_GROUPING
.u32All
, 1, PS_GROUPING_shift
, PS_GROUPING_mask
);
1051 SETfield(r700
->CB_COLOR_CONTROL
.u32All
, 0xCC, ROP3_shift
, ROP3_mask
);
1052 CLEARbit(r700
->CB_COLOR_CONTROL
.u32All
, PER_MRT_BLEND_bit
);
1054 r700
->DB_SHADER_CONTROL
.u32All
= 0;
1055 SETbit(r700
->DB_SHADER_CONTROL
.u32All
, DUAL_EXPORT_ENABLE_bit
);
1057 /* Set up the culling control register */
1058 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_TRIANGLES
,
1059 POLYMODE_FRONT_PTYPE_shift
, POLYMODE_FRONT_PTYPE_mask
);
1060 SETfield(r700
->PA_SU_SC_MODE_CNTL
.u32All
, X_DRAW_TRIANGLES
,
1061 POLYMODE_BACK_PTYPE_shift
, POLYMODE_BACK_PTYPE_mask
);
1064 r700
->PA_SC_SCREEN_SCISSOR_TL
.u32All
= 0x0;
1066 SETfield(r700
->PA_SC_SCREEN_SCISSOR_BR
.u32All
,
1067 ((RADEONDRIPtr
)(context
->radeon
.radeonScreen
->driScreen
->pDevPriv
))->width
,
1068 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift
, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask
);
1069 SETfield(r700
->PA_SC_SCREEN_SCISSOR_BR
.u32All
,
1070 ((RADEONDRIPtr
)(context
->radeon
.radeonScreen
->driScreen
->pDevPriv
))->height
,
1071 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift
, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask
);
1073 /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
1074 r700
->PA_SC_CLIPRECT_RULE
.u32All
= 0;
1075 SETfield(r700
->PA_SC_CLIPRECT_RULE
.u32All
, CLIP_RULE_mask
, CLIP_RULE_shift
, CLIP_RULE_mask
);
1077 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
)
1078 r700
->PA_SC_EDGERULE
.u32All
= 0;
1080 r700
->PA_SC_EDGERULE
.u32All
= 0xAAAAAAAA;
1082 if (context
->radeon
.radeonScreen
->chip_family
< CHIP_FAMILY_RV770
) {
1083 r700
->PA_SC_MODE_CNTL
.u32All
= 0;
1084 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, WALK_ORDER_ENABLE_bit
);
1085 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, FORCE_EOV_CNTDWN_ENABLE_bit
);
1087 r700
->PA_SC_MODE_CNTL
.u32All
= 0x00500000;
1088 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, FORCE_EOV_REZ_ENABLE_bit
);
1089 SETbit(r700
->PA_SC_MODE_CNTL
.u32All
, FORCE_EOV_CNTDWN_ENABLE_bit
);
1092 /* Do scale XY and Z by 1/W0. */
1093 r700
->bEnablePerspective
= GL_TRUE
;
1094 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_XY_FMT_bit
);
1095 CLEARbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_Z_FMT_bit
);
1096 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VTX_W0_FMT_bit
);
1098 /* Enable viewport scaling for all three axis */
1099 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_X_SCALE_ENA_bit
);
1100 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_X_OFFSET_ENA_bit
);
1101 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Y_SCALE_ENA_bit
);
1102 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Y_OFFSET_ENA_bit
);
1103 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Z_SCALE_ENA_bit
);
1104 SETbit(r700
->PA_CL_VTE_CNTL
.u32All
, VPORT_Z_OFFSET_ENA_bit
);
1106 /* Set up point sizes and min/max values */
1107 SETfield(r700
->PA_SU_POINT_SIZE
.u32All
, 0x8,
1108 PA_SU_POINT_SIZE__HEIGHT_shift
, PA_SU_POINT_SIZE__HEIGHT_mask
);
1109 SETfield(r700
->PA_SU_POINT_SIZE
.u32All
, 0x8,
1110 PA_SU_POINT_SIZE__WIDTH_shift
, PA_SU_POINT_SIZE__WIDTH_mask
);
1111 CLEARfield(r700
->PA_SU_POINT_MINMAX
.u32All
, MIN_SIZE_mask
);
1112 SETfield(r700
->PA_SU_POINT_MINMAX
.u32All
, 0x8000, MAX_SIZE_shift
, MAX_SIZE_mask
);
1114 /* Set up line control */
1115 SETfield(r700
->PA_SU_LINE_CNTL
.u32All
, 0x8,
1116 PA_SU_LINE_CNTL__WIDTH_shift
, PA_SU_LINE_CNTL__WIDTH_mask
);
1118 r700
->PA_SC_LINE_CNTL
.u32All
= 0;
1119 CLEARbit(r700
->PA_SC_LINE_CNTL
.u32All
, EXPAND_LINE_WIDTH_bit
);
1120 SETbit(r700
->PA_SC_LINE_CNTL
.u32All
, LAST_PIXEL_bit
);
1122 /* Set up vertex control */
1123 r700
->PA_SU_VTX_CNTL
.u32All
= 0;
1124 CLEARfield(r700
->PA_SU_VTX_CNTL
.u32All
, QUANT_MODE_mask
);
1125 SETbit(r700
->PA_SU_VTX_CNTL
.u32All
, PIX_CENTER_bit
);
1126 SETfield(r700
->PA_SU_VTX_CNTL
.u32All
, X_ROUND_TO_EVEN
,
1127 PA_SU_VTX_CNTL__ROUND_MODE_shift
, PA_SU_VTX_CNTL__ROUND_MODE_mask
);
1129 /* to 1.0 = no guard band */
1130 r700
->PA_CL_GB_VERT_CLIP_ADJ
.u32All
= 0x3F800000; /* 1.0 */
1131 r700
->PA_CL_GB_VERT_DISC_ADJ
.u32All
= 0x3F800000;
1132 r700
->PA_CL_GB_HORZ_CLIP_ADJ
.u32All
= 0x3F800000;
1133 r700
->PA_CL_GB_HORZ_DISC_ADJ
.u32All
= 0x3F800000;
1136 r700
->CB_CLEAR_RED_R6XX
.f32All
= 1.0; //r6xx only
1137 r700
->CB_CLEAR_GREEN_R6XX
.f32All
= 0.0; //r6xx only
1138 r700
->CB_CLEAR_BLUE_R6XX
.f32All
= 1.0; //r6xx only
1139 r700
->CB_CLEAR_ALPHA_R6XX
.f32All
= 1.0; //r6xx only
1140 r700
->CB_FOG_RED_R6XX
.u32All
= 0; //r6xx only
1141 r700
->CB_FOG_GREEN_R6XX
.u32All
= 0; //r6xx only
1142 r700
->CB_FOG_BLUE_R6XX
.u32All
= 0; //r6xx only
1144 r700
->CB_BLEND_RED
.u32All
= 0;
1145 r700
->CB_BLEND_GREEN
.u32All
= 0;
1146 r700
->CB_BLEND_BLUE
.u32All
= 0;
1147 r700
->CB_BLEND_ALPHA
.u32All
= 0;
1149 r700
->CB_BLEND_CONTROL
.u32All
= 0;
1151 /* Disable color compares */
1152 SETfield(r700
->CB_CLRCMP_CONTROL
.u32All
, CLRCMP_DRAW_ALWAYS
,
1153 CLRCMP_FCN_SRC_shift
, CLRCMP_FCN_SRC_mask
);
1154 SETfield(r700
->CB_CLRCMP_CONTROL
.u32All
, CLRCMP_DRAW_ALWAYS
,
1155 CLRCMP_FCN_DST_shift
, CLRCMP_FCN_DST_mask
);
1156 SETfield(r700
->CB_CLRCMP_CONTROL
.u32All
, CLRCMP_SEL_SRC
,
1157 CLRCMP_FCN_SEL_shift
, CLRCMP_FCN_SEL_mask
);
1159 /* Zero out source */
1160 r700
->CB_CLRCMP_SRC
.u32All
= 0x00000000;
1162 /* Put a compare color in for error checking */
1163 r700
->CB_CLRCMP_DST
.u32All
= 0x000000FF;
1165 /* Set up color compare mask */
1166 r700
->CB_CLRCMP_MSK
.u32All
= 0xFFFFFFFF;
1168 /* default color mask */
1169 SETfield(r700
->CB_SHADER_MASK
.u32All
, 0xF, OUTPUT0_ENABLE_shift
, OUTPUT0_ENABLE_mask
);
1171 /* Enable all samples for multi-sample anti-aliasing */
1172 r700
->PA_SC_AA_MASK
.u32All
= 0xFFFFFFFF;
1174 r700
->PA_SC_AA_CONFIG
.u32All
= 0;
1176 r700
->SX_MISC
.u32All
= 0;
1178 r700InitSQConfig(ctx
);
1181 void r700InitStateFuncs(struct dd_function_table
*functions
) //-----------------
1183 functions
->UpdateState
= r700InvalidateState
;
1184 functions
->AlphaFunc
= r700AlphaFunc
;
1185 functions
->BlendColor
= r700BlendColor
;
1186 functions
->BlendEquationSeparate
= r700BlendEquationSeparate
;
1187 functions
->BlendFuncSeparate
= r700BlendFuncSeparate
;
1188 functions
->Enable
= r700Enable
;
1189 functions
->ColorMask
= r700ColorMask
;
1190 functions
->DepthFunc
= r700DepthFunc
;
1191 functions
->DepthMask
= r700DepthMask
;
1192 functions
->CullFace
= r700CullFace
;
1193 functions
->Fogfv
= r700Fogfv
;
1194 functions
->FrontFace
= r700FrontFace
;
1195 functions
->ShadeModel
= r700ShadeModel
;
1197 /* ARB_point_parameters */
1198 functions
->PointParameterfv
= r700PointParameter
;
1200 /* Stencil related */
1201 functions
->StencilFuncSeparate
= r700StencilFuncSeparate
;
1202 functions
->StencilMaskSeparate
= r700StencilMaskSeparate
;
1203 functions
->StencilOpSeparate
= r700StencilOpSeparate
;
1205 /* Viewport related */
1206 functions
->Viewport
= r700Viewport
;
1207 functions
->DepthRange
= r700DepthRange
;
1208 functions
->PointSize
= r700PointSize
;
1209 functions
->LineWidth
= r700LineWidth
;
1211 functions
->PolygonOffset
= r700PolygonOffset
;
1212 functions
->PolygonMode
= r700PolygonMode
;
1214 functions
->RenderMode
= r700RenderMode
;
1216 functions
->ClipPlane
= r700ClipPlane
;
1218 functions
->Scissor
= radeonScissor
;
1220 functions
->DrawBuffer
= radeonDrawBuffer
;
1221 functions
->ReadBuffer
= radeonReadBuffer
;