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radeon: Minor warnings cleanup.
[mesa.git] / src / mesa / drivers / dri / r600 / r700_state.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/context.h"
34 #include "main/dd.h"
35 #include "main/simple_list.h"
36
37 #include "tnl/tnl.h"
38 #include "tnl/t_pipeline.h"
39 #include "tnl/t_vp_build.h"
40 #include "swrast/swrast.h"
41 #include "swrast_setup/swrast_setup.h"
42 #include "main/api_arrayelt.h"
43 #include "main/state.h"
44 #include "main/framebuffer.h"
45
46 #include "shader/prog_parameter.h"
47 #include "shader/prog_statevars.h"
48 #include "vbo/vbo.h"
49 #include "main/texformat.h"
50
51 #include "r600_context.h"
52
53 #include "r700_state.h"
54
55 #include "r700_fragprog.h"
56 #include "r700_vertprog.h"
57
58
59 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state);
60 static void r700UpdatePolygonMode(GLcontext * ctx);
61 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state);
62 static void r700SetStencilState(GLcontext * ctx, GLboolean state);
63
64 void r700SetDefaultStates(context_t *context) //--------------------
65 {
66
67 }
68
69 void r700UpdateShaders (GLcontext * ctx) //----------------------------------
70 {
71 context_t *context = R700_CONTEXT(ctx);
72
73 GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
74 GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
75 int i;
76
77 if (ctx->FragmentProgram._Current) {
78 struct r700_fragment_program *fp = (struct r700_fragment_program *)
79 (ctx->FragmentProgram._Current);
80 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
81 {
82 fp->r700AsmCode.bR6xx = 1;
83 }
84
85 if(GL_FALSE == fp->translated)
86 {
87 if( GL_FALSE == r700TranslateFragmentShader(fp, &(fp->mesa_program)) )
88 {
89 //return GL_TRUE;
90 }
91 }
92 }
93
94 if (context->radeon.NewGLState)
95 {
96 struct r700_vertex_program *vp;
97 context->radeon.NewGLState = 0;
98
99 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++)
100 {
101 /* mat states from state var not array for sw */
102 dummy_attrib[i].stride = 0;
103
104 temp_attrib[i] = TNL_CONTEXT(ctx)->vb.AttribPtr[i];
105 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = &(dummy_attrib[i]);
106 }
107
108 _tnl_UpdateFixedFunctionProgram(ctx);
109
110 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++)
111 {
112 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = temp_attrib[i];
113 }
114
115 r700SelectVertexShader(ctx);
116 vp = (struct r700_vertex_program *)ctx->VertexProgram._Current;
117
118 if (vp->translated == GL_FALSE)
119 {
120 // TODO
121 //fprintf(stderr, "Failing back to sw-tcl\n");
122 //hw_tcl_on = future_hw_tcl_on = 0;
123 //r300ResetHwState(rmesa);
124 //
125 r700UpdateStateParameters(ctx, _NEW_PROGRAM);
126 return;
127 }
128 }
129
130 r700UpdateStateParameters(ctx, _NEW_PROGRAM);
131 }
132
133 /*
134 * To correctly position primitives:
135 */
136 void r700UpdateViewportOffset(GLcontext * ctx) //------------------
137 {
138 context_t *context = R700_CONTEXT(ctx);
139 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
140 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
141 GLfloat xoffset = (GLfloat) dPriv->x;
142 GLfloat yoffset = (GLfloat) dPriv->y + dPriv->h;
143 const GLfloat *v = ctx->Viewport._WindowMap.m;
144 int id = 0;
145
146 GLfloat tx = v[MAT_TX] + xoffset;
147 GLfloat ty = (-v[MAT_TY]) + yoffset;
148
149 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
150 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
151
152 radeonUpdateScissor(ctx);
153 }
154
155 /**
156 * Tell the card where to render (offset, pitch).
157 * Effected by glDrawBuffer, etc
158 */
159 void r700UpdateDrawBuffer(GLcontext * ctx) /* TODO */ //---------------------
160 {
161 #if 0 /* to be enabled */
162 context_t *context = R700_CONTEXT(ctx);
163
164 switch (ctx->DrawBuffer->_ColorDrawBufferIndexes[0])
165 {
166 case BUFFER_FRONT_LEFT:
167 context->target.rt = context->screen->frontBuffer;
168 break;
169 case BUFFER_BACK_LEFT:
170 context->target.rt = context->screen->backBuffer;
171 break;
172 default:
173 memset (&context->target.rt, sizeof(context->target.rt), 0);
174 }
175 #endif /* to be enabled */
176 }
177
178 static void r700FetchStateParameter(GLcontext * ctx,
179 const gl_state_index state[STATE_LENGTH],
180 GLfloat * value)
181 {
182 /* TODO */
183 }
184
185 void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state) //--------------------
186 {
187 struct r700_fragment_program *fp;
188 struct gl_program_parameter_list *paramList;
189 GLuint i;
190
191 if (!(new_state & (_NEW_BUFFERS | _NEW_PROGRAM)))
192 return;
193
194 fp = (struct r700_fragment_program *)ctx->FragmentProgram._Current;
195 if (!fp)
196 {
197 return;
198 }
199
200 paramList = fp->mesa_program.Base.Parameters;
201
202 if (!paramList)
203 {
204 return;
205 }
206
207 for (i = 0; i < paramList->NumParameters; i++)
208 {
209 if (paramList->Parameters[i].Type == PROGRAM_STATE_VAR)
210 {
211 r700FetchStateParameter(ctx,
212 paramList->Parameters[i].
213 StateIndexes,
214 paramList->ParameterValues[i]);
215 }
216 }
217 }
218
219 /**
220 * Called by Mesa after an internal state update.
221 */
222 static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //-------------------
223 {
224 context_t *context = R700_CONTEXT(ctx);
225
226 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
227
228 _swrast_InvalidateState(ctx, new_state);
229 _swsetup_InvalidateState(ctx, new_state);
230 _vbo_InvalidateState(ctx, new_state);
231 _tnl_InvalidateState(ctx, new_state);
232 _ae_invalidate_state(ctx, new_state);
233
234 if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL))
235 {
236 _mesa_update_framebuffer(ctx);
237 /* this updates the DrawBuffer's Width/Height if it's a FBO */
238 _mesa_update_draw_buffer_bounds(ctx);
239
240 r700UpdateDrawBuffer(ctx);
241 }
242
243 r700UpdateStateParameters(ctx, new_state);
244
245 if(GL_TRUE == r700->bEnablePerspective)
246 {
247 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
248 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
249 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
250
251 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
252
253 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
254 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
255 }
256 else
257 {
258 /* For orthogonal case. */
259 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
260 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
261
262 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
263
264 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
265 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
266 }
267
268 context->radeon.NewGLState |= new_state;
269 }
270
271 static void r700SetDepthState(GLcontext * ctx)
272 {
273 context_t *context = R700_CONTEXT(ctx);
274
275 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
276
277 if (ctx->Depth.Test)
278 {
279 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
280 if (ctx->Depth.Mask)
281 {
282 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
283 }
284 else
285 {
286 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
287 }
288
289 switch (ctx->Depth.Func)
290 {
291 case GL_NEVER:
292 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NEVER,
293 ZFUNC_shift, ZFUNC_mask);
294 break;
295 case GL_LESS:
296 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LESS,
297 ZFUNC_shift, ZFUNC_mask);
298 break;
299 case GL_EQUAL:
300 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_EQUAL,
301 ZFUNC_shift, ZFUNC_mask);
302 break;
303 case GL_LEQUAL:
304 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LEQUAL,
305 ZFUNC_shift, ZFUNC_mask);
306 break;
307 case GL_GREATER:
308 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GREATER,
309 ZFUNC_shift, ZFUNC_mask);
310 break;
311 case GL_NOTEQUAL:
312 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NOTEQUAL,
313 ZFUNC_shift, ZFUNC_mask);
314 break;
315 case GL_GEQUAL:
316 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GEQUAL,
317 ZFUNC_shift, ZFUNC_mask);
318 break;
319 case GL_ALWAYS:
320 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
321 ZFUNC_shift, ZFUNC_mask);
322 break;
323 default:
324 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
325 ZFUNC_shift, ZFUNC_mask);
326 break;
327 }
328 }
329 else
330 {
331 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
332 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
333 }
334 }
335
336 static void r700SetAlphaState(GLcontext * ctx)
337 {
338 context_t *context = R700_CONTEXT(ctx);
339 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
340 uint32_t alpha_func = REF_ALWAYS;
341 GLboolean really_enabled = ctx->Color.AlphaEnabled;
342
343 switch (ctx->Color.AlphaFunc) {
344 case GL_NEVER:
345 alpha_func = REF_NEVER;
346 break;
347 case GL_LESS:
348 alpha_func = REF_LESS;
349 break;
350 case GL_EQUAL:
351 alpha_func = REF_EQUAL;
352 break;
353 case GL_LEQUAL:
354 alpha_func = REF_LEQUAL;
355 break;
356 case GL_GREATER:
357 alpha_func = REF_GREATER;
358 break;
359 case GL_NOTEQUAL:
360 alpha_func = REF_NOTEQUAL;
361 break;
362 case GL_GEQUAL:
363 alpha_func = REF_GEQUAL;
364 break;
365 case GL_ALWAYS:
366 /*alpha_func = REF_ALWAYS; */
367 really_enabled = GL_FALSE;
368 break;
369 }
370
371 if (really_enabled) {
372 SETfield(r700->SX_ALPHA_TEST_CONTROL.u32All, alpha_func,
373 ALPHA_FUNC_shift, ALPHA_FUNC_mask);
374 SETbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
375 r700->SX_ALPHA_REF.f32All = ctx->Color.AlphaRef;
376 } else {
377 CLEARbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
378 }
379
380 }
381
382 static void r700AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref) //---------------
383 {
384 (void)func;
385 (void)ref;
386 r700SetAlphaState(ctx);
387 }
388
389
390 static void r700BlendColor(GLcontext * ctx, const GLfloat cf[4]) //----------------
391 {
392 context_t *context = R700_CONTEXT(ctx);
393 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
394
395 r700->CB_BLEND_RED.f32All = cf[0];
396 r700->CB_BLEND_GREEN.f32All = cf[1];
397 r700->CB_BLEND_BLUE.f32All = cf[2];
398 r700->CB_BLEND_ALPHA.f32All = cf[3];
399 }
400
401 static int blend_factor(GLenum factor, GLboolean is_src)
402 {
403 switch (factor) {
404 case GL_ZERO:
405 return BLEND_ZERO;
406 break;
407 case GL_ONE:
408 return BLEND_ONE;
409 break;
410 case GL_DST_COLOR:
411 return BLEND_DST_COLOR;
412 break;
413 case GL_ONE_MINUS_DST_COLOR:
414 return BLEND_ONE_MINUS_DST_COLOR;
415 break;
416 case GL_SRC_COLOR:
417 return BLEND_SRC_COLOR;
418 break;
419 case GL_ONE_MINUS_SRC_COLOR:
420 return BLEND_ONE_MINUS_SRC_COLOR;
421 break;
422 case GL_SRC_ALPHA:
423 return BLEND_SRC_ALPHA;
424 break;
425 case GL_ONE_MINUS_SRC_ALPHA:
426 return BLEND_ONE_MINUS_SRC_ALPHA;
427 break;
428 case GL_DST_ALPHA:
429 return BLEND_DST_ALPHA;
430 break;
431 case GL_ONE_MINUS_DST_ALPHA:
432 return BLEND_ONE_MINUS_DST_ALPHA;
433 break;
434 case GL_SRC_ALPHA_SATURATE:
435 return (is_src) ? BLEND_SRC_ALPHA_SATURATE : BLEND_ZERO;
436 break;
437 case GL_CONSTANT_COLOR:
438 return BLEND_CONSTANT_COLOR;
439 break;
440 case GL_ONE_MINUS_CONSTANT_COLOR:
441 return BLEND_ONE_MINUS_CONSTANT_COLOR;
442 break;
443 case GL_CONSTANT_ALPHA:
444 return BLEND_CONSTANT_ALPHA;
445 break;
446 case GL_ONE_MINUS_CONSTANT_ALPHA:
447 return BLEND_ONE_MINUS_CONSTANT_ALPHA;
448 break;
449 default:
450 fprintf(stderr, "unknown blend factor %x\n", factor);
451 return (is_src) ? BLEND_ONE : BLEND_ZERO;
452 break;
453 }
454 }
455
456 static void r700SetBlendState(GLcontext * ctx)
457 {
458 context_t *context = R700_CONTEXT(ctx);
459 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
460 int id = 0;
461 uint32_t blend_reg = 0, eqn, eqnA;
462
463 if (RGBA_LOGICOP_ENABLED(ctx) || !ctx->Color.BlendEnabled) {
464 SETfield(blend_reg,
465 BLEND_ONE, COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
466 SETfield(blend_reg,
467 BLEND_ZERO, COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
468 SETfield(blend_reg,
469 COMB_DST_PLUS_SRC, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
470 SETfield(blend_reg,
471 BLEND_ONE, ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
472 SETfield(blend_reg,
473 BLEND_ZERO, ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
474 SETfield(blend_reg,
475 COMB_DST_PLUS_SRC, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
476 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
477 r700->CB_BLEND_CONTROL.u32All = blend_reg;
478 else
479 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
480 return;
481 }
482
483 SETfield(blend_reg,
484 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
485 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
486 SETfield(blend_reg,
487 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
488 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
489
490 switch (ctx->Color.BlendEquationRGB) {
491 case GL_FUNC_ADD:
492 eqn = COMB_DST_PLUS_SRC;
493 break;
494 case GL_FUNC_SUBTRACT:
495 eqn = COMB_SRC_MINUS_DST;
496 break;
497 case GL_FUNC_REVERSE_SUBTRACT:
498 eqn = COMB_DST_MINUS_SRC;
499 break;
500 case GL_MIN:
501 eqn = COMB_MIN_DST_SRC;
502 SETfield(blend_reg,
503 BLEND_ONE,
504 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
505 SETfield(blend_reg,
506 BLEND_ONE,
507 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
508 break;
509 case GL_MAX:
510 eqn = COMB_MAX_DST_SRC;
511 SETfield(blend_reg,
512 BLEND_ONE,
513 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
514 SETfield(blend_reg,
515 BLEND_ONE,
516 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
517 break;
518
519 default:
520 fprintf(stderr,
521 "[%s:%u] Invalid RGB blend equation (0x%04x).\n",
522 __FUNCTION__, __LINE__, ctx->Color.BlendEquationRGB);
523 return;
524 }
525 SETfield(blend_reg,
526 eqn, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
527
528 SETfield(blend_reg,
529 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
530 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
531 SETfield(blend_reg,
532 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
533 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
534
535 switch (ctx->Color.BlendEquationA) {
536 case GL_FUNC_ADD:
537 eqnA = COMB_DST_PLUS_SRC;
538 break;
539 case GL_FUNC_SUBTRACT:
540 eqnA = COMB_SRC_MINUS_DST;
541 break;
542 case GL_FUNC_REVERSE_SUBTRACT:
543 eqnA = COMB_DST_MINUS_SRC;
544 break;
545 case GL_MIN:
546 eqnA = COMB_MIN_DST_SRC;
547 SETfield(blend_reg,
548 BLEND_ONE,
549 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
550 SETfield(blend_reg,
551 BLEND_ONE,
552 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
553 break;
554 case GL_MAX:
555 eqnA = COMB_MAX_DST_SRC;
556 SETfield(blend_reg,
557 BLEND_ONE,
558 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
559 SETfield(blend_reg,
560 BLEND_ONE,
561 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
562 break;
563 default:
564 fprintf(stderr,
565 "[%s:%u] Invalid A blend equation (0x%04x).\n",
566 __FUNCTION__, __LINE__, ctx->Color.BlendEquationA);
567 return;
568 }
569
570 SETfield(blend_reg,
571 eqnA, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
572
573 SETbit(blend_reg, SEPARATE_ALPHA_BLEND_bit);
574
575 if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
576 r700->CB_BLEND_CONTROL.u32All = blend_reg;
577 else {
578 r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
579 SETbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit);
580 }
581 SETfield(r700->CB_COLOR_CONTROL.u32All, (1 << id),
582 TARGET_BLEND_ENABLE_shift, TARGET_BLEND_ENABLE_mask);
583
584 }
585
586 static void r700BlendEquationSeparate(GLcontext * ctx,
587 GLenum modeRGB, GLenum modeA) //-----------------
588 {
589 r700SetBlendState(ctx);
590 }
591
592 static void r700BlendFuncSeparate(GLcontext * ctx,
593 GLenum sfactorRGB, GLenum dfactorRGB,
594 GLenum sfactorA, GLenum dfactorA) //------------------------
595 {
596 r700SetBlendState(ctx);
597 }
598
599 /**
600 * Translate LogicOp enums into hardware representation.
601 */
602 static GLuint translate_logicop(GLenum logicop)
603 {
604 switch (logicop) {
605 case GL_CLEAR:
606 return 0x00;
607 case GL_SET:
608 return 0xff;
609 case GL_COPY:
610 return 0xcc;
611 case GL_COPY_INVERTED:
612 return 0x33;
613 case GL_NOOP:
614 return 0xaa;
615 case GL_INVERT:
616 return 0x55;
617 case GL_AND:
618 return 0x88;
619 case GL_NAND:
620 return 0x77;
621 case GL_OR:
622 return 0xee;
623 case GL_NOR:
624 return 0x11;
625 case GL_XOR:
626 return 0x66;
627 case GL_EQUIV:
628 return 0xaa;
629 case GL_AND_REVERSE:
630 return 0x44;
631 case GL_AND_INVERTED:
632 return 0x22;
633 case GL_OR_REVERSE:
634 return 0xdd;
635 case GL_OR_INVERTED:
636 return 0xbb;
637 default:
638 fprintf(stderr, "unknown blend logic operation %x\n", logicop);
639 return 0xcc;
640 }
641 }
642
643 /**
644 * Used internally to update the r300->hw hardware state to match the
645 * current OpenGL state.
646 */
647 static void r700SetLogicOpState(GLcontext *ctx)
648 {
649 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
650
651 if (RGBA_LOGICOP_ENABLED(ctx))
652 SETfield(r700->CB_COLOR_CONTROL.u32All,
653 translate_logicop(ctx->Color.LogicOp), ROP3_shift, ROP3_mask);
654 else
655 SETfield(r700->CB_COLOR_CONTROL.u32All, 0xCC, ROP3_shift, ROP3_mask);
656 }
657
658 /**
659 * Called by Mesa when an application program changes the LogicOp state
660 * via glLogicOp.
661 */
662 static void r700LogicOpcode(GLcontext *ctx, GLenum logicop)
663 {
664 if (RGBA_LOGICOP_ENABLED(ctx))
665 r700SetLogicOpState(ctx);
666 }
667
668 static void r700UpdateCulling(GLcontext * ctx)
669 {
670 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
671
672 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
673 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
674 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
675
676 if (ctx->Polygon.CullFlag)
677 {
678 switch (ctx->Polygon.CullFaceMode)
679 {
680 case GL_FRONT:
681 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
682 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
683 break;
684 case GL_BACK:
685 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
686 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
687 break;
688 case GL_FRONT_AND_BACK:
689 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
690 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
691 break;
692 default:
693 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
694 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
695 break;
696 }
697 }
698
699 switch (ctx->Polygon.FrontFace)
700 {
701 case GL_CW:
702 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
703 break;
704 case GL_CCW:
705 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
706 break;
707 default:
708 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); /* default: ccw */
709 break;
710 }
711 }
712
713 static void r700UpdateLineStipple(GLcontext * ctx)
714 {
715 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
716 if (ctx->Line.StippleFlag)
717 {
718 SETbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
719 }
720 else
721 {
722 CLEARbit(r700->PA_SC_MODE_CNTL.u32All, LINE_STIPPLE_ENABLE_bit);
723 }
724 }
725
726 static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //------------------
727 {
728 context_t *context = R700_CONTEXT(ctx);
729
730 switch (cap) {
731 case GL_TEXTURE_1D:
732 case GL_TEXTURE_2D:
733 case GL_TEXTURE_3D:
734 /* empty */
735 break;
736 case GL_FOG:
737 /* empty */
738 break;
739 case GL_ALPHA_TEST:
740 r700SetAlphaState(ctx);
741 break;
742 case GL_COLOR_LOGIC_OP:
743 r700SetLogicOpState(ctx);
744 /* fall-through, because logic op overrides blending */
745 case GL_BLEND:
746 r700SetBlendState(ctx);
747 break;
748 case GL_CLIP_PLANE0:
749 case GL_CLIP_PLANE1:
750 case GL_CLIP_PLANE2:
751 case GL_CLIP_PLANE3:
752 case GL_CLIP_PLANE4:
753 case GL_CLIP_PLANE5:
754 r700SetClipPlaneState(ctx, cap, state);
755 break;
756 case GL_DEPTH_TEST:
757 r700SetDepthState(ctx);
758 break;
759 case GL_STENCIL_TEST:
760 r700SetStencilState(ctx, state);
761 break;
762 case GL_CULL_FACE:
763 r700UpdateCulling(ctx);
764 break;
765 case GL_POLYGON_OFFSET_POINT:
766 case GL_POLYGON_OFFSET_LINE:
767 case GL_POLYGON_OFFSET_FILL:
768 r700SetPolygonOffsetState(ctx, state);
769 break;
770 case GL_SCISSOR_TEST:
771 radeon_firevertices(&context->radeon);
772 context->radeon.state.scissor.enabled = state;
773 radeonUpdateScissor(ctx);
774 break;
775 case GL_LINE_STIPPLE:
776 r700UpdateLineStipple(ctx);
777 break;
778 default:
779 break;
780 }
781
782 }
783
784 /**
785 * Handle glColorMask()
786 */
787 static void r700ColorMask(GLcontext * ctx,
788 GLboolean r, GLboolean g, GLboolean b, GLboolean a) //------------------
789 {
790 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
791 unsigned int mask = ((r ? 1 : 0) |
792 (g ? 2 : 0) |
793 (b ? 4 : 0) |
794 (a ? 8 : 0));
795
796 if (mask != r700->CB_SHADER_MASK.u32All)
797 SETfield(r700->CB_SHADER_MASK.u32All, mask, OUTPUT0_ENABLE_shift, OUTPUT0_ENABLE_mask);
798 }
799
800 /**
801 * Change the depth testing function.
802 *
803 * \note Mesa already filters redundant calls to this function.
804 */
805 static void r700DepthFunc(GLcontext * ctx, GLenum func) //--------------------
806 {
807 r700SetDepthState(ctx);
808 }
809
810 /**
811 * Enable/Disable depth writing.
812 *
813 * \note Mesa already filters redundant calls to this function.
814 */
815 static void r700DepthMask(GLcontext * ctx, GLboolean mask) //------------------
816 {
817 r700SetDepthState(ctx);
818 }
819
820 /**
821 * Change the culling mode.
822 *
823 * \note Mesa already filters redundant calls to this function.
824 */
825 static void r700CullFace(GLcontext * ctx, GLenum mode) //-----------------
826 {
827 r700UpdateCulling(ctx);
828 }
829
830 /* =============================================================
831 * Fog
832 */
833 static void r700Fogfv(GLcontext * ctx, GLenum pname, const GLfloat * param) //--------------
834 {
835 }
836
837 /**
838 * Change the polygon orientation.
839 *
840 * \note Mesa already filters redundant calls to this function.
841 */
842 static void r700FrontFace(GLcontext * ctx, GLenum mode) //------------------
843 {
844 r700UpdateCulling(ctx);
845 r700UpdatePolygonMode(ctx);
846 }
847
848 static void r700ShadeModel(GLcontext * ctx, GLenum mode) //--------------------
849 {
850 context_t *context = R700_CONTEXT(ctx);
851 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
852
853 /* also need to set/clear FLAT_SHADE bit per param in SPI_PS_INPUT_CNTL_[0-31] */
854 switch (mode) {
855 case GL_FLAT:
856 SETbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
857 break;
858 case GL_SMOOTH:
859 CLEARbit(r700->SPI_INTERP_CONTROL_0.u32All, FLAT_SHADE_ENA_bit);
860 break;
861 default:
862 return;
863 }
864 }
865
866 /* =============================================================
867 * Point state
868 */
869 static void r700PointSize(GLcontext * ctx, GLfloat size)
870 {
871 context_t *context = R700_CONTEXT(ctx);
872 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
873
874 /* We need to clamp to user defined range here, because
875 * the HW clamping happens only for per vertex point size. */
876 size = CLAMP(size, ctx->Point.MinSize, ctx->Point.MaxSize);
877
878 /* same size limits for AA, non-AA points */
879 size = CLAMP(size, ctx->Const.MinPointSize, ctx->Const.MaxPointSize);
880
881 /* format is 12.4 fixed point */
882 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 16),
883 PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask);
884 SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 16),
885 PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask);
886
887 }
888
889 static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * param) //---------------
890 {
891 context_t *context = R700_CONTEXT(ctx);
892 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
893
894 /* format is 12.4 fixed point */
895 switch (pname) {
896 case GL_POINT_SIZE_MIN:
897 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MinSize * 16.0),
898 MIN_SIZE_shift, MIN_SIZE_mask);
899 break;
900 case GL_POINT_SIZE_MAX:
901 SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MaxSize * 16.0),
902 MAX_SIZE_shift, MAX_SIZE_mask);
903 break;
904 case GL_POINT_DISTANCE_ATTENUATION:
905 break;
906 case GL_POINT_FADE_THRESHOLD_SIZE:
907 break;
908 default:
909 break;
910 }
911 }
912
913 static int translate_stencil_func(int func)
914 {
915 switch (func) {
916 case GL_NEVER:
917 return REF_NEVER;
918 case GL_LESS:
919 return REF_LESS;
920 case GL_EQUAL:
921 return REF_EQUAL;
922 case GL_LEQUAL:
923 return REF_LEQUAL;
924 case GL_GREATER:
925 return REF_GREATER;
926 case GL_NOTEQUAL:
927 return REF_NOTEQUAL;
928 case GL_GEQUAL:
929 return REF_GEQUAL;
930 case GL_ALWAYS:
931 return REF_ALWAYS;
932 }
933 return 0;
934 }
935
936 static int translate_stencil_op(int op)
937 {
938 switch (op) {
939 case GL_KEEP:
940 return STENCIL_KEEP;
941 case GL_ZERO:
942 return STENCIL_ZERO;
943 case GL_REPLACE:
944 return STENCIL_REPLACE;
945 case GL_INCR:
946 return STENCIL_INCR_CLAMP;
947 case GL_DECR:
948 return STENCIL_DECR_CLAMP;
949 case GL_INCR_WRAP_EXT:
950 return STENCIL_INCR_WRAP;
951 case GL_DECR_WRAP_EXT:
952 return STENCIL_DECR_WRAP;
953 case GL_INVERT:
954 return STENCIL_INVERT;
955 default:
956 WARN_ONCE("Do not know how to translate stencil op");
957 return STENCIL_KEEP;
958 }
959 return 0;
960 }
961
962 static void r700SetStencilState(GLcontext * ctx, GLboolean state)
963 {
964 context_t *context = R700_CONTEXT(ctx);
965 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
966 GLboolean hw_stencil = GL_FALSE;
967
968 //fixme
969 //r300CatchStencilFallback(ctx);
970
971 if (ctx->DrawBuffer) {
972 struct radeon_renderbuffer *rrbStencil
973 = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
974 hw_stencil = (rrbStencil && rrbStencil->bo);
975 }
976
977 if (hw_stencil) {
978 if (state)
979 SETbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
980 else
981 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
982 }
983 }
984
985 static void r700StencilFuncSeparate(GLcontext * ctx, GLenum face,
986 GLenum func, GLint ref, GLuint mask) //---------------------
987 {
988 context_t *context = R700_CONTEXT(ctx);
989 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
990 const unsigned back = ctx->Stencil._BackFace;
991
992 //fixme
993 //r300CatchStencilFallback(ctx);
994
995 //front
996 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.Ref[0],
997 STENCILREF_shift, STENCILREF_mask);
998 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.ValueMask[0],
999 STENCILMASK_shift, STENCILMASK_mask);
1000
1001 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[0]),
1002 STENCILFUNC_shift, STENCILFUNC_mask);
1003
1004 //back
1005 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.Ref[back],
1006 STENCILREF_BF_shift, STENCILREF_BF_mask);
1007 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.ValueMask[back],
1008 STENCILMASK_BF_shift, STENCILMASK_BF_mask);
1009
1010 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[back]),
1011 STENCILFUNC_BF_shift, STENCILFUNC_BF_mask);
1012
1013 }
1014
1015 static void r700StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) //--------------
1016 {
1017 context_t *context = R700_CONTEXT(ctx);
1018 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1019 const unsigned back = ctx->Stencil._BackFace;
1020
1021 //fixme
1022 //r300CatchStencilFallback(ctx);
1023
1024 // front
1025 SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.WriteMask[0],
1026 STENCILWRITEMASK_shift, STENCILWRITEMASK_mask);
1027
1028 // back
1029 SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.WriteMask[back],
1030 STENCILWRITEMASK_BF_shift, STENCILWRITEMASK_BF_mask);
1031
1032 }
1033
1034 static void r700StencilOpSeparate(GLcontext * ctx, GLenum face,
1035 GLenum fail, GLenum zfail, GLenum zpass) //--------------------
1036 {
1037 context_t *context = R700_CONTEXT(ctx);
1038 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1039 const unsigned back = ctx->Stencil._BackFace;
1040
1041 //fixme
1042 //r300CatchStencilFallback(ctx);
1043
1044 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[0]),
1045 STENCILFAIL_shift, STENCILFAIL_mask);
1046 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[0]),
1047 STENCILZFAIL_shift, STENCILZFAIL_mask);
1048 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[0]),
1049 STENCILZPASS_shift, STENCILZPASS_mask);
1050
1051 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[back]),
1052 STENCILFAIL_BF_shift, STENCILFAIL_BF_mask);
1053 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[back]),
1054 STENCILZFAIL_BF_shift, STENCILZFAIL_BF_mask);
1055 SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[back]),
1056 STENCILZPASS_BF_shift, STENCILZPASS_BF_mask);
1057 }
1058
1059 static void r700UpdateWindow(GLcontext * ctx, int id) //--------------------
1060 {
1061 context_t *context = R700_CONTEXT(ctx);
1062 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1063 __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
1064 GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
1065 GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
1066 const GLfloat *v = ctx->Viewport._WindowMap.m;
1067 const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
1068 const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
1069 GLfloat y_scale, y_bias;
1070
1071 if (render_to_fbo) {
1072 y_scale = 1.0;
1073 y_bias = 0;
1074 } else {
1075 y_scale = -1.0;
1076 y_bias = yoffset;
1077 }
1078
1079 GLfloat sx = v[MAT_SX];
1080 GLfloat tx = v[MAT_TX] + xoffset;
1081 GLfloat sy = v[MAT_SY] * y_scale;
1082 GLfloat ty = (v[MAT_TY] * y_scale) + y_bias;
1083 GLfloat sz = v[MAT_SZ] * depthScale;
1084 GLfloat tz = v[MAT_TZ] * depthScale;
1085
1086 /* TODO : Need DMA flush as well. */
1087
1088 r700->viewport[id].PA_CL_VPORT_XSCALE.f32All = sx;
1089 r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
1090
1091 r700->viewport[id].PA_CL_VPORT_YSCALE.f32All = sy;
1092 r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
1093
1094 r700->viewport[id].PA_CL_VPORT_ZSCALE.f32All = sz;
1095 r700->viewport[id].PA_CL_VPORT_ZOFFSET.f32All = tz;
1096
1097 r700->viewport[id].enabled = GL_TRUE;
1098
1099 r700SetScissor(context);
1100 }
1101
1102
1103 static void r700Viewport(GLcontext * ctx,
1104 GLint x,
1105 GLint y,
1106 GLsizei width,
1107 GLsizei height) //--------------------
1108 {
1109 r700UpdateWindow(ctx, 0);
1110
1111 radeon_viewport(ctx, x, y, width, height);
1112 }
1113
1114 static void r700DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) //-------------
1115 {
1116 r700UpdateWindow(ctx, 0);
1117 }
1118
1119 static void r700LineWidth(GLcontext * ctx, GLfloat widthf) //---------------
1120 {
1121 context_t *context = R700_CONTEXT(ctx);
1122 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1123 uint32_t lineWidth = (uint32_t)((widthf * 0.5) * (1 << 4));
1124 if (lineWidth > 0xFFFF)
1125 lineWidth = 0xFFFF;
1126 SETfield(r700->PA_SU_LINE_CNTL.u32All,(uint16_t)lineWidth,
1127 PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
1128 }
1129
1130 static void r700LineStipple(GLcontext *ctx, GLint factor, GLushort pattern)
1131 {
1132 context_t *context = R700_CONTEXT(ctx);
1133 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1134
1135 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, pattern, LINE_PATTERN_shift, LINE_PATTERN_mask);
1136 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, (factor-1), REPEAT_COUNT_shift, REPEAT_COUNT_mask);
1137 SETfield(r700->PA_SC_LINE_STIPPLE.u32All, 1, AUTO_RESET_CNTL_shift, AUTO_RESET_CNTL_mask);
1138 }
1139
1140 static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state)
1141 {
1142 context_t *context = R700_CONTEXT(ctx);
1143 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1144
1145 if (state) {
1146 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1147 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1148 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1149 } else {
1150 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
1151 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
1152 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
1153 }
1154 }
1155
1156 static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) //--------------
1157 {
1158 context_t *context = R700_CONTEXT(ctx);
1159 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1160 GLfloat constant = units;
1161
1162 switch (ctx->Visual.depthBits) {
1163 case 16:
1164 constant *= 4.0;
1165 break;
1166 case 24:
1167 constant *= 2.0;
1168 break;
1169 }
1170
1171 factor *= 12.0;
1172
1173 r700->PA_SU_POLY_OFFSET_FRONT_SCALE.f32All = factor;
1174 r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.f32All = constant;
1175 r700->PA_SU_POLY_OFFSET_BACK_SCALE.f32All = factor;
1176 r700->PA_SU_POLY_OFFSET_BACK_OFFSET.f32All = constant;
1177 }
1178
1179 static void r700UpdatePolygonMode(GLcontext * ctx)
1180 {
1181 context_t *context = R700_CONTEXT(ctx);
1182 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1183
1184 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DISABLE_POLY_MODE, POLY_MODE_shift, POLY_MODE_mask);
1185
1186 /* Only do something if a polygon mode is wanted, default is GL_FILL */
1187 if (ctx->Polygon.FrontMode != GL_FILL ||
1188 ctx->Polygon.BackMode != GL_FILL) {
1189 GLenum f, b;
1190
1191 /* Handle GL_CW (clock wise and GL_CCW (counter clock wise)
1192 * correctly by selecting the correct front and back face
1193 */
1194 if (ctx->Polygon.FrontFace == GL_CCW) {
1195 f = ctx->Polygon.FrontMode;
1196 b = ctx->Polygon.BackMode;
1197 } else {
1198 f = ctx->Polygon.BackMode;
1199 b = ctx->Polygon.FrontMode;
1200 }
1201
1202 /* Enable polygon mode */
1203 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DUAL_MODE, POLY_MODE_shift, POLY_MODE_mask);
1204
1205 switch (f) {
1206 case GL_LINE:
1207 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1208 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1209 break;
1210 case GL_POINT:
1211 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1212 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1213 break;
1214 case GL_FILL:
1215 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1216 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
1217 break;
1218 }
1219
1220 switch (b) {
1221 case GL_LINE:
1222 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
1223 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1224 break;
1225 case GL_POINT:
1226 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
1227 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1228 break;
1229 case GL_FILL:
1230 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
1231 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
1232 break;
1233 }
1234 }
1235 }
1236
1237 static void r700PolygonMode(GLcontext * ctx, GLenum face, GLenum mode) //------------------
1238 {
1239 (void)face;
1240 (void)mode;
1241
1242 r700UpdatePolygonMode(ctx);
1243 }
1244
1245 static void r700RenderMode(GLcontext * ctx, GLenum mode) //---------------------
1246 {
1247 }
1248
1249 static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
1250 {
1251 context_t *context = R700_CONTEXT(ctx);
1252 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1253 GLint p;
1254 GLint *ip;
1255
1256 p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
1257 ip = (GLint *)ctx->Transform._ClipUserPlane[p];
1258
1259 r700->ucp[p].PA_CL_UCP_0_X.u32All = ip[0];
1260 r700->ucp[p].PA_CL_UCP_0_Y.u32All = ip[1];
1261 r700->ucp[p].PA_CL_UCP_0_Z.u32All = ip[2];
1262 r700->ucp[p].PA_CL_UCP_0_W.u32All = ip[3];
1263 }
1264
1265 static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state)
1266 {
1267 context_t *context = R700_CONTEXT(ctx);
1268 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1269 GLuint p;
1270
1271 p = cap - GL_CLIP_PLANE0;
1272 if (state) {
1273 r700->PA_CL_CLIP_CNTL.u32All |= (UCP_ENA_0_bit << p);
1274 r700->ucp[p].enabled = GL_TRUE;
1275 r700ClipPlane(ctx, cap, NULL);
1276 } else {
1277 r700->PA_CL_CLIP_CNTL.u32All &= ~(UCP_ENA_0_bit << p);
1278 r700->ucp[p].enabled = GL_FALSE;
1279 }
1280 }
1281
1282 void r700SetScissor(context_t *context) //---------------
1283 {
1284 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1285 unsigned x1, y1, x2, y2;
1286 int id = 0;
1287 struct radeon_renderbuffer *rrb;
1288
1289 rrb = radeon_get_colorbuffer(&context->radeon);
1290 if (!rrb || !rrb->bo) {
1291 return;
1292 }
1293 if (context->radeon.state.scissor.enabled) {
1294 x1 = context->radeon.state.scissor.rect.x1;
1295 y1 = context->radeon.state.scissor.rect.y1;
1296 x2 = context->radeon.state.scissor.rect.x2 - 1;
1297 y2 = context->radeon.state.scissor.rect.y2 - 1;
1298 } else {
1299 x1 = rrb->dPriv->x;
1300 y1 = rrb->dPriv->y;
1301 x2 = rrb->dPriv->x + rrb->dPriv->w;
1302 y2 = rrb->dPriv->y + rrb->dPriv->h;
1303 }
1304
1305 /* window */
1306 SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1307 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, x1,
1308 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask);
1309 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, y1,
1310 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask);
1311
1312 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, x2,
1313 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask);
1314 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, y2,
1315 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask);
1316
1317
1318 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, x1,
1319 PA_SC_CLIPRECT_0_TL__TL_X_shift, PA_SC_CLIPRECT_0_TL__TL_X_mask);
1320 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, y1,
1321 PA_SC_CLIPRECT_0_TL__TL_Y_shift, PA_SC_CLIPRECT_0_TL__TL_Y_mask);
1322 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, x2,
1323 PA_SC_CLIPRECT_0_BR__BR_X_shift, PA_SC_CLIPRECT_0_BR__BR_X_mask);
1324 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, y2,
1325 PA_SC_CLIPRECT_0_BR__BR_Y_shift, PA_SC_CLIPRECT_0_BR__BR_Y_mask);
1326
1327 r700->PA_SC_CLIPRECT_1_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1328 r700->PA_SC_CLIPRECT_1_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1329 r700->PA_SC_CLIPRECT_2_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1330 r700->PA_SC_CLIPRECT_2_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1331 r700->PA_SC_CLIPRECT_3_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
1332 r700->PA_SC_CLIPRECT_3_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
1333
1334 /* more....2d clip */
1335 SETbit(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1336 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, x1,
1337 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask);
1338 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, y1,
1339 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask);
1340 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, x2,
1341 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask);
1342 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, y2,
1343 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask);
1344
1345 SETbit(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
1346 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, x1,
1347 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask);
1348 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, y1,
1349 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask);
1350 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, x2,
1351 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask);
1352 SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, y2,
1353 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask);
1354
1355 r700->viewport[id].PA_SC_VPORT_ZMIN_0.u32All = 0;
1356 r700->viewport[id].PA_SC_VPORT_ZMAX_0.u32All = 0x3F800000;
1357 r700->viewport[id].enabled = GL_TRUE;
1358 }
1359
1360 void r700SetRenderTarget(context_t *context, int id)
1361 {
1362 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1363
1364 struct radeon_renderbuffer *rrb;
1365 unsigned int nPitchInPixel;
1366
1367 /* screen/window/view */
1368 SETfield(r700->CB_TARGET_MASK.u32All, 0xF, (4 * id), TARGET0_ENABLE_mask);
1369
1370 rrb = radeon_get_colorbuffer(&context->radeon);
1371 if (!rrb || !rrb->bo) {
1372 fprintf(stderr, "no rrb\n");
1373 return;
1374 }
1375
1376 /* color buffer */
1377 r700->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset;
1378
1379 nPitchInPixel = rrb->pitch/rrb->cpp;
1380 SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1,
1381 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
1382 SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
1383 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
1384 r700->render_target[id].CB_COLOR0_BASE.u32All = 0;
1385 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
1386 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL,
1387 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
1388 if(4 == rrb->cpp)
1389 {
1390 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_8_8_8_8,
1391 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
1392 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT, COMP_SWAP_shift, COMP_SWAP_mask);
1393 }
1394 else
1395 {
1396 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_5_6_5,
1397 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
1398 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT_REV,
1399 COMP_SWAP_shift, COMP_SWAP_mask);
1400 }
1401 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
1402 SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit);
1403 SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
1404
1405 r700->render_target[id].enabled = GL_TRUE;
1406 }
1407
1408 void r700SetDepthTarget(context_t *context)
1409 {
1410 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1411
1412 struct radeon_renderbuffer *rrb;
1413 unsigned int nPitchInPixel;
1414
1415 /* depth buf */
1416 r700->DB_DEPTH_SIZE.u32All = 0;
1417 r700->DB_DEPTH_BASE.u32All = 0;
1418 r700->DB_DEPTH_INFO.u32All = 0;
1419
1420 r700->DB_DEPTH_CLEAR.u32All = 0x3F800000;
1421 r700->DB_DEPTH_VIEW.u32All = 0;
1422 r700->DB_RENDER_CONTROL.u32All = 0;
1423 SETbit(r700->DB_RENDER_CONTROL.u32All, STENCIL_COMPRESS_DISABLE_bit);
1424 SETbit(r700->DB_RENDER_CONTROL.u32All, DEPTH_COMPRESS_DISABLE_bit);
1425 r700->DB_RENDER_OVERRIDE.u32All = 0;
1426 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1427 SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit);
1428 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
1429 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
1430 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
1431
1432 r700->DB_ALPHA_TO_MASK.u32All = 0;
1433 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask);
1434 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET1_shift, ALPHA_TO_MASK_OFFSET1_mask);
1435 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET2_shift, ALPHA_TO_MASK_OFFSET2_mask);
1436 SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET3_shift, ALPHA_TO_MASK_OFFSET3_mask);
1437
1438 rrb = radeon_get_depthbuffer(&context->radeon);
1439 if (!rrb)
1440 return;
1441
1442 nPitchInPixel = rrb->pitch/rrb->cpp;
1443
1444 SETfield(r700->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1,
1445 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
1446 SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
1447 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */
1448
1449 if(4 == rrb->cpp)
1450 {
1451 switch (GL_CONTEXT(context)->Visual.depthBits)
1452 {
1453 case 16:
1454 case 24:
1455 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_8_24,
1456 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
1457 break;
1458 default:
1459 fprintf(stderr, "Error: Unsupported depth %d... exiting\n",
1460 GL_CONTEXT(context)->Visual.depthBits);
1461 _mesa_exit(-1);
1462 }
1463 }
1464 else
1465 {
1466 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16,
1467 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
1468 }
1469 SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_2D_TILED_THIN1,
1470 DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask);
1471 /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */
1472 }
1473
1474 static void r700InitSQConfig(GLcontext * ctx)
1475 {
1476 context_t *context = R700_CONTEXT(ctx);
1477 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1478 int ps_prio;
1479 int vs_prio;
1480 int gs_prio;
1481 int es_prio;
1482 int num_ps_gprs;
1483 int num_vs_gprs;
1484 int num_gs_gprs;
1485 int num_es_gprs;
1486 int num_temp_gprs;
1487 int num_ps_threads;
1488 int num_vs_threads;
1489 int num_gs_threads;
1490 int num_es_threads;
1491 int num_ps_stack_entries;
1492 int num_vs_stack_entries;
1493 int num_gs_stack_entries;
1494 int num_es_stack_entries;
1495
1496 // SQ
1497 ps_prio = 0;
1498 vs_prio = 1;
1499 gs_prio = 2;
1500 es_prio = 3;
1501 switch (context->radeon.radeonScreen->chip_family) {
1502 case CHIP_FAMILY_R600:
1503 num_ps_gprs = 192;
1504 num_vs_gprs = 56;
1505 num_temp_gprs = 4;
1506 num_gs_gprs = 0;
1507 num_es_gprs = 0;
1508 num_ps_threads = 136;
1509 num_vs_threads = 48;
1510 num_gs_threads = 4;
1511 num_es_threads = 4;
1512 num_ps_stack_entries = 128;
1513 num_vs_stack_entries = 128;
1514 num_gs_stack_entries = 0;
1515 num_es_stack_entries = 0;
1516 break;
1517 case CHIP_FAMILY_RV630:
1518 case CHIP_FAMILY_RV635:
1519 num_ps_gprs = 84;
1520 num_vs_gprs = 36;
1521 num_temp_gprs = 4;
1522 num_gs_gprs = 0;
1523 num_es_gprs = 0;
1524 num_ps_threads = 144;
1525 num_vs_threads = 40;
1526 num_gs_threads = 4;
1527 num_es_threads = 4;
1528 num_ps_stack_entries = 40;
1529 num_vs_stack_entries = 40;
1530 num_gs_stack_entries = 32;
1531 num_es_stack_entries = 16;
1532 break;
1533 case CHIP_FAMILY_RV610:
1534 case CHIP_FAMILY_RV620:
1535 case CHIP_FAMILY_RS780:
1536 default:
1537 num_ps_gprs = 84;
1538 num_vs_gprs = 36;
1539 num_temp_gprs = 4;
1540 num_gs_gprs = 0;
1541 num_es_gprs = 0;
1542 num_ps_threads = 136;
1543 num_vs_threads = 48;
1544 num_gs_threads = 4;
1545 num_es_threads = 4;
1546 num_ps_stack_entries = 40;
1547 num_vs_stack_entries = 40;
1548 num_gs_stack_entries = 32;
1549 num_es_stack_entries = 16;
1550 break;
1551 case CHIP_FAMILY_RV670:
1552 num_ps_gprs = 144;
1553 num_vs_gprs = 40;
1554 num_temp_gprs = 4;
1555 num_gs_gprs = 0;
1556 num_es_gprs = 0;
1557 num_ps_threads = 136;
1558 num_vs_threads = 48;
1559 num_gs_threads = 4;
1560 num_es_threads = 4;
1561 num_ps_stack_entries = 40;
1562 num_vs_stack_entries = 40;
1563 num_gs_stack_entries = 32;
1564 num_es_stack_entries = 16;
1565 break;
1566 case CHIP_FAMILY_RV770:
1567 num_ps_gprs = 192;
1568 num_vs_gprs = 56;
1569 num_temp_gprs = 4;
1570 num_gs_gprs = 0;
1571 num_es_gprs = 0;
1572 num_ps_threads = 188;
1573 num_vs_threads = 60;
1574 num_gs_threads = 0;
1575 num_es_threads = 0;
1576 num_ps_stack_entries = 256;
1577 num_vs_stack_entries = 256;
1578 num_gs_stack_entries = 0;
1579 num_es_stack_entries = 0;
1580 break;
1581 case CHIP_FAMILY_RV730:
1582 case CHIP_FAMILY_RV740:
1583 num_ps_gprs = 84;
1584 num_vs_gprs = 36;
1585 num_temp_gprs = 4;
1586 num_gs_gprs = 0;
1587 num_es_gprs = 0;
1588 num_ps_threads = 188;
1589 num_vs_threads = 60;
1590 num_gs_threads = 0;
1591 num_es_threads = 0;
1592 num_ps_stack_entries = 128;
1593 num_vs_stack_entries = 128;
1594 num_gs_stack_entries = 0;
1595 num_es_stack_entries = 0;
1596 break;
1597 case CHIP_FAMILY_RV710:
1598 num_ps_gprs = 192;
1599 num_vs_gprs = 56;
1600 num_temp_gprs = 4;
1601 num_gs_gprs = 0;
1602 num_es_gprs = 0;
1603 num_ps_threads = 144;
1604 num_vs_threads = 48;
1605 num_gs_threads = 0;
1606 num_es_threads = 0;
1607 num_ps_stack_entries = 128;
1608 num_vs_stack_entries = 128;
1609 num_gs_stack_entries = 0;
1610 num_es_stack_entries = 0;
1611 break;
1612 }
1613
1614 r700->sq_config.SQ_CONFIG.u32All = 0;
1615 if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
1616 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
1617 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
1618 (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
1619 CLEARbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1620 else
1621 SETbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
1622 SETbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit);
1623 SETbit(r700->sq_config.SQ_CONFIG.u32All, ALU_INST_PREFER_VECTOR_bit);
1624 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, PS_PRIO_shift, PS_PRIO_mask);
1625 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, VS_PRIO_shift, VS_PRIO_mask);
1626 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, GS_PRIO_shift, GS_PRIO_mask);
1627 SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, ES_PRIO_shift, ES_PRIO_mask);
1628
1629 r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All = 0;
1630 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_ps_gprs, NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
1631 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_vs_gprs, NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
1632 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_temp_gprs,
1633 NUM_CLAUSE_TEMP_GPRS_shift, NUM_CLAUSE_TEMP_GPRS_mask);
1634
1635 r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All = 0;
1636 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_gs_gprs, NUM_GS_GPRS_shift, NUM_GS_GPRS_mask);
1637 SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_es_gprs, NUM_ES_GPRS_shift, NUM_ES_GPRS_mask);
1638
1639 r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All = 0;
1640 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_ps_threads,
1641 NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
1642 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_vs_threads,
1643 NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
1644 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_gs_threads,
1645 NUM_GS_THREADS_shift, NUM_GS_THREADS_mask);
1646 SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_es_threads,
1647 NUM_ES_THREADS_shift, NUM_ES_THREADS_mask);
1648
1649 r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All = 0;
1650 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_ps_stack_entries,
1651 NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
1652 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_vs_stack_entries,
1653 NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
1654
1655 r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All = 0;
1656 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_gs_stack_entries,
1657 NUM_GS_STACK_ENTRIES_shift, NUM_GS_STACK_ENTRIES_mask);
1658 SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_es_stack_entries,
1659 NUM_ES_STACK_ENTRIES_shift, NUM_ES_STACK_ENTRIES_mask);
1660
1661 }
1662
1663 /**
1664 * Calculate initial hardware state and register state functions.
1665 * Assumes that the command buffer and state atoms have been
1666 * initialized already.
1667 */
1668 void r700InitState(GLcontext * ctx) //-------------------
1669 {
1670 context_t *context = R700_CONTEXT(ctx);
1671 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1672
1673 radeon_firevertices(&context->radeon);
1674
1675 r700->TA_CNTL_AUX.u32All = 0;
1676 SETfield(r700->TA_CNTL_AUX.u32All, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask);
1677 r700->VC_ENHANCE.u32All = 0;
1678 r700->DB_WATERMARKS.u32All = 0;
1679 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_FREE_shift, DEPTH_FREE_mask);
1680 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_FLUSH_shift, DEPTH_FLUSH_mask);
1681 SETfield(r700->DB_WATERMARKS.u32All, 0, FORCE_SUMMARIZE_shift, FORCE_SUMMARIZE_mask);
1682 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_PENDING_FREE_shift, DEPTH_PENDING_FREE_mask);
1683 r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All = 0;
1684 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1685 SETfield(r700->TA_CNTL_AUX.u32All, 3, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1686 r700->DB_DEBUG.u32All = 0x82000000;
1687 SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1688 } else {
1689 SETfield(r700->TA_CNTL_AUX.u32All, 2, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
1690 SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
1691 SETbit(r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All, VS_PC_LIMIT_ENABLE_bit);
1692 }
1693
1694 /* Turn off vgt reuse */
1695 r700->VGT_REUSE_OFF.u32All = 0;
1696 SETbit(r700->VGT_REUSE_OFF.u32All, REUSE_OFF_bit);
1697
1698 /* Specify offsetting and clamp values for vertices */
1699 r700->VGT_MAX_VTX_INDX.u32All = 0xFFFFFF;
1700 r700->VGT_MIN_VTX_INDX.u32All = 0;
1701 r700->VGT_INDX_OFFSET.u32All = 0;
1702
1703 /* default shader connections. */
1704 r700->SPI_VS_OUT_ID_0.u32All = 0x03020100;
1705 r700->SPI_VS_OUT_ID_1.u32All = 0x07060504;
1706
1707 r700->SPI_THREAD_GROUPING.u32All = 0;
1708 if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
1709 SETfield(r700->SPI_THREAD_GROUPING.u32All, 1, PS_GROUPING_shift, PS_GROUPING_mask);
1710
1711 /* screen */
1712 r700->PA_SC_SCREEN_SCISSOR_TL.u32All = 0x0;
1713
1714 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All,
1715 ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->width,
1716 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask);
1717 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All,
1718 ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->height,
1719 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask);
1720
1721 /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
1722 r700->PA_SC_CLIPRECT_RULE.u32All = 0;
1723 SETfield(r700->PA_SC_CLIPRECT_RULE.u32All, CLIP_RULE_mask, CLIP_RULE_shift, CLIP_RULE_mask);
1724
1725 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1726 r700->PA_SC_EDGERULE.u32All = 0;
1727 else
1728 r700->PA_SC_EDGERULE.u32All = 0xAAAAAAAA;
1729
1730 if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1731 r700->PA_SC_MODE_CNTL.u32All = 0;
1732 SETbit(r700->PA_SC_MODE_CNTL.u32All, WALK_ORDER_ENABLE_bit);
1733 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1734 } else {
1735 r700->PA_SC_MODE_CNTL.u32All = 0x00500000;
1736 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_REZ_ENABLE_bit);
1737 SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
1738 }
1739
1740 /* Do scale XY and Z by 1/W0. */
1741 r700->bEnablePerspective = GL_TRUE;
1742 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
1743 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
1744 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
1745
1746 /* Enable viewport scaling for all three axis */
1747 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_SCALE_ENA_bit);
1748 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_OFFSET_ENA_bit);
1749 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_SCALE_ENA_bit);
1750 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_OFFSET_ENA_bit);
1751 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_SCALE_ENA_bit);
1752 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_OFFSET_ENA_bit);
1753
1754 /* GL uses last vtx for flat shading components */
1755 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
1756
1757 /* Set up vertex control */
1758 r700->PA_SU_VTX_CNTL.u32All = 0;
1759 CLEARfield(r700->PA_SU_VTX_CNTL.u32All, QUANT_MODE_mask);
1760 SETbit(r700->PA_SU_VTX_CNTL.u32All, PIX_CENTER_bit);
1761 SETfield(r700->PA_SU_VTX_CNTL.u32All, X_ROUND_TO_EVEN,
1762 PA_SU_VTX_CNTL__ROUND_MODE_shift, PA_SU_VTX_CNTL__ROUND_MODE_mask);
1763
1764 /* to 1.0 = no guard band */
1765 r700->PA_CL_GB_VERT_CLIP_ADJ.u32All = 0x3F800000; /* 1.0 */
1766 r700->PA_CL_GB_VERT_DISC_ADJ.u32All = 0x3F800000;
1767 r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All = 0x3F800000;
1768 r700->PA_CL_GB_HORZ_DISC_ADJ.u32All = 0x3F800000;
1769
1770 /* Enable all samples for multi-sample anti-aliasing */
1771 r700->PA_SC_AA_MASK.u32All = 0xFFFFFFFF;
1772 /* Turn off AA */
1773 r700->PA_SC_AA_CONFIG.u32All = 0;
1774
1775 r700->SX_MISC.u32All = 0;
1776
1777 r700InitSQConfig(ctx);
1778
1779 r700ColorMask(ctx,
1780 ctx->Color.ColorMask[RCOMP],
1781 ctx->Color.ColorMask[GCOMP],
1782 ctx->Color.ColorMask[BCOMP],
1783 ctx->Color.ColorMask[ACOMP]);
1784
1785 r700Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test);
1786 r700DepthMask(ctx, ctx->Depth.Mask);
1787 r700DepthFunc(ctx, ctx->Depth.Func);
1788 SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
1789
1790 /* stencil */
1791 r700Enable(ctx, GL_STENCIL_TEST, ctx->Stencil._Enabled);
1792 r700StencilMaskSeparate(ctx, 0, ctx->Stencil.WriteMask[0]);
1793 r700StencilFuncSeparate(ctx, 0, ctx->Stencil.Function[0],
1794 ctx->Stencil.Ref[0], ctx->Stencil.ValueMask[0]);
1795 r700StencilOpSeparate(ctx, 0, ctx->Stencil.FailFunc[0],
1796 ctx->Stencil.ZFailFunc[0],
1797 ctx->Stencil.ZPassFunc[0]);
1798
1799 r700UpdateCulling(ctx);
1800
1801 r700SetBlendState(ctx);
1802 r700SetLogicOpState(ctx);
1803
1804 r700AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef);
1805 r700Enable(ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled);
1806
1807 r700PointSize(ctx, 1.0);
1808
1809 CLEARfield(r700->PA_SU_POINT_MINMAX.u32All, MIN_SIZE_mask);
1810 SETfield(r700->PA_SU_POINT_MINMAX.u32All, 0x8000, MAX_SIZE_shift, MAX_SIZE_mask);
1811
1812 r700LineWidth(ctx, 1.0);
1813
1814 r700->PA_SC_LINE_CNTL.u32All = 0;
1815 CLEARbit(r700->PA_SC_LINE_CNTL.u32All, EXPAND_LINE_WIDTH_bit);
1816 SETbit(r700->PA_SC_LINE_CNTL.u32All, LAST_PIXEL_bit);
1817
1818 r700ShadeModel(ctx, ctx->Light.ShadeModel);
1819 r700PolygonMode(ctx, GL_FRONT, ctx->Polygon.FrontMode);
1820 r700PolygonMode(ctx, GL_BACK, ctx->Polygon.BackMode);
1821 r700PolygonOffset(ctx, ctx->Polygon.OffsetFactor,
1822 ctx->Polygon.OffsetUnits);
1823 r700Enable(ctx, GL_POLYGON_OFFSET_POINT, ctx->Polygon.OffsetPoint);
1824 r700Enable(ctx, GL_POLYGON_OFFSET_LINE, ctx->Polygon.OffsetLine);
1825 r700Enable(ctx, GL_POLYGON_OFFSET_FILL, ctx->Polygon.OffsetFill);
1826
1827 /* CB */
1828 r700BlendColor(ctx, ctx->Color.BlendColor);
1829
1830 r700->CB_CLEAR_RED_R6XX.f32All = 1.0; //r6xx only
1831 r700->CB_CLEAR_GREEN_R6XX.f32All = 0.0; //r6xx only
1832 r700->CB_CLEAR_BLUE_R6XX.f32All = 1.0; //r6xx only
1833 r700->CB_CLEAR_ALPHA_R6XX.f32All = 1.0; //r6xx only
1834 r700->CB_FOG_RED_R6XX.u32All = 0; //r6xx only
1835 r700->CB_FOG_GREEN_R6XX.u32All = 0; //r6xx only
1836 r700->CB_FOG_BLUE_R6XX.u32All = 0; //r6xx only
1837
1838 /* Disable color compares */
1839 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1840 CLRCMP_FCN_SRC_shift, CLRCMP_FCN_SRC_mask);
1841 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
1842 CLRCMP_FCN_DST_shift, CLRCMP_FCN_DST_mask);
1843 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_SEL_SRC,
1844 CLRCMP_FCN_SEL_shift, CLRCMP_FCN_SEL_mask);
1845
1846 /* Zero out source */
1847 r700->CB_CLRCMP_SRC.u32All = 0x00000000;
1848
1849 /* Put a compare color in for error checking */
1850 r700->CB_CLRCMP_DST.u32All = 0x000000FF;
1851
1852 /* Set up color compare mask */
1853 r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF;
1854
1855 context->radeon.hw.all_dirty = GL_TRUE;
1856
1857 }
1858
1859 void r700InitStateFuncs(struct dd_function_table *functions) //-----------------
1860 {
1861 functions->UpdateState = r700InvalidateState;
1862 functions->AlphaFunc = r700AlphaFunc;
1863 functions->BlendColor = r700BlendColor;
1864 functions->BlendEquationSeparate = r700BlendEquationSeparate;
1865 functions->BlendFuncSeparate = r700BlendFuncSeparate;
1866 functions->Enable = r700Enable;
1867 functions->ColorMask = r700ColorMask;
1868 functions->DepthFunc = r700DepthFunc;
1869 functions->DepthMask = r700DepthMask;
1870 functions->CullFace = r700CullFace;
1871 functions->Fogfv = r700Fogfv;
1872 functions->FrontFace = r700FrontFace;
1873 functions->ShadeModel = r700ShadeModel;
1874 functions->LogicOpcode = r700LogicOpcode;
1875
1876 /* ARB_point_parameters */
1877 functions->PointParameterfv = r700PointParameter;
1878
1879 /* Stencil related */
1880 functions->StencilFuncSeparate = r700StencilFuncSeparate;
1881 functions->StencilMaskSeparate = r700StencilMaskSeparate;
1882 functions->StencilOpSeparate = r700StencilOpSeparate;
1883
1884 /* Viewport related */
1885 functions->Viewport = r700Viewport;
1886 functions->DepthRange = r700DepthRange;
1887 functions->PointSize = r700PointSize;
1888 functions->LineWidth = r700LineWidth;
1889 functions->LineStipple = r700LineStipple;
1890
1891 functions->PolygonOffset = r700PolygonOffset;
1892 functions->PolygonMode = r700PolygonMode;
1893
1894 functions->RenderMode = r700RenderMode;
1895
1896 functions->ClipPlane = r700ClipPlane;
1897
1898 functions->Scissor = radeonScissor;
1899
1900 functions->DrawBuffer = radeonDrawBuffer;
1901 functions->ReadBuffer = radeonReadBuffer;
1902
1903 }
1904