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Clean up scissor and viewport code
[mesa.git] / src / mesa / drivers / dri / r600 / r700_state.c
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #include "main/glheader.h"
28 #include "main/mtypes.h"
29 #include "main/state.h"
30 #include "main/imports.h"
31 #include "main/enums.h"
32 #include "main/macros.h"
33 #include "main/dd.h"
34 #include "main/simple_list.h"
35
36 #include "tnl/tnl.h"
37 #include "tnl/t_pipeline.h"
38 #include "tnl/t_vp_build.h"
39 #include "swrast/swrast.h"
40 #include "swrast_setup/swrast_setup.h"
41 #include "main/api_arrayelt.h"
42 #include "main/state.h"
43 #include "main/framebuffer.h"
44
45 #include "shader/prog_parameter.h"
46 #include "shader/prog_statevars.h"
47 #include "vbo/vbo.h"
48 #include "main/texformat.h"
49
50 #include "r600_context.h"
51
52 #include "r700_state.h"
53
54 #include "r700_fragprog.h"
55 #include "r700_vertprog.h"
56
57
58 void r700SetDefaultStates(context_t *context) //--------------------
59 {
60
61 }
62
63 void r700UpdateShaders (GLcontext * ctx) //----------------------------------
64 {
65 context_t *context = R700_CONTEXT(ctx);
66
67 GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
68 GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
69
70 struct r700_vertex_program *vp;
71 int i;
72
73 if (context->radeon.NewGLState)
74 {
75 context->radeon.NewGLState = 0;
76
77 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++)
78 {
79 /* mat states from state var not array for sw */
80 dummy_attrib[i].stride = 0;
81
82 temp_attrib[i] = TNL_CONTEXT(ctx)->vb.AttribPtr[i];
83 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = &(dummy_attrib[i]);
84 }
85
86 _tnl_UpdateFixedFunctionProgram(ctx);
87
88 for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++)
89 {
90 TNL_CONTEXT(ctx)->vb.AttribPtr[i] = temp_attrib[i];
91 }
92
93 r700SelectVertexShader(ctx);
94 vp = (struct r700_vertex_program *)ctx->VertexProgram._Current;
95
96 if (vp->translated == GL_FALSE)
97 {
98 // TODO
99 //fprintf(stderr, "Failing back to sw-tcl\n");
100 //hw_tcl_on = future_hw_tcl_on = 0;
101 //r300ResetHwState(rmesa);
102 //
103 r700UpdateStateParameters(ctx, _NEW_PROGRAM);
104 return;
105 }
106 }
107
108 r700UpdateStateParameters(ctx, _NEW_PROGRAM);
109 }
110
111 /*
112 * To correctly position primitives:
113 */
114 void r700UpdateViewportOffset(GLcontext * ctx) //------------------
115 {
116
117 //radeonUpdateScissor(ctx);
118
119 return;
120 }
121
122 /**
123 * Tell the card where to render (offset, pitch).
124 * Effected by glDrawBuffer, etc
125 */
126 void r700UpdateDrawBuffer(GLcontext * ctx) /* TODO */ //---------------------
127 {
128 #if 0 /* to be enabled */
129 context_t *context = R700_CONTEXT(ctx);
130
131 switch (ctx->DrawBuffer->_ColorDrawBufferIndexes[0])
132 {
133 case BUFFER_FRONT_LEFT:
134 context->target.rt = context->screen->frontBuffer;
135 break;
136 case BUFFER_BACK_LEFT:
137 context->target.rt = context->screen->backBuffer;
138 break;
139 default:
140 memset (&context->target.rt, sizeof(context->target.rt), 0);
141 }
142 #endif /* to be enabled */
143 }
144
145 static void r700FetchStateParameter(GLcontext * ctx,
146 const gl_state_index state[STATE_LENGTH],
147 GLfloat * value)
148 {
149 context_t *context = R700_CONTEXT(ctx);
150
151 /* TODO */
152 }
153
154 void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state) //--------------------
155 {
156 struct r700_fragment_program *fp;
157 struct gl_program_parameter_list *paramList;
158 GLuint i;
159
160 if (!(new_state & (_NEW_BUFFERS | _NEW_PROGRAM)))
161 return;
162
163 fp = (struct r700_fragment_program *)ctx->FragmentProgram._Current;
164 if (!fp)
165 {
166 return;
167 }
168
169 paramList = fp->mesa_program.Base.Parameters;
170
171 if (!paramList)
172 {
173 return;
174 }
175
176 for (i = 0; i < paramList->NumParameters; i++)
177 {
178 if (paramList->Parameters[i].Type == PROGRAM_STATE_VAR)
179 {
180 r700FetchStateParameter(ctx,
181 paramList->Parameters[i].
182 StateIndexes,
183 paramList->ParameterValues[i]);
184 }
185 }
186 }
187
188 /**
189 * Called by Mesa after an internal state update.
190 */
191 static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //-------------------
192 {
193 context_t *context = R700_CONTEXT(ctx);
194
195 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
196
197 _swrast_InvalidateState(ctx, new_state);
198 _swsetup_InvalidateState(ctx, new_state);
199 _vbo_InvalidateState(ctx, new_state);
200 _tnl_InvalidateState(ctx, new_state);
201 _ae_invalidate_state(ctx, new_state);
202
203 if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL))
204 {
205 _mesa_update_framebuffer(ctx);
206 /* this updates the DrawBuffer's Width/Height if it's a FBO */
207 _mesa_update_draw_buffer_bounds(ctx);
208
209 r700UpdateDrawBuffer(ctx);
210 }
211
212 r700UpdateStateParameters(ctx, new_state);
213
214 if(GL_TRUE == r700->bEnablePerspective)
215 {
216 /* Do scale XY and Z by 1/W0 for perspective correction on pos. For orthogonal case, set both to one. */
217 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
218 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
219
220 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
221
222 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
223 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
224 }
225 else
226 {
227 /* For orthogonal case. */
228 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
229 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
230
231 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
232
233 CLEARbit(r700->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
234 SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
235 }
236
237 context->radeon.NewGLState |= new_state;
238 }
239
240 static void r700SetDepthState(GLcontext * ctx)
241 {
242 context_t *context = R700_CONTEXT(ctx);
243
244 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
245
246 if (ctx->Depth.Test)
247 {
248 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
249 if (ctx->Depth.Mask)
250 {
251 SETbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
252 }
253 else
254 {
255 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
256 }
257
258 switch (ctx->Depth.Func)
259 {
260 case GL_NEVER:
261 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NEVER,
262 ZFUNC_shift, ZFUNC_mask);
263 break;
264 case GL_LESS:
265 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LESS,
266 ZFUNC_shift, ZFUNC_mask);
267 break;
268 case GL_EQUAL:
269 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_EQUAL,
270 ZFUNC_shift, ZFUNC_mask);
271 break;
272 case GL_LEQUAL:
273 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LEQUAL,
274 ZFUNC_shift, ZFUNC_mask);
275 break;
276 case GL_GREATER:
277 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GREATER,
278 ZFUNC_shift, ZFUNC_mask);
279 break;
280 case GL_NOTEQUAL:
281 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NOTEQUAL,
282 ZFUNC_shift, ZFUNC_mask);
283 break;
284 case GL_GEQUAL:
285 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GEQUAL,
286 ZFUNC_shift, ZFUNC_mask);
287 break;
288 case GL_ALWAYS:
289 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
290 ZFUNC_shift, ZFUNC_mask);
291 break;
292 default:
293 SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
294 ZFUNC_shift, ZFUNC_mask);
295 break;
296 }
297 }
298 else
299 {
300 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_ENABLE_bit);
301 CLEARbit(r700->DB_DEPTH_CONTROL.u32All, Z_WRITE_ENABLE_bit);
302 }
303 }
304
305 static void r700AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref) //---------------
306 {
307 }
308
309
310 static void r700BlendColor(GLcontext * ctx, const GLfloat cf[4]) //----------------
311 {
312 }
313
314 static void r700BlendEquationSeparate(GLcontext * ctx,
315 GLenum modeRGB, GLenum modeA) //-----------------
316 {
317 }
318
319 static void r700BlendFuncSeparate(GLcontext * ctx,
320 GLenum sfactorRGB, GLenum dfactorRGB,
321 GLenum sfactorA, GLenum dfactorA) //------------------------
322 {
323 }
324
325 static void r700UpdateCulling(GLcontext * ctx)
326 {
327 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
328
329 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
330 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
331 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
332
333 if (ctx->Polygon.CullFlag)
334 {
335 switch (ctx->Polygon.CullFaceMode)
336 {
337 case GL_FRONT:
338 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
339 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
340 break;
341 case GL_BACK:
342 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
343 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
344 break;
345 case GL_FRONT_AND_BACK:
346 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
347 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
348 break;
349 default:
350 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
351 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
352 break;
353 }
354 }
355
356 switch (ctx->Polygon.FrontFace)
357 {
358 case GL_CW:
359 SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
360 break;
361 case GL_CCW:
362 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
363 break;
364 default:
365 CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); /* default: ccw */
366 break;
367 }
368 }
369
370 static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //------------------
371 {
372 switch (cap)
373 {
374 case GL_TEXTURE_1D:
375 case GL_TEXTURE_2D:
376 case GL_TEXTURE_3D:
377 break;
378 case GL_FOG:
379 break;
380 case GL_ALPHA_TEST:
381 break;
382 case GL_COLOR_LOGIC_OP:
383 case GL_BLEND:
384 break;
385 case GL_CLIP_PLANE0:
386 case GL_CLIP_PLANE1:
387 case GL_CLIP_PLANE2:
388 case GL_CLIP_PLANE3:
389 case GL_CLIP_PLANE4:
390 case GL_CLIP_PLANE5:
391 break;
392 case GL_DEPTH_TEST:
393 r700SetDepthState(ctx);
394 break;
395 case GL_STENCIL_TEST:
396 break;
397 case GL_CULL_FACE:
398 r700UpdateCulling(ctx);
399 break;
400 case GL_POLYGON_OFFSET_POINT:
401 case GL_POLYGON_OFFSET_LINE:
402 case GL_POLYGON_OFFSET_FILL:
403 break;
404 default:
405 break;
406 }
407 }
408
409 /**
410 * Handle glColorMask()
411 */
412 static void r700ColorMask(GLcontext * ctx,
413 GLboolean r, GLboolean g, GLboolean b, GLboolean a) //------------------
414 {
415 }
416
417 /**
418 * Change the depth testing function.
419 *
420 * \note Mesa already filters redundant calls to this function.
421 */
422 static void r700DepthFunc(GLcontext * ctx, GLenum func) //--------------------
423 {
424 r700SetDepthState(ctx);
425 }
426
427 /**
428 * Enable/Disable depth writing.
429 *
430 * \note Mesa already filters redundant calls to this function.
431 */
432 static void r700DepthMask(GLcontext * ctx, GLboolean mask) //------------------
433 {
434 r700SetDepthState(ctx);
435 }
436
437 /**
438 * Change the culling mode.
439 *
440 * \note Mesa already filters redundant calls to this function.
441 */
442 static void r700CullFace(GLcontext * ctx, GLenum mode) //-----------------
443 {
444 r700UpdateCulling(ctx);
445 }
446
447 /* =============================================================
448 * Fog
449 */
450 static void r700Fogfv(GLcontext * ctx, GLenum pname, const GLfloat * param) //--------------
451 {
452 }
453
454 /**
455 * Change the polygon orientation.
456 *
457 * \note Mesa already filters redundant calls to this function.
458 */
459 static void r700FrontFace(GLcontext * ctx, GLenum mode) //------------------
460 {
461 r700UpdateCulling(ctx);
462 }
463
464 static void r700ShadeModel(GLcontext * ctx, GLenum mode) //--------------------
465 {
466 }
467
468 static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * param) //---------------
469 {
470 }
471
472 static void r700StencilFuncSeparate(GLcontext * ctx, GLenum face,
473 GLenum func, GLint ref, GLuint mask) //---------------------
474 {
475 }
476
477
478 static void r700StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) //--------------
479 {
480 }
481
482 static void r700StencilOpSeparate(GLcontext * ctx, GLenum face,
483 GLenum fail, GLenum zfail, GLenum zpass) //--------------------
484 {
485 }
486
487 static void r700UpdateWindow(GLcontext * ctx) //--------------------
488 {
489
490 context_t *context = R700_CONTEXT(ctx);
491 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
492 __DRIdrawablePrivate *dPriv = context->radeon.dri.drawable;
493 GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
494 GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
495 const GLfloat *v = ctx->Viewport._WindowMap.m;
496 const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
497 const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
498 GLfloat y_scale, y_bias;
499
500 if (render_to_fbo) {
501 y_scale = 1.0;
502 y_bias = 0;
503 } else {
504 y_scale = -1.0;
505 y_bias = yoffset;
506 }
507
508 GLfloat sx = v[MAT_SX];
509 GLfloat tx = v[MAT_TX] + xoffset;
510 GLfloat sy = v[MAT_SY] * y_scale;
511 GLfloat ty = (v[MAT_TY] * y_scale) + y_bias;
512 GLfloat sz = v[MAT_SZ] * depthScale;
513 GLfloat tz = v[MAT_TZ] * depthScale;
514
515 /* TODO : Need DMA flush as well. */
516
517 r700->PA_CL_VPORT_XSCALE.u32All = *((unsigned int*)(&sx));
518 r700->PA_CL_VPORT_XOFFSET.u32All = *((unsigned int*)(&tx));
519
520 r700->PA_CL_VPORT_YSCALE.u32All = *((unsigned int*)(&sy));
521 r700->PA_CL_VPORT_YOFFSET.u32All = *((unsigned int*)(&ty));
522
523 r700->PA_CL_VPORT_ZSCALE.u32All = *((unsigned int*)(&sz));
524 r700->PA_CL_VPORT_ZOFFSET.u32All = *((unsigned int*)(&tz));
525 }
526
527
528 static void r700Viewport(GLcontext * ctx,
529 GLint x,
530 GLint y,
531 GLsizei width,
532 GLsizei height) //--------------------
533 {
534 r700UpdateWindow(ctx);
535
536 radeon_viewport(ctx, x, y, width, height);
537 }
538
539 static void r700DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) //-------------
540 {
541 r700UpdateWindow(ctx);
542 }
543
544 static void r700PointSize(GLcontext * ctx, GLfloat size) //-------------------
545 {
546 }
547
548 static void r700LineWidth(GLcontext * ctx, GLfloat widthf) //---------------
549 {
550 }
551
552 static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) //--------------
553 {
554 }
555
556
557 static void r700PolygonMode(GLcontext * ctx, GLenum face, GLenum mode) //------------------
558 {
559 }
560
561 static void r700RenderMode(GLcontext * ctx, GLenum mode) //---------------------
562 {
563 }
564
565 static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq ) //-----------------
566 {
567 }
568
569 void r700SetScissor(context_t *context) //---------------
570 {
571 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
572 unsigned x1, y1, x2, y2;
573 struct radeon_renderbuffer *rrb;
574
575 rrb = radeon_get_colorbuffer(&context->radeon);
576 if (!rrb || !rrb->bo) {
577 fprintf(stderr, "no rrb\n");
578 return;
579 }
580 if (context->radeon.state.scissor.enabled) {
581 x1 = context->radeon.state.scissor.rect.x1;
582 y1 = context->radeon.state.scissor.rect.y1;
583 x2 = context->radeon.state.scissor.rect.x2 - 1;
584 y2 = context->radeon.state.scissor.rect.y2 - 1;
585 } else {
586 x1 = 0;
587 y1 = 0;
588 x2 = rrb->width - 1;
589 y2 = rrb->height - 1;
590 }
591
592 /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
593 r700->PA_SC_CLIPRECT_RULE.u32All = 0x0000FFFF;
594
595 /* window */
596 SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
597 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, x1,
598 PA_SC_WINDOW_SCISSOR_TL__TL_X_shift, PA_SC_WINDOW_SCISSOR_TL__TL_X_mask);
599 SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, y1,
600 PA_SC_WINDOW_SCISSOR_TL__TL_Y_shift, PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask);
601
602 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, x2,
603 PA_SC_WINDOW_SCISSOR_BR__BR_X_shift, PA_SC_WINDOW_SCISSOR_BR__BR_X_mask);
604 SETfield(r700->PA_SC_WINDOW_SCISSOR_BR.u32All, y2,
605 PA_SC_WINDOW_SCISSOR_BR__BR_Y_shift, PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask);
606
607
608 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, x1,
609 PA_SC_CLIPRECT_0_TL__TL_X_shift, PA_SC_CLIPRECT_0_TL__TL_X_mask);
610 SETfield(r700->PA_SC_CLIPRECT_0_TL.u32All, y1,
611 PA_SC_CLIPRECT_0_TL__TL_Y_shift, PA_SC_CLIPRECT_0_TL__TL_Y_mask);
612 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, x2,
613 PA_SC_CLIPRECT_0_BR__BR_X_shift, PA_SC_CLIPRECT_0_BR__BR_X_mask);
614 SETfield(r700->PA_SC_CLIPRECT_0_BR.u32All, y2,
615 PA_SC_CLIPRECT_0_BR__BR_Y_shift, PA_SC_CLIPRECT_0_BR__BR_Y_mask);
616
617 r700->PA_SC_CLIPRECT_1_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
618 r700->PA_SC_CLIPRECT_1_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
619 r700->PA_SC_CLIPRECT_2_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
620 r700->PA_SC_CLIPRECT_2_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
621 r700->PA_SC_CLIPRECT_3_TL.u32All = r700->PA_SC_CLIPRECT_0_TL.u32All;
622 r700->PA_SC_CLIPRECT_3_BR.u32All = r700->PA_SC_CLIPRECT_0_BR.u32All;
623
624 /* more....2d clip */
625 SETbit(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
626 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, x1,
627 PA_SC_GENERIC_SCISSOR_TL__TL_X_shift, PA_SC_GENERIC_SCISSOR_TL__TL_X_mask);
628 SETfield(r700->PA_SC_GENERIC_SCISSOR_TL.u32All, y1,
629 PA_SC_GENERIC_SCISSOR_TL__TL_Y_shift, PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask);
630 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, x2,
631 PA_SC_GENERIC_SCISSOR_BR__BR_X_shift, PA_SC_GENERIC_SCISSOR_BR__BR_X_mask);
632 SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, y2,
633 PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask);
634
635 SETbit(r700->PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
636 SETfield(r700->PA_SC_VPORT_SCISSOR_0_TL.u32All, x1,
637 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask);
638 SETfield(r700->PA_SC_VPORT_SCISSOR_0_TL.u32All, y1,
639 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask);
640 SETfield(r700->PA_SC_VPORT_SCISSOR_0_BR.u32All, x2,
641 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask);
642 SETfield(r700->PA_SC_VPORT_SCISSOR_0_BR.u32All, y2,
643 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask);
644
645 SETbit(r700->PA_SC_VPORT_SCISSOR_1_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
646 SETfield(r700->PA_SC_VPORT_SCISSOR_1_TL.u32All, x1,
647 PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask);
648 SETfield(r700->PA_SC_VPORT_SCISSOR_1_TL.u32All, y1,
649 PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask);
650 SETfield(r700->PA_SC_VPORT_SCISSOR_1_BR.u32All, x2,
651 PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask);
652 SETfield(r700->PA_SC_VPORT_SCISSOR_1_BR.u32All, y2,
653 PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask);
654 }
655
656 void r700SetRenderTarget(context_t *context)
657 {
658 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
659
660 struct radeon_renderbuffer *rrb;
661 unsigned int nPitchInPixel;
662
663 /* screen/window/view */
664 SETfield(r700->CB_TARGET_MASK.u32All, 0xF, TARGET0_ENABLE_shift, TARGET0_ENABLE_mask);
665 SETfield(r700->CB_SHADER_MASK.u32All, 0xF, OUTPUT0_ENABLE_shift, OUTPUT0_ENABLE_mask);
666
667 rrb = radeon_get_colorbuffer(&context->radeon);
668 if (!rrb || !rrb->bo) {
669 fprintf(stderr, "no rrb\n");
670 return;
671 }
672
673 /* color buffer */
674 r700->CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset;
675
676 nPitchInPixel = rrb->pitch/rrb->cpp;
677 SETfield(r700->CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1,
678 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
679 SETfield(r700->CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
680 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
681 r700->CB_COLOR0_BASE.u32All = 0;
682 SETfield(r700->CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
683 SETfield(r700->CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL,
684 CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
685 if(4 == rrb->cpp)
686 {
687 SETfield(r700->CB_COLOR0_INFO.u32All, COLOR_8_8_8_8,
688 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
689 SETfield(r700->CB_COLOR0_INFO.u32All, SWAP_ALT, COMP_SWAP_shift, COMP_SWAP_mask);
690 }
691 else
692 {
693 SETfield(r700->CB_COLOR0_INFO.u32All, COLOR_5_6_5,
694 CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
695 SETfield(r700->CB_COLOR0_INFO.u32All, SWAP_ALT_REV,
696 COMP_SWAP_shift, COMP_SWAP_mask);
697 }
698 SETbit(r700->CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
699 SETbit(r700->CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit);
700 SETfield(r700->CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
701
702 }
703
704 void r700SetDepthTarget(context_t *context)
705 {
706 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
707
708 struct radeon_renderbuffer *rrb;
709 unsigned int nPitchInPixel;
710
711 /* depth buf */
712 r700->DB_DEPTH_SIZE.u32All = 0;
713 r700->DB_DEPTH_BASE.u32All = 0;
714 r700->DB_DEPTH_INFO.u32All = 0;
715
716 r700->DB_DEPTH_CONTROL.u32All = 0;
717 r700->DB_DEPTH_CLEAR.u32All = 0x3F800000;
718 r700->DB_DEPTH_VIEW.u32All = 0;
719 r700->DB_RENDER_CONTROL.u32All = 0;
720 r700->DB_RENDER_OVERRIDE.u32All = 0;
721 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
722 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
723 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
724
725 rrb = radeon_get_depthbuffer(&context->radeon);
726 if (!rrb)
727 return;
728
729 nPitchInPixel = rrb->pitch/rrb->cpp;
730
731 SETfield(r700->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1,
732 PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
733 SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
734 SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */
735
736 if(4 == rrb->cpp)
737 {
738 switch (GL_CONTEXT(context)->Visual.depthBits)
739 {
740 case 16:
741 case 24:
742 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_8_24,
743 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
744 break;
745 default:
746 fprintf(stderr, "Error: Unsupported depth %d... exiting\n",
747 GL_CONTEXT(context)->Visual.depthBits);
748 _mesa_exit(-1);
749 }
750 }
751 else
752 {
753 SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16,
754 DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
755 }
756 SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_2D_TILED_THIN1,
757 DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask);
758 /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */
759 }
760
761 /**
762 * Calculate initial hardware state and register state functions.
763 * Assumes that the command buffer and state atoms have been
764 * initialized already.
765 */
766 void r700InitState(GLcontext * ctx) //-------------------
767 {
768 context_t *context = R700_CONTEXT(ctx);
769
770 R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
771
772 /* Turn off vgt reuse */
773 r700->VGT_REUSE_OFF.u32All = 0;
774 SETbit(r700->VGT_REUSE_OFF.u32All, REUSE_OFF_bit);
775
776 /* Specify offsetting and clamp values for vertices */
777 r700->VGT_MAX_VTX_INDX.u32All = 0xFFFFFF;
778 r700->VGT_MIN_VTX_INDX.u32All = 0;
779 r700->VGT_INDX_OFFSET.u32All = 0;
780
781 /* Specify the number of instances */
782 r700->VGT_DMA_NUM_INSTANCES.u32All = 1;
783
784 /* not alpha blend */
785 CLEARfield(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_FUNC_mask);
786 CLEARbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
787
788 /* defualt shader connections. */
789 r700->SPI_VS_OUT_ID_0.u32All = 0x03020100;
790 r700->SPI_VS_OUT_ID_1.u32All = 0x07060504;
791
792 r700->SPI_PS_INPUT_CNTL_0.u32All = 0x00000800;
793 r700->SPI_PS_INPUT_CNTL_1.u32All = 0x00000801;
794 r700->SPI_PS_INPUT_CNTL_2.u32All = 0x00000802;
795
796 SETfield(r700->CB_COLOR_CONTROL.u32All, 0xCC, ROP3_shift, ROP3_mask);
797 CLEARbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit);
798 CLEARfield(r700->CB_BLEND0_CONTROL.u32All, COLOR_SRCBLEND_mask); /* no dst blend */
799 CLEARfield(r700->CB_BLEND0_CONTROL.u32All, ALPHA_SRCBLEND_mask); /* no dst blend */
800
801 r700->DB_SHADER_CONTROL.u32All = 0;
802 SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
803
804 /* Set up the culling control register */
805 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
806 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
807 SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
808 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
809
810 /* screen */
811 r700->PA_SC_SCREEN_SCISSOR_TL.u32All = 0x0;
812
813 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All,
814 ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->width,
815 PA_SC_SCREEN_SCISSOR_BR__BR_X_shift, PA_SC_SCREEN_SCISSOR_BR__BR_X_mask);
816 SETfield(r700->PA_SC_SCREEN_SCISSOR_BR.u32All,
817 ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->height,
818 PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask);
819
820 /* Do scale XY and Z by 1/W0. */
821 r700->bEnablePerspective = GL_TRUE;
822 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
823 CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_Z_FMT_bit);
824 SETbit(r700->PA_CL_VTE_CNTL.u32All, VTX_W0_FMT_bit);
825
826 /* Enable viewport scaling for all three axis */
827 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_SCALE_ENA_bit);
828 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_X_OFFSET_ENA_bit);
829 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_SCALE_ENA_bit);
830 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Y_OFFSET_ENA_bit);
831 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_SCALE_ENA_bit);
832 SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_OFFSET_ENA_bit);
833
834 /* Set up point sizes and min/max values */
835 SETfield(r700->PA_SU_POINT_SIZE.u32All, 0x8,
836 PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask);
837 SETfield(r700->PA_SU_POINT_SIZE.u32All, 0x8,
838 PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask);
839 CLEARfield(r700->PA_SU_POINT_MINMAX.u32All, MIN_SIZE_mask);
840 SETfield(r700->PA_SU_POINT_MINMAX.u32All, 0x8000, MAX_SIZE_shift, MAX_SIZE_mask);
841
842 /* Set up line control */
843 SETfield(r700->PA_SU_LINE_CNTL.u32All, 0x8,
844 PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
845
846 r700->PA_SC_LINE_CNTL.u32All = 0;
847 CLEARbit(r700->PA_SC_LINE_CNTL.u32All, EXPAND_LINE_WIDTH_bit);
848 SETbit(r700->PA_SC_LINE_CNTL.u32All, LAST_PIXEL_bit);
849
850 /* Set up vertex control */
851 r700->PA_SU_VTX_CNTL.u32All = 0;
852 CLEARfield(r700->PA_SU_VTX_CNTL.u32All, QUANT_MODE_mask);
853 SETbit(r700->PA_SU_VTX_CNTL.u32All, PIX_CENTER_bit);
854 SETfield(r700->PA_SU_VTX_CNTL.u32All, X_ROUND_TO_EVEN,
855 PA_SU_VTX_CNTL__ROUND_MODE_shift, PA_SU_VTX_CNTL__ROUND_MODE_mask);
856
857 /* to 1.0 = no guard band */
858 r700->PA_CL_GB_VERT_CLIP_ADJ.u32All = 0x3F800000; /* 1.0 */
859 r700->PA_CL_GB_VERT_DISC_ADJ.u32All = 0x3F800000;
860 r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All = 0x3F800000;
861 r700->PA_CL_GB_HORZ_DISC_ADJ.u32All = 0x3F800000;
862
863 /* Disble color compares */
864 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
865 CLRCMP_FCN_SRC_shift, CLRCMP_FCN_SRC_mask);
866 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
867 CLRCMP_FCN_DST_shift, CLRCMP_FCN_DST_mask);
868 SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_SEL_SRC,
869 CLRCMP_FCN_SEL_shift, CLRCMP_FCN_SEL_mask);
870
871 /* Zero out source */
872 r700->CB_CLRCMP_SRC.u32All = 0x00000000;
873
874 /* Put a compare color in for error checking */
875 r700->CB_CLRCMP_DST.u32All = 0x000000FF;
876
877 /* Set up color compare mask */
878 r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF;
879
880 /* Enable all samples for multi-sample anti-aliasing */
881 r700->PA_SC_AA_MASK.u32All = 0xFFFFFFFF;
882 /* Turn off AA */
883 r700->PA_SC_AA_CONFIG.u32All = 0;
884
885 SETfield(r700->VGT_OUT_DEALLOC_CNTL.u32All, 16, DEALLOC_DIST_shift, DEALLOC_DIST_mask);
886 SETfield(r700->VGT_VERTEX_REUSE_BLOCK_CNTL.u32All, 14, VTX_REUSE_DEPTH_shift, VTX_REUSE_DEPTH_mask);
887
888 r700->SX_MISC.u32All = 0;
889
890 /* depth buf */
891 r700->DB_DEPTH_SIZE.u32All = 0;
892 r700->DB_DEPTH_BASE.u32All = 0;
893 r700->DB_DEPTH_INFO.u32All = 0;
894 r700->DB_DEPTH_CONTROL.u32All = 0;
895 r700->DB_DEPTH_CLEAR.u32All = 0x3F800000;
896 r700->DB_DEPTH_VIEW.u32All = 0;
897 r700->DB_RENDER_CONTROL.u32All = 0;
898 r700->DB_RENDER_OVERRIDE.u32All = 0;
899 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
900 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
901 SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
902
903 /* color buffer */
904 r700->CB_COLOR0_SIZE.u32All = 0;
905 r700->CB_COLOR0_BASE.u32All = 0;
906 r700->CB_COLOR0_INFO.u32All = 0;
907 SETbit(r700->CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
908 SETbit(r700->CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit);
909 SETfield(r700->CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
910 r700->CB_COLOR0_VIEW.u32All = 0;
911 r700->CB_COLOR0_TILE.u32All = 0;
912 r700->CB_COLOR0_FRAG.u32All = 0;
913 r700->CB_COLOR0_MASK.u32All = 0;
914
915 r700->PA_SC_VPORT_ZMAX_0.u32All = 0x3F800000;
916 }
917
918 void r700InitStateFuncs(struct dd_function_table *functions) //-----------------
919 {
920 functions->UpdateState = r700InvalidateState;
921 functions->AlphaFunc = r700AlphaFunc;
922 functions->BlendColor = r700BlendColor;
923 functions->BlendEquationSeparate = r700BlendEquationSeparate;
924 functions->BlendFuncSeparate = r700BlendFuncSeparate;
925 functions->Enable = r700Enable;
926 functions->ColorMask = r700ColorMask;
927 functions->DepthFunc = r700DepthFunc;
928 functions->DepthMask = r700DepthMask;
929 functions->CullFace = r700CullFace;
930 functions->Fogfv = r700Fogfv;
931 functions->FrontFace = r700FrontFace;
932 functions->ShadeModel = r700ShadeModel;
933
934 /* ARB_point_parameters */
935 functions->PointParameterfv = r700PointParameter;
936
937 /* Stencil related */
938 functions->StencilFuncSeparate = r700StencilFuncSeparate;
939 functions->StencilMaskSeparate = r700StencilMaskSeparate;
940 functions->StencilOpSeparate = r700StencilOpSeparate;
941
942 /* Viewport related */
943 functions->Viewport = r700Viewport;
944 functions->DepthRange = r700DepthRange;
945 functions->PointSize = r700PointSize;
946 functions->LineWidth = r700LineWidth;
947
948 functions->PolygonOffset = r700PolygonOffset;
949 functions->PolygonMode = r700PolygonMode;
950
951 functions->RenderMode = r700RenderMode;
952
953 functions->ClipPlane = r700ClipPlane;
954
955 functions->Scissor = radeonScissor;
956
957 functions->DrawBuffer = radeonDrawBuffer;
958 functions->ReadBuffer = radeonReadBuffer;
959
960 }
961