R6xx/R7xx: WIP r6xx-rewrite code
[mesa.git] / src / mesa / drivers / dri / r600 / r700_tex.h
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Authors:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #ifndef __r700_TEX_H__
28 #define __r700_TEX_H__
29
30 #include "texmem.h"
31
32 #include "r700_chip.h"
33
34 /* TODO : review this after texture load code. */
35 #define R700_BLIT_WIDTH_BYTES 1024
36 /* The BASE_ADDRESS and MIP_ADDRESS fields are 256-byte-aligned */
37 #define R700_TEXTURE_ALIGNMENT_MASK 0x255
38 /* Texel pitch is 8 alignment. */
39 #define R700_TEXEL_PITCH_ALIGNMENT_MASK 0x7
40
41 #define R700_MAX_TEXTURE_UNITS 8 /* TODO : should be 16, lets make it work, review later */
42
43 typedef struct r700_tex_obj r700TexObj, *r700TexObjPtr;
44
45 /* Texture object in locally shared texture space.
46 */
47 struct r700_tex_obj
48 {
49 driTextureObject base;
50
51 /* r300 tex obj */
52 GLuint bufAddr;
53 GLboolean image_override;
54 GLuint pitch;
55 GLuint filter;
56 GLuint filter_1;
57 GLuint pitch_reg;
58 GLuint size;
59 GLuint format;
60 GLuint offset;
61 GLuint unknown4;
62 GLuint unknown5;
63 GLboolean border_fallback;
64 GLuint tile_bits;
65
66 /* r700 texture states */
67 TEXTURE_STATE_STRUCT texture_state;
68 SAMPLER_STATE_STRUCT sampler_state;
69
70 GLuint texel_pitch[6][RADEON_MAX_TEXTURE_LEVELS];
71 GLuint level_offset[6][RADEON_MAX_TEXTURE_LEVELS];
72 GLuint byte_per_texel;
73 GLuint src_width_in_pexel[6][RADEON_MAX_TEXTURE_LEVELS];
74 GLuint src_hight_in_pexel[6][RADEON_MAX_TEXTURE_LEVELS];
75
76 GLuint my_dirty_images[6]; /* TODO : review */
77 };
78
79 extern void r700SetTexBuffer(__DRIcontext *pDRICtx, GLint target,
80 __DRIdrawable *dPriv);
81
82 extern void r700SetTexBuffer2(__DRIcontext *pDRICtx, GLint target,
83 GLint format, __DRIdrawable *dPriv);
84
85 extern void r700SetTexOffset(__DRIcontext *pDRICtx, GLint texname,
86 unsigned long long offset, GLint depth,
87 GLuint pitch);
88
89 extern GLuint r700GetTexObjSize(void);
90 extern void r700UpdateTextureState(context_t * context);
91
92 extern void r700SetTexOffset(__DRIcontext *pDRICtx,
93 GLint texname,
94 unsigned long long offset,
95 GLint depth,
96 GLuint pitch);
97
98 extern void r700DestroyTexObj(context_t rmesa, r700TexObjPtr t);
99
100 extern GLboolean r700ValidateBuffers(GLcontext * ctx);
101
102 extern void r700InitTextureFuncs(struct dd_function_table *functions);
103
104 #endif /* __r700_TEX_H__ */