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Merge branch 'mesa_7_6_branch'
[mesa.git] / src / mesa / drivers / dri / r600 / sq_micro_reg.h
1 /*
2 * Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 /*
23 * Contacts:
24 * Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
25 */
26
27 #if !defined (_SQ_MICRO_REG_H)
28 #define _SQ_MICRO_REG_H
29
30 #if defined(LITTLEENDIAN_CPU)
31 #elif defined(BIGENDIAN_CPU)
32 #else
33 #error "BIGENDIAN_CPU or LITTLEENDIAN_CPU must be defined"
34 #endif
35
36 /*
37 * SQ_ALU_SRC_GPR_BASE value
38 */
39
40 #define SQ_ALU_SRC_GPR_BASE 0x00000000
41
42 /*
43 * SQ_ALU_SRC_GPR_SIZE value
44 */
45
46 #define SQ_ALU_SRC_GPR_SIZE 0x00000080
47
48 /*
49 * SQ_ALU_SRC_KCACHE0_BASE value
50 */
51
52 #define SQ_ALU_SRC_KCACHE0_BASE 0x00000080
53
54 /*
55 * SQ_ALU_SRC_KCACHE0_SIZE value
56 */
57
58 #define SQ_ALU_SRC_KCACHE0_SIZE 0x00000020
59
60 /*
61 * SQ_ALU_SRC_KCACHE1_BASE value
62 */
63
64 #define SQ_ALU_SRC_KCACHE1_BASE 0x000000a0
65
66 /*
67 * SQ_ALU_SRC_KCACHE1_SIZE value
68 */
69
70 #define SQ_ALU_SRC_KCACHE1_SIZE 0x00000020
71
72 /*
73 * SQ_ALU_SRC_CFILE_BASE value
74 */
75
76 #define SQ_ALU_SRC_CFILE_BASE 0x00000100
77
78 /*
79 * SQ_ALU_SRC_CFILE_SIZE value
80 */
81
82 #define SQ_ALU_SRC_CFILE_SIZE 0x00000100
83
84 /*
85 * SQ_SP_OP_REDUC_BEGIN value
86 */
87
88 #define SQ_SP_OP_REDUC_BEGIN 0x00000050
89
90 /*
91 * SQ_SP_OP_REDUC_END value
92 */
93
94 #define SQ_SP_OP_REDUC_END 0x00000053
95
96 /*
97 * SQ_SP_OP_TRANS_BEGIN value
98 */
99
100 #define SQ_SP_OP_TRANS_BEGIN 0x00000060
101
102 /*
103 * SQ_SP_OP_TRANS_END value
104 */
105
106 #define SQ_SP_OP_TRANS_END 0x0000007f
107
108 /*
109 * SQ_CF_WORD0 struct
110 */
111
112 #define SQ_CF_WORD0_ADDR_SIZE 32
113
114 #define SQ_CF_WORD0_ADDR_SHIFT 0
115
116 #define SQ_CF_WORD0_ADDR_MASK 0xffffffff
117
118 #define SQ_CF_WORD0_MASK \
119 (SQ_CF_WORD0_ADDR_MASK)
120
121 #define SQ_CF_WORD0_DEFAULT 0xcdcdcdcd
122
123 #define SQ_CF_WORD0_GET_ADDR(sq_cf_word0) \
124 ((sq_cf_word0 & SQ_CF_WORD0_ADDR_MASK) >> SQ_CF_WORD0_ADDR_SHIFT)
125
126 #define SQ_CF_WORD0_SET_ADDR(sq_cf_word0_reg, addr) \
127 sq_cf_word0_reg = (sq_cf_word0_reg & ~SQ_CF_WORD0_ADDR_MASK) | (addr << SQ_CF_WORD0_ADDR_SHIFT)
128
129 #if defined(LITTLEENDIAN_CPU)
130
131 typedef struct _sq_cf_word0_t {
132 unsigned int addr : SQ_CF_WORD0_ADDR_SIZE;
133 } sq_cf_word0_t;
134
135 #elif defined(BIGENDIAN_CPU)
136
137 typedef struct _sq_cf_word0_t {
138 unsigned int addr : SQ_CF_WORD0_ADDR_SIZE;
139 } sq_cf_word0_t;
140
141 #endif
142
143 typedef union {
144 unsigned int val : 32;
145 sq_cf_word0_t f;
146 } sq_cf_word0_u;
147
148
149 /*
150 * SQ_CF_WORD1 struct
151 */
152
153 #define SQ_CF_WORD1_POP_COUNT_SIZE 3
154 #define SQ_CF_WORD1_CF_CONST_SIZE 5
155 #define SQ_CF_WORD1_COND_SIZE 2
156 #define SQ_CF_WORD1_COUNT_SIZE 3
157 #define SQ_CF_WORD1_CALL_COUNT_SIZE 6
158 #define SQ_CF_WORD1_COUNT_3_SIZE 1
159 #define SQ_CF_WORD1_END_OF_PROGRAM_SIZE 1
160 #define SQ_CF_WORD1_VALID_PIXEL_MODE_SIZE 1
161 #define SQ_CF_WORD1_CF_INST_SIZE 7
162 #define SQ_CF_WORD1_WHOLE_QUAD_MODE_SIZE 1
163 #define SQ_CF_WORD1_BARRIER_SIZE 1
164
165 #define SQ_CF_WORD1_POP_COUNT_SHIFT 0
166 #define SQ_CF_WORD1_CF_CONST_SHIFT 3
167 #define SQ_CF_WORD1_COND_SHIFT 8
168 #define SQ_CF_WORD1_COUNT_SHIFT 10
169 #define SQ_CF_WORD1_CALL_COUNT_SHIFT 13
170 #define SQ_CF_WORD1_COUNT_3_SHIFT 19
171 #define SQ_CF_WORD1_END_OF_PROGRAM_SHIFT 21
172 #define SQ_CF_WORD1_VALID_PIXEL_MODE_SHIFT 22
173 #define SQ_CF_WORD1_CF_INST_SHIFT 23
174 #define SQ_CF_WORD1_WHOLE_QUAD_MODE_SHIFT 30
175 #define SQ_CF_WORD1_BARRIER_SHIFT 31
176
177 #define SQ_CF_WORD1_POP_COUNT_MASK 0x00000007
178 #define SQ_CF_WORD1_CF_CONST_MASK 0x000000f8
179 #define SQ_CF_WORD1_COND_MASK 0x00000300
180 #define SQ_CF_WORD1_COUNT_MASK 0x00001c00
181 #define SQ_CF_WORD1_CALL_COUNT_MASK 0x0007e000
182 #define SQ_CF_WORD1_COUNT_3_MASK 0x00080000
183 #define SQ_CF_WORD1_END_OF_PROGRAM_MASK 0x00200000
184 #define SQ_CF_WORD1_VALID_PIXEL_MODE_MASK 0x00400000
185 #define SQ_CF_WORD1_CF_INST_MASK 0x3f800000
186 #define SQ_CF_WORD1_WHOLE_QUAD_MODE_MASK 0x40000000
187 #define SQ_CF_WORD1_BARRIER_MASK 0x80000000
188
189 #define SQ_CF_WORD1_MASK \
190 (SQ_CF_WORD1_POP_COUNT_MASK | \
191 SQ_CF_WORD1_CF_CONST_MASK | \
192 SQ_CF_WORD1_COND_MASK | \
193 SQ_CF_WORD1_COUNT_MASK | \
194 SQ_CF_WORD1_CALL_COUNT_MASK | \
195 SQ_CF_WORD1_COUNT_3_MASK | \
196 SQ_CF_WORD1_END_OF_PROGRAM_MASK | \
197 SQ_CF_WORD1_VALID_PIXEL_MODE_MASK | \
198 SQ_CF_WORD1_CF_INST_MASK | \
199 SQ_CF_WORD1_WHOLE_QUAD_MODE_MASK | \
200 SQ_CF_WORD1_BARRIER_MASK)
201
202 #define SQ_CF_WORD1_DEFAULT 0xcdcdcdcd
203
204 #define SQ_CF_WORD1_GET_POP_COUNT(sq_cf_word1) \
205 ((sq_cf_word1 & SQ_CF_WORD1_POP_COUNT_MASK) >> SQ_CF_WORD1_POP_COUNT_SHIFT)
206 #define SQ_CF_WORD1_GET_CF_CONST(sq_cf_word1) \
207 ((sq_cf_word1 & SQ_CF_WORD1_CF_CONST_MASK) >> SQ_CF_WORD1_CF_CONST_SHIFT)
208 #define SQ_CF_WORD1_GET_COND(sq_cf_word1) \
209 ((sq_cf_word1 & SQ_CF_WORD1_COND_MASK) >> SQ_CF_WORD1_COND_SHIFT)
210 #define SQ_CF_WORD1_GET_COUNT(sq_cf_word1) \
211 ((sq_cf_word1 & SQ_CF_WORD1_COUNT_MASK) >> SQ_CF_WORD1_COUNT_SHIFT)
212 #define SQ_CF_WORD1_GET_CALL_COUNT(sq_cf_word1) \
213 ((sq_cf_word1 & SQ_CF_WORD1_CALL_COUNT_MASK) >> SQ_CF_WORD1_CALL_COUNT_SHIFT)
214 #define SQ_CF_WORD1_GET_COUNT_3(sq_cf_word1) \
215 ((sq_cf_word1 & SQ_CF_WORD1_COUNT_3_MASK) >> SQ_CF_WORD1_COUNT_3_SHIFT)
216 #define SQ_CF_WORD1_GET_END_OF_PROGRAM(sq_cf_word1) \
217 ((sq_cf_word1 & SQ_CF_WORD1_END_OF_PROGRAM_MASK) >> SQ_CF_WORD1_END_OF_PROGRAM_SHIFT)
218 #define SQ_CF_WORD1_GET_VALID_PIXEL_MODE(sq_cf_word1) \
219 ((sq_cf_word1 & SQ_CF_WORD1_VALID_PIXEL_MODE_MASK) >> SQ_CF_WORD1_VALID_PIXEL_MODE_SHIFT)
220 #define SQ_CF_WORD1_GET_CF_INST(sq_cf_word1) \
221 ((sq_cf_word1 & SQ_CF_WORD1_CF_INST_MASK) >> SQ_CF_WORD1_CF_INST_SHIFT)
222 #define SQ_CF_WORD1_GET_WHOLE_QUAD_MODE(sq_cf_word1) \
223 ((sq_cf_word1 & SQ_CF_WORD1_WHOLE_QUAD_MODE_MASK) >> SQ_CF_WORD1_WHOLE_QUAD_MODE_SHIFT)
224 #define SQ_CF_WORD1_GET_BARRIER(sq_cf_word1) \
225 ((sq_cf_word1 & SQ_CF_WORD1_BARRIER_MASK) >> SQ_CF_WORD1_BARRIER_SHIFT)
226
227 #define SQ_CF_WORD1_SET_POP_COUNT(sq_cf_word1_reg, pop_count) \
228 sq_cf_word1_reg = (sq_cf_word1_reg & ~SQ_CF_WORD1_POP_COUNT_MASK) | (pop_count << SQ_CF_WORD1_POP_COUNT_SHIFT)
229 #define SQ_CF_WORD1_SET_CF_CONST(sq_cf_word1_reg, cf_const) \
230 sq_cf_word1_reg = (sq_cf_word1_reg & ~SQ_CF_WORD1_CF_CONST_MASK) | (cf_const << SQ_CF_WORD1_CF_CONST_SHIFT)
231 #define SQ_CF_WORD1_SET_COND(sq_cf_word1_reg, cond) \
232 sq_cf_word1_reg = (sq_cf_word1_reg & ~SQ_CF_WORD1_COND_MASK) | (cond << SQ_CF_WORD1_COND_SHIFT)
233 #define SQ_CF_WORD1_SET_COUNT(sq_cf_word1_reg, count) \
234 sq_cf_word1_reg = (sq_cf_word1_reg & ~SQ_CF_WORD1_COUNT_MASK) | (count << SQ_CF_WORD1_COUNT_SHIFT)
235 #define SQ_CF_WORD1_SET_CALL_COUNT(sq_cf_word1_reg, call_count) \
236 sq_cf_word1_reg = (sq_cf_word1_reg & ~SQ_CF_WORD1_CALL_COUNT_MASK) | (call_count << SQ_CF_WORD1_CALL_COUNT_SHIFT)
237 #define SQ_CF_WORD1_SET_COUNT_3(sq_cf_word1_reg, count_3) \
238 sq_cf_word1_reg = (sq_cf_word1_reg & ~SQ_CF_WORD1_COUNT_3_MASK) | (count_3 << SQ_CF_WORD1_COUNT_3_SHIFT)
239 #define SQ_CF_WORD1_SET_END_OF_PROGRAM(sq_cf_word1_reg, end_of_program) \
240 sq_cf_word1_reg = (sq_cf_word1_reg & ~SQ_CF_WORD1_END_OF_PROGRAM_MASK) | (end_of_program << SQ_CF_WORD1_END_OF_PROGRAM_SHIFT)
241 #define SQ_CF_WORD1_SET_VALID_PIXEL_MODE(sq_cf_word1_reg, valid_pixel_mode) \
242 sq_cf_word1_reg = (sq_cf_word1_reg & ~SQ_CF_WORD1_VALID_PIXEL_MODE_MASK) | (valid_pixel_mode << SQ_CF_WORD1_VALID_PIXEL_MODE_SHIFT)
243 #define SQ_CF_WORD1_SET_CF_INST(sq_cf_word1_reg, cf_inst) \
244 sq_cf_word1_reg = (sq_cf_word1_reg & ~SQ_CF_WORD1_CF_INST_MASK) | (cf_inst << SQ_CF_WORD1_CF_INST_SHIFT)
245 #define SQ_CF_WORD1_SET_WHOLE_QUAD_MODE(sq_cf_word1_reg, whole_quad_mode) \
246 sq_cf_word1_reg = (sq_cf_word1_reg & ~SQ_CF_WORD1_WHOLE_QUAD_MODE_MASK) | (whole_quad_mode << SQ_CF_WORD1_WHOLE_QUAD_MODE_SHIFT)
247 #define SQ_CF_WORD1_SET_BARRIER(sq_cf_word1_reg, barrier) \
248 sq_cf_word1_reg = (sq_cf_word1_reg & ~SQ_CF_WORD1_BARRIER_MASK) | (barrier << SQ_CF_WORD1_BARRIER_SHIFT)
249
250 #if defined(LITTLEENDIAN_CPU)
251
252 typedef struct _sq_cf_word1_t {
253 unsigned int pop_count : SQ_CF_WORD1_POP_COUNT_SIZE;
254 unsigned int cf_const : SQ_CF_WORD1_CF_CONST_SIZE;
255 unsigned int cond : SQ_CF_WORD1_COND_SIZE;
256 unsigned int count : SQ_CF_WORD1_COUNT_SIZE;
257 unsigned int call_count : SQ_CF_WORD1_CALL_COUNT_SIZE;
258 unsigned int count_3 : SQ_CF_WORD1_COUNT_3_SIZE;
259 unsigned int : 1;
260 unsigned int end_of_program : SQ_CF_WORD1_END_OF_PROGRAM_SIZE;
261 unsigned int valid_pixel_mode : SQ_CF_WORD1_VALID_PIXEL_MODE_SIZE;
262 unsigned int cf_inst : SQ_CF_WORD1_CF_INST_SIZE;
263 unsigned int whole_quad_mode : SQ_CF_WORD1_WHOLE_QUAD_MODE_SIZE;
264 unsigned int barrier : SQ_CF_WORD1_BARRIER_SIZE;
265 } sq_cf_word1_t;
266
267 #elif defined(BIGENDIAN_CPU)
268
269 typedef struct _sq_cf_word1_t {
270 unsigned int barrier : SQ_CF_WORD1_BARRIER_SIZE;
271 unsigned int whole_quad_mode : SQ_CF_WORD1_WHOLE_QUAD_MODE_SIZE;
272 unsigned int cf_inst : SQ_CF_WORD1_CF_INST_SIZE;
273 unsigned int valid_pixel_mode : SQ_CF_WORD1_VALID_PIXEL_MODE_SIZE;
274 unsigned int end_of_program : SQ_CF_WORD1_END_OF_PROGRAM_SIZE;
275 unsigned int : 1;
276 unsigned int count_3 : SQ_CF_WORD1_COUNT_3_SIZE;
277 unsigned int call_count : SQ_CF_WORD1_CALL_COUNT_SIZE;
278 unsigned int count : SQ_CF_WORD1_COUNT_SIZE;
279 unsigned int cond : SQ_CF_WORD1_COND_SIZE;
280 unsigned int cf_const : SQ_CF_WORD1_CF_CONST_SIZE;
281 unsigned int pop_count : SQ_CF_WORD1_POP_COUNT_SIZE;
282 } sq_cf_word1_t;
283
284 #endif
285
286 typedef union {
287 unsigned int val : 32;
288 sq_cf_word1_t f;
289 } sq_cf_word1_u;
290
291
292 /*
293 * SQ_CF_ALU_WORD0 struct
294 */
295
296 #define SQ_CF_ALU_WORD0_ADDR_SIZE 22
297 #define SQ_CF_ALU_WORD0_KCACHE_BANK0_SIZE 4
298 #define SQ_CF_ALU_WORD0_KCACHE_BANK1_SIZE 4
299 #define SQ_CF_ALU_WORD0_KCACHE_MODE0_SIZE 2
300
301 #define SQ_CF_ALU_WORD0_ADDR_SHIFT 0
302 #define SQ_CF_ALU_WORD0_KCACHE_BANK0_SHIFT 22
303 #define SQ_CF_ALU_WORD0_KCACHE_BANK1_SHIFT 26
304 #define SQ_CF_ALU_WORD0_KCACHE_MODE0_SHIFT 30
305
306 #define SQ_CF_ALU_WORD0_ADDR_MASK 0x003fffff
307 #define SQ_CF_ALU_WORD0_KCACHE_BANK0_MASK 0x03c00000
308 #define SQ_CF_ALU_WORD0_KCACHE_BANK1_MASK 0x3c000000
309 #define SQ_CF_ALU_WORD0_KCACHE_MODE0_MASK 0xc0000000
310
311 #define SQ_CF_ALU_WORD0_MASK \
312 (SQ_CF_ALU_WORD0_ADDR_MASK | \
313 SQ_CF_ALU_WORD0_KCACHE_BANK0_MASK | \
314 SQ_CF_ALU_WORD0_KCACHE_BANK1_MASK | \
315 SQ_CF_ALU_WORD0_KCACHE_MODE0_MASK)
316
317 #define SQ_CF_ALU_WORD0_DEFAULT 0xcdcdcdcd
318
319 #define SQ_CF_ALU_WORD0_GET_ADDR(sq_cf_alu_word0) \
320 ((sq_cf_alu_word0 & SQ_CF_ALU_WORD0_ADDR_MASK) >> SQ_CF_ALU_WORD0_ADDR_SHIFT)
321 #define SQ_CF_ALU_WORD0_GET_KCACHE_BANK0(sq_cf_alu_word0) \
322 ((sq_cf_alu_word0 & SQ_CF_ALU_WORD0_KCACHE_BANK0_MASK) >> SQ_CF_ALU_WORD0_KCACHE_BANK0_SHIFT)
323 #define SQ_CF_ALU_WORD0_GET_KCACHE_BANK1(sq_cf_alu_word0) \
324 ((sq_cf_alu_word0 & SQ_CF_ALU_WORD0_KCACHE_BANK1_MASK) >> SQ_CF_ALU_WORD0_KCACHE_BANK1_SHIFT)
325 #define SQ_CF_ALU_WORD0_GET_KCACHE_MODE0(sq_cf_alu_word0) \
326 ((sq_cf_alu_word0 & SQ_CF_ALU_WORD0_KCACHE_MODE0_MASK) >> SQ_CF_ALU_WORD0_KCACHE_MODE0_SHIFT)
327
328 #define SQ_CF_ALU_WORD0_SET_ADDR(sq_cf_alu_word0_reg, addr) \
329 sq_cf_alu_word0_reg = (sq_cf_alu_word0_reg & ~SQ_CF_ALU_WORD0_ADDR_MASK) | (addr << SQ_CF_ALU_WORD0_ADDR_SHIFT)
330 #define SQ_CF_ALU_WORD0_SET_KCACHE_BANK0(sq_cf_alu_word0_reg, kcache_bank0) \
331 sq_cf_alu_word0_reg = (sq_cf_alu_word0_reg & ~SQ_CF_ALU_WORD0_KCACHE_BANK0_MASK) | (kcache_bank0 << SQ_CF_ALU_WORD0_KCACHE_BANK0_SHIFT)
332 #define SQ_CF_ALU_WORD0_SET_KCACHE_BANK1(sq_cf_alu_word0_reg, kcache_bank1) \
333 sq_cf_alu_word0_reg = (sq_cf_alu_word0_reg & ~SQ_CF_ALU_WORD0_KCACHE_BANK1_MASK) | (kcache_bank1 << SQ_CF_ALU_WORD0_KCACHE_BANK1_SHIFT)
334 #define SQ_CF_ALU_WORD0_SET_KCACHE_MODE0(sq_cf_alu_word0_reg, kcache_mode0) \
335 sq_cf_alu_word0_reg = (sq_cf_alu_word0_reg & ~SQ_CF_ALU_WORD0_KCACHE_MODE0_MASK) | (kcache_mode0 << SQ_CF_ALU_WORD0_KCACHE_MODE0_SHIFT)
336
337 #if defined(LITTLEENDIAN_CPU)
338
339 typedef struct _sq_cf_alu_word0_t {
340 unsigned int addr : SQ_CF_ALU_WORD0_ADDR_SIZE;
341 unsigned int kcache_bank0 : SQ_CF_ALU_WORD0_KCACHE_BANK0_SIZE;
342 unsigned int kcache_bank1 : SQ_CF_ALU_WORD0_KCACHE_BANK1_SIZE;
343 unsigned int kcache_mode0 : SQ_CF_ALU_WORD0_KCACHE_MODE0_SIZE;
344 } sq_cf_alu_word0_t;
345
346 #elif defined(BIGENDIAN_CPU)
347
348 typedef struct _sq_cf_alu_word0_t {
349 unsigned int kcache_mode0 : SQ_CF_ALU_WORD0_KCACHE_MODE0_SIZE;
350 unsigned int kcache_bank1 : SQ_CF_ALU_WORD0_KCACHE_BANK1_SIZE;
351 unsigned int kcache_bank0 : SQ_CF_ALU_WORD0_KCACHE_BANK0_SIZE;
352 unsigned int addr : SQ_CF_ALU_WORD0_ADDR_SIZE;
353 } sq_cf_alu_word0_t;
354
355 #endif
356
357 typedef union {
358 unsigned int val : 32;
359 sq_cf_alu_word0_t f;
360 } sq_cf_alu_word0_u;
361
362
363 /*
364 * SQ_CF_ALU_WORD1 struct
365 */
366
367 #define SQ_CF_ALU_WORD1_KCACHE_MODE1_SIZE 2
368 #define SQ_CF_ALU_WORD1_KCACHE_ADDR0_SIZE 8
369 #define SQ_CF_ALU_WORD1_KCACHE_ADDR1_SIZE 8
370 #define SQ_CF_ALU_WORD1_COUNT_SIZE 7
371 #define SQ_CF_ALU_WORD1_ALT_CONST_SIZE 1
372 #define SQ_CF_ALU_WORD1_CF_INST_SIZE 4
373 #define SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE_SIZE 1
374 #define SQ_CF_ALU_WORD1_BARRIER_SIZE 1
375
376 #define SQ_CF_ALU_WORD1_KCACHE_MODE1_SHIFT 0
377 #define SQ_CF_ALU_WORD1_KCACHE_ADDR0_SHIFT 2
378 #define SQ_CF_ALU_WORD1_KCACHE_ADDR1_SHIFT 10
379 #define SQ_CF_ALU_WORD1_COUNT_SHIFT 18
380 #define SQ_CF_ALU_WORD1_ALT_CONST_SHIFT 25
381 #define SQ_CF_ALU_WORD1_CF_INST_SHIFT 26
382 #define SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE_SHIFT 30
383 #define SQ_CF_ALU_WORD1_BARRIER_SHIFT 31
384
385 #define SQ_CF_ALU_WORD1_KCACHE_MODE1_MASK 0x00000003
386 #define SQ_CF_ALU_WORD1_KCACHE_ADDR0_MASK 0x000003fc
387 #define SQ_CF_ALU_WORD1_KCACHE_ADDR1_MASK 0x0003fc00
388 #define SQ_CF_ALU_WORD1_COUNT_MASK 0x01fc0000
389 #define SQ_CF_ALU_WORD1_ALT_CONST_MASK 0x02000000
390 #define SQ_CF_ALU_WORD1_CF_INST_MASK 0x3c000000
391 #define SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE_MASK 0x40000000
392 #define SQ_CF_ALU_WORD1_BARRIER_MASK 0x80000000
393
394 #define SQ_CF_ALU_WORD1_MASK \
395 (SQ_CF_ALU_WORD1_KCACHE_MODE1_MASK | \
396 SQ_CF_ALU_WORD1_KCACHE_ADDR0_MASK | \
397 SQ_CF_ALU_WORD1_KCACHE_ADDR1_MASK | \
398 SQ_CF_ALU_WORD1_COUNT_MASK | \
399 SQ_CF_ALU_WORD1_ALT_CONST_MASK | \
400 SQ_CF_ALU_WORD1_CF_INST_MASK | \
401 SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE_MASK | \
402 SQ_CF_ALU_WORD1_BARRIER_MASK)
403
404 #define SQ_CF_ALU_WORD1_DEFAULT 0xcdcdcdcd
405
406 #define SQ_CF_ALU_WORD1_GET_KCACHE_MODE1(sq_cf_alu_word1) \
407 ((sq_cf_alu_word1 & SQ_CF_ALU_WORD1_KCACHE_MODE1_MASK) >> SQ_CF_ALU_WORD1_KCACHE_MODE1_SHIFT)
408 #define SQ_CF_ALU_WORD1_GET_KCACHE_ADDR0(sq_cf_alu_word1) \
409 ((sq_cf_alu_word1 & SQ_CF_ALU_WORD1_KCACHE_ADDR0_MASK) >> SQ_CF_ALU_WORD1_KCACHE_ADDR0_SHIFT)
410 #define SQ_CF_ALU_WORD1_GET_KCACHE_ADDR1(sq_cf_alu_word1) \
411 ((sq_cf_alu_word1 & SQ_CF_ALU_WORD1_KCACHE_ADDR1_MASK) >> SQ_CF_ALU_WORD1_KCACHE_ADDR1_SHIFT)
412 #define SQ_CF_ALU_WORD1_GET_COUNT(sq_cf_alu_word1) \
413 ((sq_cf_alu_word1 & SQ_CF_ALU_WORD1_COUNT_MASK) >> SQ_CF_ALU_WORD1_COUNT_SHIFT)
414 #define SQ_CF_ALU_WORD1_GET_ALT_CONST(sq_cf_alu_word1) \
415 ((sq_cf_alu_word1 & SQ_CF_ALU_WORD1_ALT_CONST_MASK) >> SQ_CF_ALU_WORD1_ALT_CONST_SHIFT)
416 #define SQ_CF_ALU_WORD1_GET_CF_INST(sq_cf_alu_word1) \
417 ((sq_cf_alu_word1 & SQ_CF_ALU_WORD1_CF_INST_MASK) >> SQ_CF_ALU_WORD1_CF_INST_SHIFT)
418 #define SQ_CF_ALU_WORD1_GET_WHOLE_QUAD_MODE(sq_cf_alu_word1) \
419 ((sq_cf_alu_word1 & SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE_MASK) >> SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE_SHIFT)
420 #define SQ_CF_ALU_WORD1_GET_BARRIER(sq_cf_alu_word1) \
421 ((sq_cf_alu_word1 & SQ_CF_ALU_WORD1_BARRIER_MASK) >> SQ_CF_ALU_WORD1_BARRIER_SHIFT)
422
423 #define SQ_CF_ALU_WORD1_SET_KCACHE_MODE1(sq_cf_alu_word1_reg, kcache_mode1) \
424 sq_cf_alu_word1_reg = (sq_cf_alu_word1_reg & ~SQ_CF_ALU_WORD1_KCACHE_MODE1_MASK) | (kcache_mode1 << SQ_CF_ALU_WORD1_KCACHE_MODE1_SHIFT)
425 #define SQ_CF_ALU_WORD1_SET_KCACHE_ADDR0(sq_cf_alu_word1_reg, kcache_addr0) \
426 sq_cf_alu_word1_reg = (sq_cf_alu_word1_reg & ~SQ_CF_ALU_WORD1_KCACHE_ADDR0_MASK) | (kcache_addr0 << SQ_CF_ALU_WORD1_KCACHE_ADDR0_SHIFT)
427 #define SQ_CF_ALU_WORD1_SET_KCACHE_ADDR1(sq_cf_alu_word1_reg, kcache_addr1) \
428 sq_cf_alu_word1_reg = (sq_cf_alu_word1_reg & ~SQ_CF_ALU_WORD1_KCACHE_ADDR1_MASK) | (kcache_addr1 << SQ_CF_ALU_WORD1_KCACHE_ADDR1_SHIFT)
429 #define SQ_CF_ALU_WORD1_SET_COUNT(sq_cf_alu_word1_reg, count) \
430 sq_cf_alu_word1_reg = (sq_cf_alu_word1_reg & ~SQ_CF_ALU_WORD1_COUNT_MASK) | (count << SQ_CF_ALU_WORD1_COUNT_SHIFT)
431 #define SQ_CF_ALU_WORD1_SET_ALT_CONST(sq_cf_alu_word1_reg, alt_const) \
432 sq_cf_alu_word1_reg = (sq_cf_alu_word1_reg & ~SQ_CF_ALU_WORD1_ALT_CONST_MASK) | (alt_const << SQ_CF_ALU_WORD1_ALT_CONST_SHIFT)
433 #define SQ_CF_ALU_WORD1_SET_CF_INST(sq_cf_alu_word1_reg, cf_inst) \
434 sq_cf_alu_word1_reg = (sq_cf_alu_word1_reg & ~SQ_CF_ALU_WORD1_CF_INST_MASK) | (cf_inst << SQ_CF_ALU_WORD1_CF_INST_SHIFT)
435 #define SQ_CF_ALU_WORD1_SET_WHOLE_QUAD_MODE(sq_cf_alu_word1_reg, whole_quad_mode) \
436 sq_cf_alu_word1_reg = (sq_cf_alu_word1_reg & ~SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE_MASK) | (whole_quad_mode << SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE_SHIFT)
437 #define SQ_CF_ALU_WORD1_SET_BARRIER(sq_cf_alu_word1_reg, barrier) \
438 sq_cf_alu_word1_reg = (sq_cf_alu_word1_reg & ~SQ_CF_ALU_WORD1_BARRIER_MASK) | (barrier << SQ_CF_ALU_WORD1_BARRIER_SHIFT)
439
440 #if defined(LITTLEENDIAN_CPU)
441
442 typedef struct _sq_cf_alu_word1_t {
443 unsigned int kcache_mode1 : SQ_CF_ALU_WORD1_KCACHE_MODE1_SIZE;
444 unsigned int kcache_addr0 : SQ_CF_ALU_WORD1_KCACHE_ADDR0_SIZE;
445 unsigned int kcache_addr1 : SQ_CF_ALU_WORD1_KCACHE_ADDR1_SIZE;
446 unsigned int count : SQ_CF_ALU_WORD1_COUNT_SIZE;
447 unsigned int alt_const : SQ_CF_ALU_WORD1_ALT_CONST_SIZE;
448 unsigned int cf_inst : SQ_CF_ALU_WORD1_CF_INST_SIZE;
449 unsigned int whole_quad_mode : SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE_SIZE;
450 unsigned int barrier : SQ_CF_ALU_WORD1_BARRIER_SIZE;
451 } sq_cf_alu_word1_t;
452
453 #elif defined(BIGENDIAN_CPU)
454
455 typedef struct _sq_cf_alu_word1_t {
456 unsigned int barrier : SQ_CF_ALU_WORD1_BARRIER_SIZE;
457 unsigned int whole_quad_mode : SQ_CF_ALU_WORD1_WHOLE_QUAD_MODE_SIZE;
458 unsigned int cf_inst : SQ_CF_ALU_WORD1_CF_INST_SIZE;
459 unsigned int alt_const : SQ_CF_ALU_WORD1_ALT_CONST_SIZE;
460 unsigned int count : SQ_CF_ALU_WORD1_COUNT_SIZE;
461 unsigned int kcache_addr1 : SQ_CF_ALU_WORD1_KCACHE_ADDR1_SIZE;
462 unsigned int kcache_addr0 : SQ_CF_ALU_WORD1_KCACHE_ADDR0_SIZE;
463 unsigned int kcache_mode1 : SQ_CF_ALU_WORD1_KCACHE_MODE1_SIZE;
464 } sq_cf_alu_word1_t;
465
466 #endif
467
468 typedef union {
469 unsigned int val : 32;
470 sq_cf_alu_word1_t f;
471 } sq_cf_alu_word1_u;
472
473
474 /*
475 * SQ_CF_ALLOC_EXPORT_WORD0 struct
476 */
477
478 #define SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE_SIZE 13
479 #define SQ_CF_ALLOC_EXPORT_WORD0_TYPE_SIZE 2
480 #define SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR_SIZE 7
481 #define SQ_CF_ALLOC_EXPORT_WORD0_RW_REL_SIZE 1
482 #define SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR_SIZE 7
483 #define SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE_SIZE 2
484
485 #define SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE_SHIFT 0
486 #define SQ_CF_ALLOC_EXPORT_WORD0_TYPE_SHIFT 13
487 #define SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR_SHIFT 15
488 #define SQ_CF_ALLOC_EXPORT_WORD0_RW_REL_SHIFT 22
489 #define SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR_SHIFT 23
490 #define SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE_SHIFT 30
491
492 #define SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE_MASK 0x00001fff
493 #define SQ_CF_ALLOC_EXPORT_WORD0_TYPE_MASK 0x00006000
494 #define SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR_MASK 0x003f8000
495 #define SQ_CF_ALLOC_EXPORT_WORD0_RW_REL_MASK 0x00400000
496 #define SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR_MASK 0x3f800000
497 #define SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE_MASK 0xc0000000
498
499 #define SQ_CF_ALLOC_EXPORT_WORD0_MASK \
500 (SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE_MASK | \
501 SQ_CF_ALLOC_EXPORT_WORD0_TYPE_MASK | \
502 SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR_MASK | \
503 SQ_CF_ALLOC_EXPORT_WORD0_RW_REL_MASK | \
504 SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR_MASK | \
505 SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE_MASK)
506
507 #define SQ_CF_ALLOC_EXPORT_WORD0_DEFAULT 0xcdcdcdcd
508
509 #define SQ_CF_ALLOC_EXPORT_WORD0_GET_ARRAY_BASE(sq_cf_alloc_export_word0) \
510 ((sq_cf_alloc_export_word0 & SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE_MASK) >> SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE_SHIFT)
511 #define SQ_CF_ALLOC_EXPORT_WORD0_GET_TYPE(sq_cf_alloc_export_word0) \
512 ((sq_cf_alloc_export_word0 & SQ_CF_ALLOC_EXPORT_WORD0_TYPE_MASK) >> SQ_CF_ALLOC_EXPORT_WORD0_TYPE_SHIFT)
513 #define SQ_CF_ALLOC_EXPORT_WORD0_GET_RW_GPR(sq_cf_alloc_export_word0) \
514 ((sq_cf_alloc_export_word0 & SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR_MASK) >> SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR_SHIFT)
515 #define SQ_CF_ALLOC_EXPORT_WORD0_GET_RW_REL(sq_cf_alloc_export_word0) \
516 ((sq_cf_alloc_export_word0 & SQ_CF_ALLOC_EXPORT_WORD0_RW_REL_MASK) >> SQ_CF_ALLOC_EXPORT_WORD0_RW_REL_SHIFT)
517 #define SQ_CF_ALLOC_EXPORT_WORD0_GET_INDEX_GPR(sq_cf_alloc_export_word0) \
518 ((sq_cf_alloc_export_word0 & SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR_MASK) >> SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR_SHIFT)
519 #define SQ_CF_ALLOC_EXPORT_WORD0_GET_ELEM_SIZE(sq_cf_alloc_export_word0) \
520 ((sq_cf_alloc_export_word0 & SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE_MASK) >> SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE_SHIFT)
521
522 #define SQ_CF_ALLOC_EXPORT_WORD0_SET_ARRAY_BASE(sq_cf_alloc_export_word0_reg, array_base) \
523 sq_cf_alloc_export_word0_reg = (sq_cf_alloc_export_word0_reg & ~SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE_MASK) | (array_base << SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE_SHIFT)
524 #define SQ_CF_ALLOC_EXPORT_WORD0_SET_TYPE(sq_cf_alloc_export_word0_reg, type) \
525 sq_cf_alloc_export_word0_reg = (sq_cf_alloc_export_word0_reg & ~SQ_CF_ALLOC_EXPORT_WORD0_TYPE_MASK) | (type << SQ_CF_ALLOC_EXPORT_WORD0_TYPE_SHIFT)
526 #define SQ_CF_ALLOC_EXPORT_WORD0_SET_RW_GPR(sq_cf_alloc_export_word0_reg, rw_gpr) \
527 sq_cf_alloc_export_word0_reg = (sq_cf_alloc_export_word0_reg & ~SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR_MASK) | (rw_gpr << SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR_SHIFT)
528 #define SQ_CF_ALLOC_EXPORT_WORD0_SET_RW_REL(sq_cf_alloc_export_word0_reg, rw_rel) \
529 sq_cf_alloc_export_word0_reg = (sq_cf_alloc_export_word0_reg & ~SQ_CF_ALLOC_EXPORT_WORD0_RW_REL_MASK) | (rw_rel << SQ_CF_ALLOC_EXPORT_WORD0_RW_REL_SHIFT)
530 #define SQ_CF_ALLOC_EXPORT_WORD0_SET_INDEX_GPR(sq_cf_alloc_export_word0_reg, index_gpr) \
531 sq_cf_alloc_export_word0_reg = (sq_cf_alloc_export_word0_reg & ~SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR_MASK) | (index_gpr << SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR_SHIFT)
532 #define SQ_CF_ALLOC_EXPORT_WORD0_SET_ELEM_SIZE(sq_cf_alloc_export_word0_reg, elem_size) \
533 sq_cf_alloc_export_word0_reg = (sq_cf_alloc_export_word0_reg & ~SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE_MASK) | (elem_size << SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE_SHIFT)
534
535 #if defined(LITTLEENDIAN_CPU)
536
537 typedef struct _sq_cf_alloc_export_word0_t {
538 unsigned int array_base : SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE_SIZE;
539 unsigned int type : SQ_CF_ALLOC_EXPORT_WORD0_TYPE_SIZE;
540 unsigned int rw_gpr : SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR_SIZE;
541 unsigned int rw_rel : SQ_CF_ALLOC_EXPORT_WORD0_RW_REL_SIZE;
542 unsigned int index_gpr : SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR_SIZE;
543 unsigned int elem_size : SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE_SIZE;
544 } sq_cf_alloc_export_word0_t;
545
546 #elif defined(BIGENDIAN_CPU)
547
548 typedef struct _sq_cf_alloc_export_word0_t {
549 unsigned int elem_size : SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE_SIZE;
550 unsigned int index_gpr : SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR_SIZE;
551 unsigned int rw_rel : SQ_CF_ALLOC_EXPORT_WORD0_RW_REL_SIZE;
552 unsigned int rw_gpr : SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR_SIZE;
553 unsigned int type : SQ_CF_ALLOC_EXPORT_WORD0_TYPE_SIZE;
554 unsigned int array_base : SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE_SIZE;
555 } sq_cf_alloc_export_word0_t;
556
557 #endif
558
559 typedef union {
560 unsigned int val : 32;
561 sq_cf_alloc_export_word0_t f;
562 } sq_cf_alloc_export_word0_u;
563
564
565 /*
566 * SQ_CF_ALLOC_EXPORT_WORD1 struct
567 */
568
569 #define SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT_SIZE 4
570 #define SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM_SIZE 1
571 #define SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE_SIZE 1
572 #define SQ_CF_ALLOC_EXPORT_WORD1_CF_INST_SIZE 7
573 #define SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE_SIZE 1
574 #define SQ_CF_ALLOC_EXPORT_WORD1_BARRIER_SIZE 1
575
576 #define SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT_SHIFT 17
577 #define SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM_SHIFT 21
578 #define SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE_SHIFT 22
579 #define SQ_CF_ALLOC_EXPORT_WORD1_CF_INST_SHIFT 23
580 #define SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE_SHIFT 30
581 #define SQ_CF_ALLOC_EXPORT_WORD1_BARRIER_SHIFT 31
582
583 #define SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT_MASK 0x001e0000
584 #define SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM_MASK 0x00200000
585 #define SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE_MASK 0x00400000
586 #define SQ_CF_ALLOC_EXPORT_WORD1_CF_INST_MASK 0x3f800000
587 #define SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE_MASK 0x40000000
588 #define SQ_CF_ALLOC_EXPORT_WORD1_BARRIER_MASK 0x80000000
589
590 #define SQ_CF_ALLOC_EXPORT_WORD1_MASK \
591 (SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT_MASK | \
592 SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM_MASK | \
593 SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE_MASK | \
594 SQ_CF_ALLOC_EXPORT_WORD1_CF_INST_MASK | \
595 SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE_MASK | \
596 SQ_CF_ALLOC_EXPORT_WORD1_BARRIER_MASK)
597
598 #define SQ_CF_ALLOC_EXPORT_WORD1_DEFAULT 0xcdcc0000
599
600 #define SQ_CF_ALLOC_EXPORT_WORD1_GET_BURST_COUNT(sq_cf_alloc_export_word1) \
601 ((sq_cf_alloc_export_word1 & SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT_MASK) >> SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT_SHIFT)
602 #define SQ_CF_ALLOC_EXPORT_WORD1_GET_END_OF_PROGRAM(sq_cf_alloc_export_word1) \
603 ((sq_cf_alloc_export_word1 & SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM_MASK) >> SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM_SHIFT)
604 #define SQ_CF_ALLOC_EXPORT_WORD1_GET_VALID_PIXEL_MODE(sq_cf_alloc_export_word1) \
605 ((sq_cf_alloc_export_word1 & SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE_MASK) >> SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE_SHIFT)
606 #define SQ_CF_ALLOC_EXPORT_WORD1_GET_CF_INST(sq_cf_alloc_export_word1) \
607 ((sq_cf_alloc_export_word1 & SQ_CF_ALLOC_EXPORT_WORD1_CF_INST_MASK) >> SQ_CF_ALLOC_EXPORT_WORD1_CF_INST_SHIFT)
608 #define SQ_CF_ALLOC_EXPORT_WORD1_GET_WHOLE_QUAD_MODE(sq_cf_alloc_export_word1) \
609 ((sq_cf_alloc_export_word1 & SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE_MASK) >> SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE_SHIFT)
610 #define SQ_CF_ALLOC_EXPORT_WORD1_GET_BARRIER(sq_cf_alloc_export_word1) \
611 ((sq_cf_alloc_export_word1 & SQ_CF_ALLOC_EXPORT_WORD1_BARRIER_MASK) >> SQ_CF_ALLOC_EXPORT_WORD1_BARRIER_SHIFT)
612
613 #define SQ_CF_ALLOC_EXPORT_WORD1_SET_BURST_COUNT(sq_cf_alloc_export_word1_reg, burst_count) \
614 sq_cf_alloc_export_word1_reg = (sq_cf_alloc_export_word1_reg & ~SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT_MASK) | (burst_count << SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT_SHIFT)
615 #define SQ_CF_ALLOC_EXPORT_WORD1_SET_END_OF_PROGRAM(sq_cf_alloc_export_word1_reg, end_of_program) \
616 sq_cf_alloc_export_word1_reg = (sq_cf_alloc_export_word1_reg & ~SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM_MASK) | (end_of_program << SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM_SHIFT)
617 #define SQ_CF_ALLOC_EXPORT_WORD1_SET_VALID_PIXEL_MODE(sq_cf_alloc_export_word1_reg, valid_pixel_mode) \
618 sq_cf_alloc_export_word1_reg = (sq_cf_alloc_export_word1_reg & ~SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE_MASK) | (valid_pixel_mode << SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE_SHIFT)
619 #define SQ_CF_ALLOC_EXPORT_WORD1_SET_CF_INST(sq_cf_alloc_export_word1_reg, cf_inst) \
620 sq_cf_alloc_export_word1_reg = (sq_cf_alloc_export_word1_reg & ~SQ_CF_ALLOC_EXPORT_WORD1_CF_INST_MASK) | (cf_inst << SQ_CF_ALLOC_EXPORT_WORD1_CF_INST_SHIFT)
621 #define SQ_CF_ALLOC_EXPORT_WORD1_SET_WHOLE_QUAD_MODE(sq_cf_alloc_export_word1_reg, whole_quad_mode) \
622 sq_cf_alloc_export_word1_reg = (sq_cf_alloc_export_word1_reg & ~SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE_MASK) | (whole_quad_mode << SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE_SHIFT)
623 #define SQ_CF_ALLOC_EXPORT_WORD1_SET_BARRIER(sq_cf_alloc_export_word1_reg, barrier) \
624 sq_cf_alloc_export_word1_reg = (sq_cf_alloc_export_word1_reg & ~SQ_CF_ALLOC_EXPORT_WORD1_BARRIER_MASK) | (barrier << SQ_CF_ALLOC_EXPORT_WORD1_BARRIER_SHIFT)
625
626 #if defined(LITTLEENDIAN_CPU)
627
628 typedef struct _sq_cf_alloc_export_word1_t {
629 unsigned int : 17;
630 unsigned int burst_count : SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT_SIZE;
631 unsigned int end_of_program : SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM_SIZE;
632 unsigned int valid_pixel_mode : SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE_SIZE;
633 unsigned int cf_inst : SQ_CF_ALLOC_EXPORT_WORD1_CF_INST_SIZE;
634 unsigned int whole_quad_mode : SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE_SIZE;
635 unsigned int barrier : SQ_CF_ALLOC_EXPORT_WORD1_BARRIER_SIZE;
636 } sq_cf_alloc_export_word1_t;
637
638 #elif defined(BIGENDIAN_CPU)
639
640 typedef struct _sq_cf_alloc_export_word1_t {
641 unsigned int barrier : SQ_CF_ALLOC_EXPORT_WORD1_BARRIER_SIZE;
642 unsigned int whole_quad_mode : SQ_CF_ALLOC_EXPORT_WORD1_WHOLE_QUAD_MODE_SIZE;
643 unsigned int cf_inst : SQ_CF_ALLOC_EXPORT_WORD1_CF_INST_SIZE;
644 unsigned int valid_pixel_mode : SQ_CF_ALLOC_EXPORT_WORD1_VALID_PIXEL_MODE_SIZE;
645 unsigned int end_of_program : SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM_SIZE;
646 unsigned int burst_count : SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT_SIZE;
647 unsigned int : 17;
648 } sq_cf_alloc_export_word1_t;
649
650 #endif
651
652 typedef union {
653 unsigned int val : 32;
654 sq_cf_alloc_export_word1_t f;
655 } sq_cf_alloc_export_word1_u;
656
657
658 /*
659 * SQ_CF_ALLOC_EXPORT_WORD1_BUF struct
660 */
661
662 #define SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE_SIZE 12
663 #define SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK_SIZE 4
664
665 #define SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE_SHIFT 0
666 #define SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK_SHIFT 12
667
668 #define SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE_MASK 0x00000fff
669 #define SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK_MASK 0x0000f000
670
671 #define SQ_CF_ALLOC_EXPORT_WORD1_BUF_MASK \
672 (SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE_MASK | \
673 SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK_MASK)
674
675 #define SQ_CF_ALLOC_EXPORT_WORD1_BUF_DEFAULT 0x0000cdcd
676
677 #define SQ_CF_ALLOC_EXPORT_WORD1_BUF_GET_ARRAY_SIZE(sq_cf_alloc_export_word1_buf) \
678 ((sq_cf_alloc_export_word1_buf & SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE_MASK) >> SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE_SHIFT)
679 #define SQ_CF_ALLOC_EXPORT_WORD1_BUF_GET_COMP_MASK(sq_cf_alloc_export_word1_buf) \
680 ((sq_cf_alloc_export_word1_buf & SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK_MASK) >> SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK_SHIFT)
681
682 #define SQ_CF_ALLOC_EXPORT_WORD1_BUF_SET_ARRAY_SIZE(sq_cf_alloc_export_word1_buf_reg, array_size) \
683 sq_cf_alloc_export_word1_buf_reg = (sq_cf_alloc_export_word1_buf_reg & ~SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE_MASK) | (array_size << SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE_SHIFT)
684 #define SQ_CF_ALLOC_EXPORT_WORD1_BUF_SET_COMP_MASK(sq_cf_alloc_export_word1_buf_reg, comp_mask) \
685 sq_cf_alloc_export_word1_buf_reg = (sq_cf_alloc_export_word1_buf_reg & ~SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK_MASK) | (comp_mask << SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK_SHIFT)
686
687 #if defined(LITTLEENDIAN_CPU)
688
689 typedef struct _sq_cf_alloc_export_word1_buf_t {
690 unsigned int array_size : SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE_SIZE;
691 unsigned int comp_mask : SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK_SIZE;
692 unsigned int : 16;
693 } sq_cf_alloc_export_word1_buf_t;
694
695 #elif defined(BIGENDIAN_CPU)
696
697 typedef struct _sq_cf_alloc_export_word1_buf_t {
698 unsigned int : 16;
699 unsigned int comp_mask : SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK_SIZE;
700 unsigned int array_size : SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE_SIZE;
701 } sq_cf_alloc_export_word1_buf_t;
702
703 #endif
704
705 typedef union {
706 unsigned int val : 32;
707 sq_cf_alloc_export_word1_buf_t f;
708 } sq_cf_alloc_export_word1_buf_u;
709
710
711 /*
712 * SQ_CF_ALLOC_EXPORT_WORD1_SWIZ struct
713 */
714
715 #define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X_SIZE 3
716 #define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y_SIZE 3
717 #define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z_SIZE 3
718 #define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W_SIZE 3
719
720 #define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X_SHIFT 0
721 #define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y_SHIFT 3
722 #define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z_SHIFT 6
723 #define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W_SHIFT 9
724
725 #define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X_MASK 0x00000007
726 #define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y_MASK 0x00000038
727 #define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z_MASK 0x000001c0
728 #define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W_MASK 0x00000e00
729
730 #define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_MASK \
731 (SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X_MASK | \
732 SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y_MASK | \
733 SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z_MASK | \
734 SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W_MASK)
735
736 #define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_DEFAULT 0x00000dcd
737
738 #define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_GET_SEL_X(sq_cf_alloc_export_word1_swiz) \
739 ((sq_cf_alloc_export_word1_swiz & SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X_MASK) >> SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X_SHIFT)
740 #define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_GET_SEL_Y(sq_cf_alloc_export_word1_swiz) \
741 ((sq_cf_alloc_export_word1_swiz & SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y_MASK) >> SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y_SHIFT)
742 #define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_GET_SEL_Z(sq_cf_alloc_export_word1_swiz) \
743 ((sq_cf_alloc_export_word1_swiz & SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z_MASK) >> SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z_SHIFT)
744 #define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_GET_SEL_W(sq_cf_alloc_export_word1_swiz) \
745 ((sq_cf_alloc_export_word1_swiz & SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W_MASK) >> SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W_SHIFT)
746
747 #define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SET_SEL_X(sq_cf_alloc_export_word1_swiz_reg, sel_x) \
748 sq_cf_alloc_export_word1_swiz_reg = (sq_cf_alloc_export_word1_swiz_reg & ~SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X_MASK) | (sel_x << SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X_SHIFT)
749 #define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SET_SEL_Y(sq_cf_alloc_export_word1_swiz_reg, sel_y) \
750 sq_cf_alloc_export_word1_swiz_reg = (sq_cf_alloc_export_word1_swiz_reg & ~SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y_MASK) | (sel_y << SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y_SHIFT)
751 #define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SET_SEL_Z(sq_cf_alloc_export_word1_swiz_reg, sel_z) \
752 sq_cf_alloc_export_word1_swiz_reg = (sq_cf_alloc_export_word1_swiz_reg & ~SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z_MASK) | (sel_z << SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z_SHIFT)
753 #define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SET_SEL_W(sq_cf_alloc_export_word1_swiz_reg, sel_w) \
754 sq_cf_alloc_export_word1_swiz_reg = (sq_cf_alloc_export_word1_swiz_reg & ~SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W_MASK) | (sel_w << SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W_SHIFT)
755
756 #if defined(LITTLEENDIAN_CPU)
757
758 typedef struct _sq_cf_alloc_export_word1_swiz_t {
759 unsigned int sel_x : SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X_SIZE;
760 unsigned int sel_y : SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y_SIZE;
761 unsigned int sel_z : SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z_SIZE;
762 unsigned int sel_w : SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W_SIZE;
763 unsigned int : 20;
764 } sq_cf_alloc_export_word1_swiz_t;
765
766 #elif defined(BIGENDIAN_CPU)
767
768 typedef struct _sq_cf_alloc_export_word1_swiz_t {
769 unsigned int : 20;
770 unsigned int sel_w : SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W_SIZE;
771 unsigned int sel_z : SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z_SIZE;
772 unsigned int sel_y : SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y_SIZE;
773 unsigned int sel_x : SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X_SIZE;
774 } sq_cf_alloc_export_word1_swiz_t;
775
776 #endif
777
778 typedef union {
779 unsigned int val : 32;
780 sq_cf_alloc_export_word1_swiz_t f;
781 } sq_cf_alloc_export_word1_swiz_u;
782
783
784 /*
785 * SQ_ALU_WORD0 struct
786 */
787
788 #define SQ_ALU_WORD0_SRC0_SEL_SIZE 9
789 #define SQ_ALU_WORD0_SRC0_REL_SIZE 1
790 #define SQ_ALU_WORD0_SRC0_CHAN_SIZE 2
791 #define SQ_ALU_WORD0_SRC0_NEG_SIZE 1
792 #define SQ_ALU_WORD0_SRC1_SEL_SIZE 9
793 #define SQ_ALU_WORD0_SRC1_REL_SIZE 1
794 #define SQ_ALU_WORD0_SRC1_CHAN_SIZE 2
795 #define SQ_ALU_WORD0_SRC1_NEG_SIZE 1
796 #define SQ_ALU_WORD0_INDEX_MODE_SIZE 3
797 #define SQ_ALU_WORD0_PRED_SEL_SIZE 2
798 #define SQ_ALU_WORD0_LAST_SIZE 1
799
800 #define SQ_ALU_WORD0_SRC0_SEL_SHIFT 0
801 #define SQ_ALU_WORD0_SRC0_REL_SHIFT 9
802 #define SQ_ALU_WORD0_SRC0_CHAN_SHIFT 10
803 #define SQ_ALU_WORD0_SRC0_NEG_SHIFT 12
804 #define SQ_ALU_WORD0_SRC1_SEL_SHIFT 13
805 #define SQ_ALU_WORD0_SRC1_REL_SHIFT 22
806 #define SQ_ALU_WORD0_SRC1_CHAN_SHIFT 23
807 #define SQ_ALU_WORD0_SRC1_NEG_SHIFT 25
808 #define SQ_ALU_WORD0_INDEX_MODE_SHIFT 26
809 #define SQ_ALU_WORD0_PRED_SEL_SHIFT 29
810 #define SQ_ALU_WORD0_LAST_SHIFT 31
811
812 #define SQ_ALU_WORD0_SRC0_SEL_MASK 0x000001ff
813 #define SQ_ALU_WORD0_SRC0_REL_MASK 0x00000200
814 #define SQ_ALU_WORD0_SRC0_CHAN_MASK 0x00000c00
815 #define SQ_ALU_WORD0_SRC0_NEG_MASK 0x00001000
816 #define SQ_ALU_WORD0_SRC1_SEL_MASK 0x003fe000
817 #define SQ_ALU_WORD0_SRC1_REL_MASK 0x00400000
818 #define SQ_ALU_WORD0_SRC1_CHAN_MASK 0x01800000
819 #define SQ_ALU_WORD0_SRC1_NEG_MASK 0x02000000
820 #define SQ_ALU_WORD0_INDEX_MODE_MASK 0x1c000000
821 #define SQ_ALU_WORD0_PRED_SEL_MASK 0x60000000
822 #define SQ_ALU_WORD0_LAST_MASK 0x80000000
823
824 #define SQ_ALU_WORD0_MASK \
825 (SQ_ALU_WORD0_SRC0_SEL_MASK | \
826 SQ_ALU_WORD0_SRC0_REL_MASK | \
827 SQ_ALU_WORD0_SRC0_CHAN_MASK | \
828 SQ_ALU_WORD0_SRC0_NEG_MASK | \
829 SQ_ALU_WORD0_SRC1_SEL_MASK | \
830 SQ_ALU_WORD0_SRC1_REL_MASK | \
831 SQ_ALU_WORD0_SRC1_CHAN_MASK | \
832 SQ_ALU_WORD0_SRC1_NEG_MASK | \
833 SQ_ALU_WORD0_INDEX_MODE_MASK | \
834 SQ_ALU_WORD0_PRED_SEL_MASK | \
835 SQ_ALU_WORD0_LAST_MASK)
836
837 #define SQ_ALU_WORD0_DEFAULT 0xcdcdcdcd
838
839 #define SQ_ALU_WORD0_GET_SRC0_SEL(sq_alu_word0) \
840 ((sq_alu_word0 & SQ_ALU_WORD0_SRC0_SEL_MASK) >> SQ_ALU_WORD0_SRC0_SEL_SHIFT)
841 #define SQ_ALU_WORD0_GET_SRC0_REL(sq_alu_word0) \
842 ((sq_alu_word0 & SQ_ALU_WORD0_SRC0_REL_MASK) >> SQ_ALU_WORD0_SRC0_REL_SHIFT)
843 #define SQ_ALU_WORD0_GET_SRC0_CHAN(sq_alu_word0) \
844 ((sq_alu_word0 & SQ_ALU_WORD0_SRC0_CHAN_MASK) >> SQ_ALU_WORD0_SRC0_CHAN_SHIFT)
845 #define SQ_ALU_WORD0_GET_SRC0_NEG(sq_alu_word0) \
846 ((sq_alu_word0 & SQ_ALU_WORD0_SRC0_NEG_MASK) >> SQ_ALU_WORD0_SRC0_NEG_SHIFT)
847 #define SQ_ALU_WORD0_GET_SRC1_SEL(sq_alu_word0) \
848 ((sq_alu_word0 & SQ_ALU_WORD0_SRC1_SEL_MASK) >> SQ_ALU_WORD0_SRC1_SEL_SHIFT)
849 #define SQ_ALU_WORD0_GET_SRC1_REL(sq_alu_word0) \
850 ((sq_alu_word0 & SQ_ALU_WORD0_SRC1_REL_MASK) >> SQ_ALU_WORD0_SRC1_REL_SHIFT)
851 #define SQ_ALU_WORD0_GET_SRC1_CHAN(sq_alu_word0) \
852 ((sq_alu_word0 & SQ_ALU_WORD0_SRC1_CHAN_MASK) >> SQ_ALU_WORD0_SRC1_CHAN_SHIFT)
853 #define SQ_ALU_WORD0_GET_SRC1_NEG(sq_alu_word0) \
854 ((sq_alu_word0 & SQ_ALU_WORD0_SRC1_NEG_MASK) >> SQ_ALU_WORD0_SRC1_NEG_SHIFT)
855 #define SQ_ALU_WORD0_GET_INDEX_MODE(sq_alu_word0) \
856 ((sq_alu_word0 & SQ_ALU_WORD0_INDEX_MODE_MASK) >> SQ_ALU_WORD0_INDEX_MODE_SHIFT)
857 #define SQ_ALU_WORD0_GET_PRED_SEL(sq_alu_word0) \
858 ((sq_alu_word0 & SQ_ALU_WORD0_PRED_SEL_MASK) >> SQ_ALU_WORD0_PRED_SEL_SHIFT)
859 #define SQ_ALU_WORD0_GET_LAST(sq_alu_word0) \
860 ((sq_alu_word0 & SQ_ALU_WORD0_LAST_MASK) >> SQ_ALU_WORD0_LAST_SHIFT)
861
862 #define SQ_ALU_WORD0_SET_SRC0_SEL(sq_alu_word0_reg, src0_sel) \
863 sq_alu_word0_reg = (sq_alu_word0_reg & ~SQ_ALU_WORD0_SRC0_SEL_MASK) | (src0_sel << SQ_ALU_WORD0_SRC0_SEL_SHIFT)
864 #define SQ_ALU_WORD0_SET_SRC0_REL(sq_alu_word0_reg, src0_rel) \
865 sq_alu_word0_reg = (sq_alu_word0_reg & ~SQ_ALU_WORD0_SRC0_REL_MASK) | (src0_rel << SQ_ALU_WORD0_SRC0_REL_SHIFT)
866 #define SQ_ALU_WORD0_SET_SRC0_CHAN(sq_alu_word0_reg, src0_chan) \
867 sq_alu_word0_reg = (sq_alu_word0_reg & ~SQ_ALU_WORD0_SRC0_CHAN_MASK) | (src0_chan << SQ_ALU_WORD0_SRC0_CHAN_SHIFT)
868 #define SQ_ALU_WORD0_SET_SRC0_NEG(sq_alu_word0_reg, src0_neg) \
869 sq_alu_word0_reg = (sq_alu_word0_reg & ~SQ_ALU_WORD0_SRC0_NEG_MASK) | (src0_neg << SQ_ALU_WORD0_SRC0_NEG_SHIFT)
870 #define SQ_ALU_WORD0_SET_SRC1_SEL(sq_alu_word0_reg, src1_sel) \
871 sq_alu_word0_reg = (sq_alu_word0_reg & ~SQ_ALU_WORD0_SRC1_SEL_MASK) | (src1_sel << SQ_ALU_WORD0_SRC1_SEL_SHIFT)
872 #define SQ_ALU_WORD0_SET_SRC1_REL(sq_alu_word0_reg, src1_rel) \
873 sq_alu_word0_reg = (sq_alu_word0_reg & ~SQ_ALU_WORD0_SRC1_REL_MASK) | (src1_rel << SQ_ALU_WORD0_SRC1_REL_SHIFT)
874 #define SQ_ALU_WORD0_SET_SRC1_CHAN(sq_alu_word0_reg, src1_chan) \
875 sq_alu_word0_reg = (sq_alu_word0_reg & ~SQ_ALU_WORD0_SRC1_CHAN_MASK) | (src1_chan << SQ_ALU_WORD0_SRC1_CHAN_SHIFT)
876 #define SQ_ALU_WORD0_SET_SRC1_NEG(sq_alu_word0_reg, src1_neg) \
877 sq_alu_word0_reg = (sq_alu_word0_reg & ~SQ_ALU_WORD0_SRC1_NEG_MASK) | (src1_neg << SQ_ALU_WORD0_SRC1_NEG_SHIFT)
878 #define SQ_ALU_WORD0_SET_INDEX_MODE(sq_alu_word0_reg, index_mode) \
879 sq_alu_word0_reg = (sq_alu_word0_reg & ~SQ_ALU_WORD0_INDEX_MODE_MASK) | (index_mode << SQ_ALU_WORD0_INDEX_MODE_SHIFT)
880 #define SQ_ALU_WORD0_SET_PRED_SEL(sq_alu_word0_reg, pred_sel) \
881 sq_alu_word0_reg = (sq_alu_word0_reg & ~SQ_ALU_WORD0_PRED_SEL_MASK) | (pred_sel << SQ_ALU_WORD0_PRED_SEL_SHIFT)
882 #define SQ_ALU_WORD0_SET_LAST(sq_alu_word0_reg, last) \
883 sq_alu_word0_reg = (sq_alu_word0_reg & ~SQ_ALU_WORD0_LAST_MASK) | (last << SQ_ALU_WORD0_LAST_SHIFT)
884
885 #if defined(LITTLEENDIAN_CPU)
886
887 typedef struct _sq_alu_word0_t {
888 unsigned int src0_sel : SQ_ALU_WORD0_SRC0_SEL_SIZE;
889 unsigned int src0_rel : SQ_ALU_WORD0_SRC0_REL_SIZE;
890 unsigned int src0_chan : SQ_ALU_WORD0_SRC0_CHAN_SIZE;
891 unsigned int src0_neg : SQ_ALU_WORD0_SRC0_NEG_SIZE;
892 unsigned int src1_sel : SQ_ALU_WORD0_SRC1_SEL_SIZE;
893 unsigned int src1_rel : SQ_ALU_WORD0_SRC1_REL_SIZE;
894 unsigned int src1_chan : SQ_ALU_WORD0_SRC1_CHAN_SIZE;
895 unsigned int src1_neg : SQ_ALU_WORD0_SRC1_NEG_SIZE;
896 unsigned int index_mode : SQ_ALU_WORD0_INDEX_MODE_SIZE;
897 unsigned int pred_sel : SQ_ALU_WORD0_PRED_SEL_SIZE;
898 unsigned int last : SQ_ALU_WORD0_LAST_SIZE;
899 } sq_alu_word0_t;
900
901 #elif defined(BIGENDIAN_CPU)
902
903 typedef struct _sq_alu_word0_t {
904 unsigned int last : SQ_ALU_WORD0_LAST_SIZE;
905 unsigned int pred_sel : SQ_ALU_WORD0_PRED_SEL_SIZE;
906 unsigned int index_mode : SQ_ALU_WORD0_INDEX_MODE_SIZE;
907 unsigned int src1_neg : SQ_ALU_WORD0_SRC1_NEG_SIZE;
908 unsigned int src1_chan : SQ_ALU_WORD0_SRC1_CHAN_SIZE;
909 unsigned int src1_rel : SQ_ALU_WORD0_SRC1_REL_SIZE;
910 unsigned int src1_sel : SQ_ALU_WORD0_SRC1_SEL_SIZE;
911 unsigned int src0_neg : SQ_ALU_WORD0_SRC0_NEG_SIZE;
912 unsigned int src0_chan : SQ_ALU_WORD0_SRC0_CHAN_SIZE;
913 unsigned int src0_rel : SQ_ALU_WORD0_SRC0_REL_SIZE;
914 unsigned int src0_sel : SQ_ALU_WORD0_SRC0_SEL_SIZE;
915 } sq_alu_word0_t;
916
917 #endif
918
919 typedef union {
920 unsigned int val : 32;
921 sq_alu_word0_t f;
922 } sq_alu_word0_u;
923
924
925 /*
926 * SQ_ALU_WORD1 struct
927 */
928
929 #define SQ_ALU_WORD1_ENCODING_SIZE 3
930 #define SQ_ALU_WORD1_BANK_SWIZZLE_SIZE 3
931 #define SQ_ALU_WORD1_DST_GPR_SIZE 7
932 #define SQ_ALU_WORD1_DST_REL_SIZE 1
933 #define SQ_ALU_WORD1_DST_CHAN_SIZE 2
934 #define SQ_ALU_WORD1_CLAMP_SIZE 1
935
936 #define SQ_ALU_WORD1_ENCODING_SHIFT 15
937 #define SQ_ALU_WORD1_BANK_SWIZZLE_SHIFT 18
938 #define SQ_ALU_WORD1_DST_GPR_SHIFT 21
939 #define SQ_ALU_WORD1_DST_REL_SHIFT 28
940 #define SQ_ALU_WORD1_DST_CHAN_SHIFT 29
941 #define SQ_ALU_WORD1_CLAMP_SHIFT 31
942
943 #define SQ_ALU_WORD1_ENCODING_MASK 0x00038000
944 #define SQ_ALU_WORD1_BANK_SWIZZLE_MASK 0x001c0000
945 #define SQ_ALU_WORD1_DST_GPR_MASK 0x0fe00000
946 #define SQ_ALU_WORD1_DST_REL_MASK 0x10000000
947 #define SQ_ALU_WORD1_DST_CHAN_MASK 0x60000000
948 #define SQ_ALU_WORD1_CLAMP_MASK 0x80000000
949
950 #define SQ_ALU_WORD1_MASK \
951 (SQ_ALU_WORD1_ENCODING_MASK | \
952 SQ_ALU_WORD1_BANK_SWIZZLE_MASK | \
953 SQ_ALU_WORD1_DST_GPR_MASK | \
954 SQ_ALU_WORD1_DST_REL_MASK | \
955 SQ_ALU_WORD1_DST_CHAN_MASK | \
956 SQ_ALU_WORD1_CLAMP_MASK)
957
958 #define SQ_ALU_WORD1_DEFAULT 0xcdcd8000
959
960 #define SQ_ALU_WORD1_GET_ENCODING(sq_alu_word1) \
961 ((sq_alu_word1 & SQ_ALU_WORD1_ENCODING_MASK) >> SQ_ALU_WORD1_ENCODING_SHIFT)
962 #define SQ_ALU_WORD1_GET_BANK_SWIZZLE(sq_alu_word1) \
963 ((sq_alu_word1 & SQ_ALU_WORD1_BANK_SWIZZLE_MASK) >> SQ_ALU_WORD1_BANK_SWIZZLE_SHIFT)
964 #define SQ_ALU_WORD1_GET_DST_GPR(sq_alu_word1) \
965 ((sq_alu_word1 & SQ_ALU_WORD1_DST_GPR_MASK) >> SQ_ALU_WORD1_DST_GPR_SHIFT)
966 #define SQ_ALU_WORD1_GET_DST_REL(sq_alu_word1) \
967 ((sq_alu_word1 & SQ_ALU_WORD1_DST_REL_MASK) >> SQ_ALU_WORD1_DST_REL_SHIFT)
968 #define SQ_ALU_WORD1_GET_DST_CHAN(sq_alu_word1) \
969 ((sq_alu_word1 & SQ_ALU_WORD1_DST_CHAN_MASK) >> SQ_ALU_WORD1_DST_CHAN_SHIFT)
970 #define SQ_ALU_WORD1_GET_CLAMP(sq_alu_word1) \
971 ((sq_alu_word1 & SQ_ALU_WORD1_CLAMP_MASK) >> SQ_ALU_WORD1_CLAMP_SHIFT)
972
973 #define SQ_ALU_WORD1_SET_ENCODING(sq_alu_word1_reg, encoding) \
974 sq_alu_word1_reg = (sq_alu_word1_reg & ~SQ_ALU_WORD1_ENCODING_MASK) | (encoding << SQ_ALU_WORD1_ENCODING_SHIFT)
975 #define SQ_ALU_WORD1_SET_BANK_SWIZZLE(sq_alu_word1_reg, bank_swizzle) \
976 sq_alu_word1_reg = (sq_alu_word1_reg & ~SQ_ALU_WORD1_BANK_SWIZZLE_MASK) | (bank_swizzle << SQ_ALU_WORD1_BANK_SWIZZLE_SHIFT)
977 #define SQ_ALU_WORD1_SET_DST_GPR(sq_alu_word1_reg, dst_gpr) \
978 sq_alu_word1_reg = (sq_alu_word1_reg & ~SQ_ALU_WORD1_DST_GPR_MASK) | (dst_gpr << SQ_ALU_WORD1_DST_GPR_SHIFT)
979 #define SQ_ALU_WORD1_SET_DST_REL(sq_alu_word1_reg, dst_rel) \
980 sq_alu_word1_reg = (sq_alu_word1_reg & ~SQ_ALU_WORD1_DST_REL_MASK) | (dst_rel << SQ_ALU_WORD1_DST_REL_SHIFT)
981 #define SQ_ALU_WORD1_SET_DST_CHAN(sq_alu_word1_reg, dst_chan) \
982 sq_alu_word1_reg = (sq_alu_word1_reg & ~SQ_ALU_WORD1_DST_CHAN_MASK) | (dst_chan << SQ_ALU_WORD1_DST_CHAN_SHIFT)
983 #define SQ_ALU_WORD1_SET_CLAMP(sq_alu_word1_reg, clamp) \
984 sq_alu_word1_reg = (sq_alu_word1_reg & ~SQ_ALU_WORD1_CLAMP_MASK) | (clamp << SQ_ALU_WORD1_CLAMP_SHIFT)
985
986 #if defined(LITTLEENDIAN_CPU)
987
988 typedef struct _sq_alu_word1_t {
989 unsigned int : 15;
990 unsigned int encoding : SQ_ALU_WORD1_ENCODING_SIZE;
991 unsigned int bank_swizzle : SQ_ALU_WORD1_BANK_SWIZZLE_SIZE;
992 unsigned int dst_gpr : SQ_ALU_WORD1_DST_GPR_SIZE;
993 unsigned int dst_rel : SQ_ALU_WORD1_DST_REL_SIZE;
994 unsigned int dst_chan : SQ_ALU_WORD1_DST_CHAN_SIZE;
995 unsigned int clamp : SQ_ALU_WORD1_CLAMP_SIZE;
996 } sq_alu_word1_t;
997
998 #elif defined(BIGENDIAN_CPU)
999
1000 typedef struct _sq_alu_word1_t {
1001 unsigned int clamp : SQ_ALU_WORD1_CLAMP_SIZE;
1002 unsigned int dst_chan : SQ_ALU_WORD1_DST_CHAN_SIZE;
1003 unsigned int dst_rel : SQ_ALU_WORD1_DST_REL_SIZE;
1004 unsigned int dst_gpr : SQ_ALU_WORD1_DST_GPR_SIZE;
1005 unsigned int bank_swizzle : SQ_ALU_WORD1_BANK_SWIZZLE_SIZE;
1006 unsigned int encoding : SQ_ALU_WORD1_ENCODING_SIZE;
1007 unsigned int : 15;
1008 } sq_alu_word1_t;
1009
1010 #endif
1011
1012 typedef union {
1013 unsigned int val : 32;
1014 sq_alu_word1_t f;
1015 } sq_alu_word1_u;
1016
1017
1018 /*
1019 * SQ_ALU_WORD1_OP2_V2 struct
1020 */
1021
1022 #define SQ_ALU_WORD1_OP2_V2_SRC0_ABS_SIZE 1
1023 #define SQ_ALU_WORD1_OP2_V2_SRC1_ABS_SIZE 1
1024 #define SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK_SIZE 1
1025 #define SQ_ALU_WORD1_OP2_V2_UPDATE_PRED_SIZE 1
1026 #define SQ_ALU_WORD1_OP2_V2_WRITE_MASK_SIZE 1
1027 #define SQ_ALU_WORD1_OP2_V2_OMOD_SIZE 2
1028 #define SQ_ALU_WORD1_OP2_V2_ALU_INST_SIZE 11
1029
1030 #define SQ_ALU_WORD1_OP2_V2_SRC0_ABS_SHIFT 0
1031 #define SQ_ALU_WORD1_OP2_V2_SRC1_ABS_SHIFT 1
1032 #define SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK_SHIFT 2
1033 #define SQ_ALU_WORD1_OP2_V2_UPDATE_PRED_SHIFT 3
1034 #define SQ_ALU_WORD1_OP2_V2_WRITE_MASK_SHIFT 4
1035 #define SQ_ALU_WORD1_OP2_V2_OMOD_SHIFT 5
1036 #define SQ_ALU_WORD1_OP2_V2_ALU_INST_SHIFT 7
1037
1038 #define SQ_ALU_WORD1_OP2_V2_SRC0_ABS_MASK 0x00000001
1039 #define SQ_ALU_WORD1_OP2_V2_SRC1_ABS_MASK 0x00000002
1040 #define SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK_MASK 0x00000004
1041 #define SQ_ALU_WORD1_OP2_V2_UPDATE_PRED_MASK 0x00000008
1042 #define SQ_ALU_WORD1_OP2_V2_WRITE_MASK_MASK 0x00000010
1043 #define SQ_ALU_WORD1_OP2_V2_OMOD_MASK 0x00000060
1044 #define SQ_ALU_WORD1_OP2_V2_ALU_INST_MASK 0x0003ff80
1045
1046 #define SQ_ALU_WORD1_OP2_V2_MASK \
1047 (SQ_ALU_WORD1_OP2_V2_SRC0_ABS_MASK | \
1048 SQ_ALU_WORD1_OP2_V2_SRC1_ABS_MASK | \
1049 SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK_MASK | \
1050 SQ_ALU_WORD1_OP2_V2_UPDATE_PRED_MASK | \
1051 SQ_ALU_WORD1_OP2_V2_WRITE_MASK_MASK | \
1052 SQ_ALU_WORD1_OP2_V2_OMOD_MASK | \
1053 SQ_ALU_WORD1_OP2_V2_ALU_INST_MASK)
1054
1055 #define SQ_ALU_WORD1_OP2_V2_DEFAULT 0x0001cdcd
1056
1057 #define SQ_ALU_WORD1_OP2_V2_GET_SRC0_ABS(sq_alu_word1_op2_v2) \
1058 ((sq_alu_word1_op2_v2 & SQ_ALU_WORD1_OP2_V2_SRC0_ABS_MASK) >> SQ_ALU_WORD1_OP2_V2_SRC0_ABS_SHIFT)
1059 #define SQ_ALU_WORD1_OP2_V2_GET_SRC1_ABS(sq_alu_word1_op2_v2) \
1060 ((sq_alu_word1_op2_v2 & SQ_ALU_WORD1_OP2_V2_SRC1_ABS_MASK) >> SQ_ALU_WORD1_OP2_V2_SRC1_ABS_SHIFT)
1061 #define SQ_ALU_WORD1_OP2_V2_GET_UPDATE_EXECUTE_MASK(sq_alu_word1_op2_v2) \
1062 ((sq_alu_word1_op2_v2 & SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK_MASK) >> SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK_SHIFT)
1063 #define SQ_ALU_WORD1_OP2_V2_GET_UPDATE_PRED(sq_alu_word1_op2_v2) \
1064 ((sq_alu_word1_op2_v2 & SQ_ALU_WORD1_OP2_V2_UPDATE_PRED_MASK) >> SQ_ALU_WORD1_OP2_V2_UPDATE_PRED_SHIFT)
1065 #define SQ_ALU_WORD1_OP2_V2_GET_WRITE_MASK(sq_alu_word1_op2_v2) \
1066 ((sq_alu_word1_op2_v2 & SQ_ALU_WORD1_OP2_V2_WRITE_MASK_MASK) >> SQ_ALU_WORD1_OP2_V2_WRITE_MASK_SHIFT)
1067 #define SQ_ALU_WORD1_OP2_V2_GET_OMOD(sq_alu_word1_op2_v2) \
1068 ((sq_alu_word1_op2_v2 & SQ_ALU_WORD1_OP2_V2_OMOD_MASK) >> SQ_ALU_WORD1_OP2_V2_OMOD_SHIFT)
1069 #define SQ_ALU_WORD1_OP2_V2_GET_ALU_INST(sq_alu_word1_op2_v2) \
1070 ((sq_alu_word1_op2_v2 & SQ_ALU_WORD1_OP2_V2_ALU_INST_MASK) >> SQ_ALU_WORD1_OP2_V2_ALU_INST_SHIFT)
1071
1072 #define SQ_ALU_WORD1_OP2_V2_SET_SRC0_ABS(sq_alu_word1_op2_v2_reg, src0_abs) \
1073 sq_alu_word1_op2_v2_reg = (sq_alu_word1_op2_v2_reg & ~SQ_ALU_WORD1_OP2_V2_SRC0_ABS_MASK) | (src0_abs << SQ_ALU_WORD1_OP2_V2_SRC0_ABS_SHIFT)
1074 #define SQ_ALU_WORD1_OP2_V2_SET_SRC1_ABS(sq_alu_word1_op2_v2_reg, src1_abs) \
1075 sq_alu_word1_op2_v2_reg = (sq_alu_word1_op2_v2_reg & ~SQ_ALU_WORD1_OP2_V2_SRC1_ABS_MASK) | (src1_abs << SQ_ALU_WORD1_OP2_V2_SRC1_ABS_SHIFT)
1076 #define SQ_ALU_WORD1_OP2_V2_SET_UPDATE_EXECUTE_MASK(sq_alu_word1_op2_v2_reg, update_execute_mask) \
1077 sq_alu_word1_op2_v2_reg = (sq_alu_word1_op2_v2_reg & ~SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK_MASK) | (update_execute_mask << SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK_SHIFT)
1078 #define SQ_ALU_WORD1_OP2_V2_SET_UPDATE_PRED(sq_alu_word1_op2_v2_reg, update_pred) \
1079 sq_alu_word1_op2_v2_reg = (sq_alu_word1_op2_v2_reg & ~SQ_ALU_WORD1_OP2_V2_UPDATE_PRED_MASK) | (update_pred << SQ_ALU_WORD1_OP2_V2_UPDATE_PRED_SHIFT)
1080 #define SQ_ALU_WORD1_OP2_V2_SET_WRITE_MASK(sq_alu_word1_op2_v2_reg, write_mask) \
1081 sq_alu_word1_op2_v2_reg = (sq_alu_word1_op2_v2_reg & ~SQ_ALU_WORD1_OP2_V2_WRITE_MASK_MASK) | (write_mask << SQ_ALU_WORD1_OP2_V2_WRITE_MASK_SHIFT)
1082 #define SQ_ALU_WORD1_OP2_V2_SET_OMOD(sq_alu_word1_op2_v2_reg, omod) \
1083 sq_alu_word1_op2_v2_reg = (sq_alu_word1_op2_v2_reg & ~SQ_ALU_WORD1_OP2_V2_OMOD_MASK) | (omod << SQ_ALU_WORD1_OP2_V2_OMOD_SHIFT)
1084 #define SQ_ALU_WORD1_OP2_V2_SET_ALU_INST(sq_alu_word1_op2_v2_reg, alu_inst) \
1085 sq_alu_word1_op2_v2_reg = (sq_alu_word1_op2_v2_reg & ~SQ_ALU_WORD1_OP2_V2_ALU_INST_MASK) | (alu_inst << SQ_ALU_WORD1_OP2_V2_ALU_INST_SHIFT)
1086
1087 #if defined(LITTLEENDIAN_CPU)
1088
1089 typedef struct _sq_alu_word1_op2_v2_t {
1090 unsigned int src0_abs : SQ_ALU_WORD1_OP2_V2_SRC0_ABS_SIZE;
1091 unsigned int src1_abs : SQ_ALU_WORD1_OP2_V2_SRC1_ABS_SIZE;
1092 unsigned int update_execute_mask : SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK_SIZE;
1093 unsigned int update_pred : SQ_ALU_WORD1_OP2_V2_UPDATE_PRED_SIZE;
1094 unsigned int write_mask : SQ_ALU_WORD1_OP2_V2_WRITE_MASK_SIZE;
1095 unsigned int omod : SQ_ALU_WORD1_OP2_V2_OMOD_SIZE;
1096 unsigned int alu_inst : SQ_ALU_WORD1_OP2_V2_ALU_INST_SIZE;
1097 unsigned int : 14;
1098 } sq_alu_word1_op2_v2_t;
1099
1100 #elif defined(BIGENDIAN_CPU)
1101
1102 typedef struct _sq_alu_word1_op2_v2_t {
1103 unsigned int : 14;
1104 unsigned int alu_inst : SQ_ALU_WORD1_OP2_V2_ALU_INST_SIZE;
1105 unsigned int omod : SQ_ALU_WORD1_OP2_V2_OMOD_SIZE;
1106 unsigned int write_mask : SQ_ALU_WORD1_OP2_V2_WRITE_MASK_SIZE;
1107 unsigned int update_pred : SQ_ALU_WORD1_OP2_V2_UPDATE_PRED_SIZE;
1108 unsigned int update_execute_mask : SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK_SIZE;
1109 unsigned int src1_abs : SQ_ALU_WORD1_OP2_V2_SRC1_ABS_SIZE;
1110 unsigned int src0_abs : SQ_ALU_WORD1_OP2_V2_SRC0_ABS_SIZE;
1111 } sq_alu_word1_op2_v2_t;
1112
1113 #endif
1114
1115 #if defined(LITTLEENDIAN_CPU)
1116
1117 typedef struct _sq_alu_word1_op2_r6xx_t {
1118 unsigned int src0_abs : SQ_ALU_WORD1_OP2_V2_SRC0_ABS_SIZE;
1119 unsigned int src1_abs : SQ_ALU_WORD1_OP2_V2_SRC1_ABS_SIZE;
1120 unsigned int update_execute_mask : SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK_SIZE;
1121 unsigned int update_pred : SQ_ALU_WORD1_OP2_V2_UPDATE_PRED_SIZE;
1122 unsigned int write_mask : SQ_ALU_WORD1_OP2_V2_WRITE_MASK_SIZE;
1123 unsigned int fog_export : 1;
1124 unsigned int omod : SQ_ALU_WORD1_OP2_V2_OMOD_SIZE;
1125 unsigned int alu_inst : 10;
1126 unsigned int : 14;
1127 } sq_alu_word1_op2_v1_t;
1128
1129 #elif defined(BIGENDIAN_CPU)
1130
1131 typedef struct _sq_alu_word1_op2_r6xx_t {
1132 unsigned int : 14;
1133 unsigned int alu_inst : 10;
1134 unsigned int omod : SQ_ALU_WORD1_OP2_V2_OMOD_SIZE;
1135 unsigned int fog_export : 1;
1136 unsigned int write_mask : SQ_ALU_WORD1_OP2_V2_WRITE_MASK_SIZE;
1137 unsigned int update_pred : SQ_ALU_WORD1_OP2_V2_UPDATE_PRED_SIZE;
1138 unsigned int update_execute_mask : SQ_ALU_WORD1_OP2_V2_UPDATE_EXECUTE_MASK_SIZE;
1139 unsigned int src1_abs : SQ_ALU_WORD1_OP2_V2_SRC1_ABS_SIZE;
1140 unsigned int src0_abs : SQ_ALU_WORD1_OP2_V2_SRC0_ABS_SIZE;
1141 } sq_alu_word1_op2_v1_t;
1142
1143 #endif
1144
1145 typedef union {
1146 unsigned int val : 32;
1147 sq_alu_word1_op2_v2_t f;
1148 sq_alu_word1_op2_v1_t f6;
1149 } sq_alu_word1_op2_v2_u;
1150
1151
1152 /*
1153 * SQ_ALU_WORD1_OP3 struct
1154 */
1155
1156 #define SQ_ALU_WORD1_OP3_SRC2_SEL_SIZE 9
1157 #define SQ_ALU_WORD1_OP3_SRC2_REL_SIZE 1
1158 #define SQ_ALU_WORD1_OP3_SRC2_CHAN_SIZE 2
1159 #define SQ_ALU_WORD1_OP3_SRC2_NEG_SIZE 1
1160 #define SQ_ALU_WORD1_OP3_ALU_INST_SIZE 5
1161
1162 #define SQ_ALU_WORD1_OP3_SRC2_SEL_SHIFT 0
1163 #define SQ_ALU_WORD1_OP3_SRC2_REL_SHIFT 9
1164 #define SQ_ALU_WORD1_OP3_SRC2_CHAN_SHIFT 10
1165 #define SQ_ALU_WORD1_OP3_SRC2_NEG_SHIFT 12
1166 #define SQ_ALU_WORD1_OP3_ALU_INST_SHIFT 13
1167
1168 #define SQ_ALU_WORD1_OP3_SRC2_SEL_MASK 0x000001ff
1169 #define SQ_ALU_WORD1_OP3_SRC2_REL_MASK 0x00000200
1170 #define SQ_ALU_WORD1_OP3_SRC2_CHAN_MASK 0x00000c00
1171 #define SQ_ALU_WORD1_OP3_SRC2_NEG_MASK 0x00001000
1172 #define SQ_ALU_WORD1_OP3_ALU_INST_MASK 0x0003e000
1173
1174 #define SQ_ALU_WORD1_OP3_MASK \
1175 (SQ_ALU_WORD1_OP3_SRC2_SEL_MASK | \
1176 SQ_ALU_WORD1_OP3_SRC2_REL_MASK | \
1177 SQ_ALU_WORD1_OP3_SRC2_CHAN_MASK | \
1178 SQ_ALU_WORD1_OP3_SRC2_NEG_MASK | \
1179 SQ_ALU_WORD1_OP3_ALU_INST_MASK)
1180
1181 #define SQ_ALU_WORD1_OP3_DEFAULT 0x0001cdcd
1182
1183 #define SQ_ALU_WORD1_OP3_GET_SRC2_SEL(sq_alu_word1_op3) \
1184 ((sq_alu_word1_op3 & SQ_ALU_WORD1_OP3_SRC2_SEL_MASK) >> SQ_ALU_WORD1_OP3_SRC2_SEL_SHIFT)
1185 #define SQ_ALU_WORD1_OP3_GET_SRC2_REL(sq_alu_word1_op3) \
1186 ((sq_alu_word1_op3 & SQ_ALU_WORD1_OP3_SRC2_REL_MASK) >> SQ_ALU_WORD1_OP3_SRC2_REL_SHIFT)
1187 #define SQ_ALU_WORD1_OP3_GET_SRC2_CHAN(sq_alu_word1_op3) \
1188 ((sq_alu_word1_op3 & SQ_ALU_WORD1_OP3_SRC2_CHAN_MASK) >> SQ_ALU_WORD1_OP3_SRC2_CHAN_SHIFT)
1189 #define SQ_ALU_WORD1_OP3_GET_SRC2_NEG(sq_alu_word1_op3) \
1190 ((sq_alu_word1_op3 & SQ_ALU_WORD1_OP3_SRC2_NEG_MASK) >> SQ_ALU_WORD1_OP3_SRC2_NEG_SHIFT)
1191 #define SQ_ALU_WORD1_OP3_GET_ALU_INST(sq_alu_word1_op3) \
1192 ((sq_alu_word1_op3 & SQ_ALU_WORD1_OP3_ALU_INST_MASK) >> SQ_ALU_WORD1_OP3_ALU_INST_SHIFT)
1193
1194 #define SQ_ALU_WORD1_OP3_SET_SRC2_SEL(sq_alu_word1_op3_reg, src2_sel) \
1195 sq_alu_word1_op3_reg = (sq_alu_word1_op3_reg & ~SQ_ALU_WORD1_OP3_SRC2_SEL_MASK) | (src2_sel << SQ_ALU_WORD1_OP3_SRC2_SEL_SHIFT)
1196 #define SQ_ALU_WORD1_OP3_SET_SRC2_REL(sq_alu_word1_op3_reg, src2_rel) \
1197 sq_alu_word1_op3_reg = (sq_alu_word1_op3_reg & ~SQ_ALU_WORD1_OP3_SRC2_REL_MASK) | (src2_rel << SQ_ALU_WORD1_OP3_SRC2_REL_SHIFT)
1198 #define SQ_ALU_WORD1_OP3_SET_SRC2_CHAN(sq_alu_word1_op3_reg, src2_chan) \
1199 sq_alu_word1_op3_reg = (sq_alu_word1_op3_reg & ~SQ_ALU_WORD1_OP3_SRC2_CHAN_MASK) | (src2_chan << SQ_ALU_WORD1_OP3_SRC2_CHAN_SHIFT)
1200 #define SQ_ALU_WORD1_OP3_SET_SRC2_NEG(sq_alu_word1_op3_reg, src2_neg) \
1201 sq_alu_word1_op3_reg = (sq_alu_word1_op3_reg & ~SQ_ALU_WORD1_OP3_SRC2_NEG_MASK) | (src2_neg << SQ_ALU_WORD1_OP3_SRC2_NEG_SHIFT)
1202 #define SQ_ALU_WORD1_OP3_SET_ALU_INST(sq_alu_word1_op3_reg, alu_inst) \
1203 sq_alu_word1_op3_reg = (sq_alu_word1_op3_reg & ~SQ_ALU_WORD1_OP3_ALU_INST_MASK) | (alu_inst << SQ_ALU_WORD1_OP3_ALU_INST_SHIFT)
1204
1205 #if defined(LITTLEENDIAN_CPU)
1206
1207 typedef struct _sq_alu_word1_op3_t {
1208 unsigned int src2_sel : SQ_ALU_WORD1_OP3_SRC2_SEL_SIZE;
1209 unsigned int src2_rel : SQ_ALU_WORD1_OP3_SRC2_REL_SIZE;
1210 unsigned int src2_chan : SQ_ALU_WORD1_OP3_SRC2_CHAN_SIZE;
1211 unsigned int src2_neg : SQ_ALU_WORD1_OP3_SRC2_NEG_SIZE;
1212 unsigned int alu_inst : SQ_ALU_WORD1_OP3_ALU_INST_SIZE;
1213 unsigned int : 14;
1214 } sq_alu_word1_op3_t;
1215
1216 #elif defined(BIGENDIAN_CPU)
1217
1218 typedef struct _sq_alu_word1_op3_t {
1219 unsigned int : 14;
1220 unsigned int alu_inst : SQ_ALU_WORD1_OP3_ALU_INST_SIZE;
1221 unsigned int src2_neg : SQ_ALU_WORD1_OP3_SRC2_NEG_SIZE;
1222 unsigned int src2_chan : SQ_ALU_WORD1_OP3_SRC2_CHAN_SIZE;
1223 unsigned int src2_rel : SQ_ALU_WORD1_OP3_SRC2_REL_SIZE;
1224 unsigned int src2_sel : SQ_ALU_WORD1_OP3_SRC2_SEL_SIZE;
1225 } sq_alu_word1_op3_t;
1226
1227 #endif
1228
1229 typedef union {
1230 unsigned int val : 32;
1231 sq_alu_word1_op3_t f;
1232 } sq_alu_word1_op3_u;
1233
1234
1235 /*
1236 * SQ_TEX_WORD0 struct
1237 */
1238
1239 #define SQ_TEX_WORD0_TEX_INST_SIZE 5
1240 #define SQ_TEX_WORD0_BC_FRAC_MODE_SIZE 1
1241 #define SQ_TEX_WORD0_FETCH_WHOLE_QUAD_SIZE 1
1242 #define SQ_TEX_WORD0_RESOURCE_ID_SIZE 8
1243 #define SQ_TEX_WORD0_SRC_GPR_SIZE 7
1244 #define SQ_TEX_WORD0_SRC_REL_SIZE 1
1245 #define SQ_TEX_WORD0_ALT_CONST_SIZE 1
1246
1247 #define SQ_TEX_WORD0_TEX_INST_SHIFT 0
1248 #define SQ_TEX_WORD0_BC_FRAC_MODE_SHIFT 5
1249 #define SQ_TEX_WORD0_FETCH_WHOLE_QUAD_SHIFT 7
1250 #define SQ_TEX_WORD0_RESOURCE_ID_SHIFT 8
1251 #define SQ_TEX_WORD0_SRC_GPR_SHIFT 16
1252 #define SQ_TEX_WORD0_SRC_REL_SHIFT 23
1253 #define SQ_TEX_WORD0_ALT_CONST_SHIFT 24
1254
1255 #define SQ_TEX_WORD0_TEX_INST_MASK 0x0000001f
1256 #define SQ_TEX_WORD0_BC_FRAC_MODE_MASK 0x00000020
1257 #define SQ_TEX_WORD0_FETCH_WHOLE_QUAD_MASK 0x00000080
1258 #define SQ_TEX_WORD0_RESOURCE_ID_MASK 0x0000ff00
1259 #define SQ_TEX_WORD0_SRC_GPR_MASK 0x007f0000
1260 #define SQ_TEX_WORD0_SRC_REL_MASK 0x00800000
1261 #define SQ_TEX_WORD0_ALT_CONST_MASK 0x01000000
1262
1263 #define SQ_TEX_WORD0_MASK \
1264 (SQ_TEX_WORD0_TEX_INST_MASK | \
1265 SQ_TEX_WORD0_BC_FRAC_MODE_MASK | \
1266 SQ_TEX_WORD0_FETCH_WHOLE_QUAD_MASK | \
1267 SQ_TEX_WORD0_RESOURCE_ID_MASK | \
1268 SQ_TEX_WORD0_SRC_GPR_MASK | \
1269 SQ_TEX_WORD0_SRC_REL_MASK | \
1270 SQ_TEX_WORD0_ALT_CONST_MASK)
1271
1272 #define SQ_TEX_WORD0_DEFAULT 0x01cdcd8d
1273
1274 #define SQ_TEX_WORD0_GET_TEX_INST(sq_tex_word0) \
1275 ((sq_tex_word0 & SQ_TEX_WORD0_TEX_INST_MASK) >> SQ_TEX_WORD0_TEX_INST_SHIFT)
1276 #define SQ_TEX_WORD0_GET_BC_FRAC_MODE(sq_tex_word0) \
1277 ((sq_tex_word0 & SQ_TEX_WORD0_BC_FRAC_MODE_MASK) >> SQ_TEX_WORD0_BC_FRAC_MODE_SHIFT)
1278 #define SQ_TEX_WORD0_GET_FETCH_WHOLE_QUAD(sq_tex_word0) \
1279 ((sq_tex_word0 & SQ_TEX_WORD0_FETCH_WHOLE_QUAD_MASK) >> SQ_TEX_WORD0_FETCH_WHOLE_QUAD_SHIFT)
1280 #define SQ_TEX_WORD0_GET_RESOURCE_ID(sq_tex_word0) \
1281 ((sq_tex_word0 & SQ_TEX_WORD0_RESOURCE_ID_MASK) >> SQ_TEX_WORD0_RESOURCE_ID_SHIFT)
1282 #define SQ_TEX_WORD0_GET_SRC_GPR(sq_tex_word0) \
1283 ((sq_tex_word0 & SQ_TEX_WORD0_SRC_GPR_MASK) >> SQ_TEX_WORD0_SRC_GPR_SHIFT)
1284 #define SQ_TEX_WORD0_GET_SRC_REL(sq_tex_word0) \
1285 ((sq_tex_word0 & SQ_TEX_WORD0_SRC_REL_MASK) >> SQ_TEX_WORD0_SRC_REL_SHIFT)
1286 #define SQ_TEX_WORD0_GET_ALT_CONST(sq_tex_word0) \
1287 ((sq_tex_word0 & SQ_TEX_WORD0_ALT_CONST_MASK) >> SQ_TEX_WORD0_ALT_CONST_SHIFT)
1288
1289 #define SQ_TEX_WORD0_SET_TEX_INST(sq_tex_word0_reg, tex_inst) \
1290 sq_tex_word0_reg = (sq_tex_word0_reg & ~SQ_TEX_WORD0_TEX_INST_MASK) | (tex_inst << SQ_TEX_WORD0_TEX_INST_SHIFT)
1291 #define SQ_TEX_WORD0_SET_BC_FRAC_MODE(sq_tex_word0_reg, bc_frac_mode) \
1292 sq_tex_word0_reg = (sq_tex_word0_reg & ~SQ_TEX_WORD0_BC_FRAC_MODE_MASK) | (bc_frac_mode << SQ_TEX_WORD0_BC_FRAC_MODE_SHIFT)
1293 #define SQ_TEX_WORD0_SET_FETCH_WHOLE_QUAD(sq_tex_word0_reg, fetch_whole_quad) \
1294 sq_tex_word0_reg = (sq_tex_word0_reg & ~SQ_TEX_WORD0_FETCH_WHOLE_QUAD_MASK) | (fetch_whole_quad << SQ_TEX_WORD0_FETCH_WHOLE_QUAD_SHIFT)
1295 #define SQ_TEX_WORD0_SET_RESOURCE_ID(sq_tex_word0_reg, resource_id) \
1296 sq_tex_word0_reg = (sq_tex_word0_reg & ~SQ_TEX_WORD0_RESOURCE_ID_MASK) | (resource_id << SQ_TEX_WORD0_RESOURCE_ID_SHIFT)
1297 #define SQ_TEX_WORD0_SET_SRC_GPR(sq_tex_word0_reg, src_gpr) \
1298 sq_tex_word0_reg = (sq_tex_word0_reg & ~SQ_TEX_WORD0_SRC_GPR_MASK) | (src_gpr << SQ_TEX_WORD0_SRC_GPR_SHIFT)
1299 #define SQ_TEX_WORD0_SET_SRC_REL(sq_tex_word0_reg, src_rel) \
1300 sq_tex_word0_reg = (sq_tex_word0_reg & ~SQ_TEX_WORD0_SRC_REL_MASK) | (src_rel << SQ_TEX_WORD0_SRC_REL_SHIFT)
1301 #define SQ_TEX_WORD0_SET_ALT_CONST(sq_tex_word0_reg, alt_const) \
1302 sq_tex_word0_reg = (sq_tex_word0_reg & ~SQ_TEX_WORD0_ALT_CONST_MASK) | (alt_const << SQ_TEX_WORD0_ALT_CONST_SHIFT)
1303
1304 #if defined(LITTLEENDIAN_CPU)
1305
1306 typedef struct _sq_tex_word0_t {
1307 unsigned int tex_inst : SQ_TEX_WORD0_TEX_INST_SIZE;
1308 unsigned int bc_frac_mode : SQ_TEX_WORD0_BC_FRAC_MODE_SIZE;
1309 unsigned int : 1;
1310 unsigned int fetch_whole_quad : SQ_TEX_WORD0_FETCH_WHOLE_QUAD_SIZE;
1311 unsigned int resource_id : SQ_TEX_WORD0_RESOURCE_ID_SIZE;
1312 unsigned int src_gpr : SQ_TEX_WORD0_SRC_GPR_SIZE;
1313 unsigned int src_rel : SQ_TEX_WORD0_SRC_REL_SIZE;
1314 unsigned int alt_const : SQ_TEX_WORD0_ALT_CONST_SIZE;
1315 unsigned int : 7;
1316 } sq_tex_word0_t;
1317
1318 #elif defined(BIGENDIAN_CPU)
1319
1320 typedef struct _sq_tex_word0_t {
1321 unsigned int : 7;
1322 unsigned int alt_const : SQ_TEX_WORD0_ALT_CONST_SIZE;
1323 unsigned int src_rel : SQ_TEX_WORD0_SRC_REL_SIZE;
1324 unsigned int src_gpr : SQ_TEX_WORD0_SRC_GPR_SIZE;
1325 unsigned int resource_id : SQ_TEX_WORD0_RESOURCE_ID_SIZE;
1326 unsigned int fetch_whole_quad : SQ_TEX_WORD0_FETCH_WHOLE_QUAD_SIZE;
1327 unsigned int : 1;
1328 unsigned int bc_frac_mode : SQ_TEX_WORD0_BC_FRAC_MODE_SIZE;
1329 unsigned int tex_inst : SQ_TEX_WORD0_TEX_INST_SIZE;
1330 } sq_tex_word0_t;
1331
1332 #endif
1333
1334 typedef union {
1335 unsigned int val : 32;
1336 sq_tex_word0_t f;
1337 } sq_tex_word0_u;
1338
1339
1340 /*
1341 * SQ_TEX_WORD1 struct
1342 */
1343
1344 #define SQ_TEX_WORD1_DST_GPR_SIZE 7
1345 #define SQ_TEX_WORD1_DST_REL_SIZE 1
1346 #define SQ_TEX_WORD1_DST_SEL_X_SIZE 3
1347 #define SQ_TEX_WORD1_DST_SEL_Y_SIZE 3
1348 #define SQ_TEX_WORD1_DST_SEL_Z_SIZE 3
1349 #define SQ_TEX_WORD1_DST_SEL_W_SIZE 3
1350 #define SQ_TEX_WORD1_LOD_BIAS_SIZE 7
1351 #define SQ_TEX_WORD1_COORD_TYPE_X_SIZE 1
1352 #define SQ_TEX_WORD1_COORD_TYPE_Y_SIZE 1
1353 #define SQ_TEX_WORD1_COORD_TYPE_Z_SIZE 1
1354 #define SQ_TEX_WORD1_COORD_TYPE_W_SIZE 1
1355
1356 #define SQ_TEX_WORD1_DST_GPR_SHIFT 0
1357 #define SQ_TEX_WORD1_DST_REL_SHIFT 7
1358 #define SQ_TEX_WORD1_DST_SEL_X_SHIFT 9
1359 #define SQ_TEX_WORD1_DST_SEL_Y_SHIFT 12
1360 #define SQ_TEX_WORD1_DST_SEL_Z_SHIFT 15
1361 #define SQ_TEX_WORD1_DST_SEL_W_SHIFT 18
1362 #define SQ_TEX_WORD1_LOD_BIAS_SHIFT 21
1363 #define SQ_TEX_WORD1_COORD_TYPE_X_SHIFT 28
1364 #define SQ_TEX_WORD1_COORD_TYPE_Y_SHIFT 29
1365 #define SQ_TEX_WORD1_COORD_TYPE_Z_SHIFT 30
1366 #define SQ_TEX_WORD1_COORD_TYPE_W_SHIFT 31
1367
1368 #define SQ_TEX_WORD1_DST_GPR_MASK 0x0000007f
1369 #define SQ_TEX_WORD1_DST_REL_MASK 0x00000080
1370 #define SQ_TEX_WORD1_DST_SEL_X_MASK 0x00000e00
1371 #define SQ_TEX_WORD1_DST_SEL_Y_MASK 0x00007000
1372 #define SQ_TEX_WORD1_DST_SEL_Z_MASK 0x00038000
1373 #define SQ_TEX_WORD1_DST_SEL_W_MASK 0x001c0000
1374 #define SQ_TEX_WORD1_LOD_BIAS_MASK 0x0fe00000
1375 #define SQ_TEX_WORD1_COORD_TYPE_X_MASK 0x10000000
1376 #define SQ_TEX_WORD1_COORD_TYPE_Y_MASK 0x20000000
1377 #define SQ_TEX_WORD1_COORD_TYPE_Z_MASK 0x40000000
1378 #define SQ_TEX_WORD1_COORD_TYPE_W_MASK 0x80000000
1379
1380 #define SQ_TEX_WORD1_MASK \
1381 (SQ_TEX_WORD1_DST_GPR_MASK | \
1382 SQ_TEX_WORD1_DST_REL_MASK | \
1383 SQ_TEX_WORD1_DST_SEL_X_MASK | \
1384 SQ_TEX_WORD1_DST_SEL_Y_MASK | \
1385 SQ_TEX_WORD1_DST_SEL_Z_MASK | \
1386 SQ_TEX_WORD1_DST_SEL_W_MASK | \
1387 SQ_TEX_WORD1_LOD_BIAS_MASK | \
1388 SQ_TEX_WORD1_COORD_TYPE_X_MASK | \
1389 SQ_TEX_WORD1_COORD_TYPE_Y_MASK | \
1390 SQ_TEX_WORD1_COORD_TYPE_Z_MASK | \
1391 SQ_TEX_WORD1_COORD_TYPE_W_MASK)
1392
1393 #define SQ_TEX_WORD1_DEFAULT 0xcdcdcccd
1394
1395 #define SQ_TEX_WORD1_GET_DST_GPR(sq_tex_word1) \
1396 ((sq_tex_word1 & SQ_TEX_WORD1_DST_GPR_MASK) >> SQ_TEX_WORD1_DST_GPR_SHIFT)
1397 #define SQ_TEX_WORD1_GET_DST_REL(sq_tex_word1) \
1398 ((sq_tex_word1 & SQ_TEX_WORD1_DST_REL_MASK) >> SQ_TEX_WORD1_DST_REL_SHIFT)
1399 #define SQ_TEX_WORD1_GET_DST_SEL_X(sq_tex_word1) \
1400 ((sq_tex_word1 & SQ_TEX_WORD1_DST_SEL_X_MASK) >> SQ_TEX_WORD1_DST_SEL_X_SHIFT)
1401 #define SQ_TEX_WORD1_GET_DST_SEL_Y(sq_tex_word1) \
1402 ((sq_tex_word1 & SQ_TEX_WORD1_DST_SEL_Y_MASK) >> SQ_TEX_WORD1_DST_SEL_Y_SHIFT)
1403 #define SQ_TEX_WORD1_GET_DST_SEL_Z(sq_tex_word1) \
1404 ((sq_tex_word1 & SQ_TEX_WORD1_DST_SEL_Z_MASK) >> SQ_TEX_WORD1_DST_SEL_Z_SHIFT)
1405 #define SQ_TEX_WORD1_GET_DST_SEL_W(sq_tex_word1) \
1406 ((sq_tex_word1 & SQ_TEX_WORD1_DST_SEL_W_MASK) >> SQ_TEX_WORD1_DST_SEL_W_SHIFT)
1407 #define SQ_TEX_WORD1_GET_LOD_BIAS(sq_tex_word1) \
1408 ((sq_tex_word1 & SQ_TEX_WORD1_LOD_BIAS_MASK) >> SQ_TEX_WORD1_LOD_BIAS_SHIFT)
1409 #define SQ_TEX_WORD1_GET_COORD_TYPE_X(sq_tex_word1) \
1410 ((sq_tex_word1 & SQ_TEX_WORD1_COORD_TYPE_X_MASK) >> SQ_TEX_WORD1_COORD_TYPE_X_SHIFT)
1411 #define SQ_TEX_WORD1_GET_COORD_TYPE_Y(sq_tex_word1) \
1412 ((sq_tex_word1 & SQ_TEX_WORD1_COORD_TYPE_Y_MASK) >> SQ_TEX_WORD1_COORD_TYPE_Y_SHIFT)
1413 #define SQ_TEX_WORD1_GET_COORD_TYPE_Z(sq_tex_word1) \
1414 ((sq_tex_word1 & SQ_TEX_WORD1_COORD_TYPE_Z_MASK) >> SQ_TEX_WORD1_COORD_TYPE_Z_SHIFT)
1415 #define SQ_TEX_WORD1_GET_COORD_TYPE_W(sq_tex_word1) \
1416 ((sq_tex_word1 & SQ_TEX_WORD1_COORD_TYPE_W_MASK) >> SQ_TEX_WORD1_COORD_TYPE_W_SHIFT)
1417
1418 #define SQ_TEX_WORD1_SET_DST_GPR(sq_tex_word1_reg, dst_gpr) \
1419 sq_tex_word1_reg = (sq_tex_word1_reg & ~SQ_TEX_WORD1_DST_GPR_MASK) | (dst_gpr << SQ_TEX_WORD1_DST_GPR_SHIFT)
1420 #define SQ_TEX_WORD1_SET_DST_REL(sq_tex_word1_reg, dst_rel) \
1421 sq_tex_word1_reg = (sq_tex_word1_reg & ~SQ_TEX_WORD1_DST_REL_MASK) | (dst_rel << SQ_TEX_WORD1_DST_REL_SHIFT)
1422 #define SQ_TEX_WORD1_SET_DST_SEL_X(sq_tex_word1_reg, dst_sel_x) \
1423 sq_tex_word1_reg = (sq_tex_word1_reg & ~SQ_TEX_WORD1_DST_SEL_X_MASK) | (dst_sel_x << SQ_TEX_WORD1_DST_SEL_X_SHIFT)
1424 #define SQ_TEX_WORD1_SET_DST_SEL_Y(sq_tex_word1_reg, dst_sel_y) \
1425 sq_tex_word1_reg = (sq_tex_word1_reg & ~SQ_TEX_WORD1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_TEX_WORD1_DST_SEL_Y_SHIFT)
1426 #define SQ_TEX_WORD1_SET_DST_SEL_Z(sq_tex_word1_reg, dst_sel_z) \
1427 sq_tex_word1_reg = (sq_tex_word1_reg & ~SQ_TEX_WORD1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_TEX_WORD1_DST_SEL_Z_SHIFT)
1428 #define SQ_TEX_WORD1_SET_DST_SEL_W(sq_tex_word1_reg, dst_sel_w) \
1429 sq_tex_word1_reg = (sq_tex_word1_reg & ~SQ_TEX_WORD1_DST_SEL_W_MASK) | (dst_sel_w << SQ_TEX_WORD1_DST_SEL_W_SHIFT)
1430 #define SQ_TEX_WORD1_SET_LOD_BIAS(sq_tex_word1_reg, lod_bias) \
1431 sq_tex_word1_reg = (sq_tex_word1_reg & ~SQ_TEX_WORD1_LOD_BIAS_MASK) | (lod_bias << SQ_TEX_WORD1_LOD_BIAS_SHIFT)
1432 #define SQ_TEX_WORD1_SET_COORD_TYPE_X(sq_tex_word1_reg, coord_type_x) \
1433 sq_tex_word1_reg = (sq_tex_word1_reg & ~SQ_TEX_WORD1_COORD_TYPE_X_MASK) | (coord_type_x << SQ_TEX_WORD1_COORD_TYPE_X_SHIFT)
1434 #define SQ_TEX_WORD1_SET_COORD_TYPE_Y(sq_tex_word1_reg, coord_type_y) \
1435 sq_tex_word1_reg = (sq_tex_word1_reg & ~SQ_TEX_WORD1_COORD_TYPE_Y_MASK) | (coord_type_y << SQ_TEX_WORD1_COORD_TYPE_Y_SHIFT)
1436 #define SQ_TEX_WORD1_SET_COORD_TYPE_Z(sq_tex_word1_reg, coord_type_z) \
1437 sq_tex_word1_reg = (sq_tex_word1_reg & ~SQ_TEX_WORD1_COORD_TYPE_Z_MASK) | (coord_type_z << SQ_TEX_WORD1_COORD_TYPE_Z_SHIFT)
1438 #define SQ_TEX_WORD1_SET_COORD_TYPE_W(sq_tex_word1_reg, coord_type_w) \
1439 sq_tex_word1_reg = (sq_tex_word1_reg & ~SQ_TEX_WORD1_COORD_TYPE_W_MASK) | (coord_type_w << SQ_TEX_WORD1_COORD_TYPE_W_SHIFT)
1440
1441 #if defined(LITTLEENDIAN_CPU)
1442
1443 typedef struct _sq_tex_word1_t {
1444 unsigned int dst_gpr : SQ_TEX_WORD1_DST_GPR_SIZE;
1445 unsigned int dst_rel : SQ_TEX_WORD1_DST_REL_SIZE;
1446 unsigned int : 1;
1447 unsigned int dst_sel_x : SQ_TEX_WORD1_DST_SEL_X_SIZE;
1448 unsigned int dst_sel_y : SQ_TEX_WORD1_DST_SEL_Y_SIZE;
1449 unsigned int dst_sel_z : SQ_TEX_WORD1_DST_SEL_Z_SIZE;
1450 unsigned int dst_sel_w : SQ_TEX_WORD1_DST_SEL_W_SIZE;
1451 unsigned int lod_bias : SQ_TEX_WORD1_LOD_BIAS_SIZE;
1452 unsigned int coord_type_x : SQ_TEX_WORD1_COORD_TYPE_X_SIZE;
1453 unsigned int coord_type_y : SQ_TEX_WORD1_COORD_TYPE_Y_SIZE;
1454 unsigned int coord_type_z : SQ_TEX_WORD1_COORD_TYPE_Z_SIZE;
1455 unsigned int coord_type_w : SQ_TEX_WORD1_COORD_TYPE_W_SIZE;
1456 } sq_tex_word1_t;
1457
1458 #elif defined(BIGENDIAN_CPU)
1459
1460 typedef struct _sq_tex_word1_t {
1461 unsigned int coord_type_w : SQ_TEX_WORD1_COORD_TYPE_W_SIZE;
1462 unsigned int coord_type_z : SQ_TEX_WORD1_COORD_TYPE_Z_SIZE;
1463 unsigned int coord_type_y : SQ_TEX_WORD1_COORD_TYPE_Y_SIZE;
1464 unsigned int coord_type_x : SQ_TEX_WORD1_COORD_TYPE_X_SIZE;
1465 unsigned int lod_bias : SQ_TEX_WORD1_LOD_BIAS_SIZE;
1466 unsigned int dst_sel_w : SQ_TEX_WORD1_DST_SEL_W_SIZE;
1467 unsigned int dst_sel_z : SQ_TEX_WORD1_DST_SEL_Z_SIZE;
1468 unsigned int dst_sel_y : SQ_TEX_WORD1_DST_SEL_Y_SIZE;
1469 unsigned int dst_sel_x : SQ_TEX_WORD1_DST_SEL_X_SIZE;
1470 unsigned int : 1;
1471 unsigned int dst_rel : SQ_TEX_WORD1_DST_REL_SIZE;
1472 unsigned int dst_gpr : SQ_TEX_WORD1_DST_GPR_SIZE;
1473 } sq_tex_word1_t;
1474
1475 #endif
1476
1477 typedef union {
1478 unsigned int val : 32;
1479 sq_tex_word1_t f;
1480 } sq_tex_word1_u;
1481
1482
1483 /*
1484 * SQ_TEX_WORD2 struct
1485 */
1486
1487 #define SQ_TEX_WORD2_OFFSET_X_SIZE 5
1488 #define SQ_TEX_WORD2_OFFSET_Y_SIZE 5
1489 #define SQ_TEX_WORD2_OFFSET_Z_SIZE 5
1490 #define SQ_TEX_WORD2_SAMPLER_ID_SIZE 5
1491 #define SQ_TEX_WORD2_SRC_SEL_X_SIZE 3
1492 #define SQ_TEX_WORD2_SRC_SEL_Y_SIZE 3
1493 #define SQ_TEX_WORD2_SRC_SEL_Z_SIZE 3
1494 #define SQ_TEX_WORD2_SRC_SEL_W_SIZE 3
1495
1496 #define SQ_TEX_WORD2_OFFSET_X_SHIFT 0
1497 #define SQ_TEX_WORD2_OFFSET_Y_SHIFT 5
1498 #define SQ_TEX_WORD2_OFFSET_Z_SHIFT 10
1499 #define SQ_TEX_WORD2_SAMPLER_ID_SHIFT 15
1500 #define SQ_TEX_WORD2_SRC_SEL_X_SHIFT 20
1501 #define SQ_TEX_WORD2_SRC_SEL_Y_SHIFT 23
1502 #define SQ_TEX_WORD2_SRC_SEL_Z_SHIFT 26
1503 #define SQ_TEX_WORD2_SRC_SEL_W_SHIFT 29
1504
1505 #define SQ_TEX_WORD2_OFFSET_X_MASK 0x0000001f
1506 #define SQ_TEX_WORD2_OFFSET_Y_MASK 0x000003e0
1507 #define SQ_TEX_WORD2_OFFSET_Z_MASK 0x00007c00
1508 #define SQ_TEX_WORD2_SAMPLER_ID_MASK 0x000f8000
1509 #define SQ_TEX_WORD2_SRC_SEL_X_MASK 0x00700000
1510 #define SQ_TEX_WORD2_SRC_SEL_Y_MASK 0x03800000
1511 #define SQ_TEX_WORD2_SRC_SEL_Z_MASK 0x1c000000
1512 #define SQ_TEX_WORD2_SRC_SEL_W_MASK 0xe0000000
1513
1514 #define SQ_TEX_WORD2_MASK \
1515 (SQ_TEX_WORD2_OFFSET_X_MASK | \
1516 SQ_TEX_WORD2_OFFSET_Y_MASK | \
1517 SQ_TEX_WORD2_OFFSET_Z_MASK | \
1518 SQ_TEX_WORD2_SAMPLER_ID_MASK | \
1519 SQ_TEX_WORD2_SRC_SEL_X_MASK | \
1520 SQ_TEX_WORD2_SRC_SEL_Y_MASK | \
1521 SQ_TEX_WORD2_SRC_SEL_Z_MASK | \
1522 SQ_TEX_WORD2_SRC_SEL_W_MASK)
1523
1524 #define SQ_TEX_WORD2_DEFAULT 0xcdcdcdcd
1525
1526 #define SQ_TEX_WORD2_GET_OFFSET_X(sq_tex_word2) \
1527 ((sq_tex_word2 & SQ_TEX_WORD2_OFFSET_X_MASK) >> SQ_TEX_WORD2_OFFSET_X_SHIFT)
1528 #define SQ_TEX_WORD2_GET_OFFSET_Y(sq_tex_word2) \
1529 ((sq_tex_word2 & SQ_TEX_WORD2_OFFSET_Y_MASK) >> SQ_TEX_WORD2_OFFSET_Y_SHIFT)
1530 #define SQ_TEX_WORD2_GET_OFFSET_Z(sq_tex_word2) \
1531 ((sq_tex_word2 & SQ_TEX_WORD2_OFFSET_Z_MASK) >> SQ_TEX_WORD2_OFFSET_Z_SHIFT)
1532 #define SQ_TEX_WORD2_GET_SAMPLER_ID(sq_tex_word2) \
1533 ((sq_tex_word2 & SQ_TEX_WORD2_SAMPLER_ID_MASK) >> SQ_TEX_WORD2_SAMPLER_ID_SHIFT)
1534 #define SQ_TEX_WORD2_GET_SRC_SEL_X(sq_tex_word2) \
1535 ((sq_tex_word2 & SQ_TEX_WORD2_SRC_SEL_X_MASK) >> SQ_TEX_WORD2_SRC_SEL_X_SHIFT)
1536 #define SQ_TEX_WORD2_GET_SRC_SEL_Y(sq_tex_word2) \
1537 ((sq_tex_word2 & SQ_TEX_WORD2_SRC_SEL_Y_MASK) >> SQ_TEX_WORD2_SRC_SEL_Y_SHIFT)
1538 #define SQ_TEX_WORD2_GET_SRC_SEL_Z(sq_tex_word2) \
1539 ((sq_tex_word2 & SQ_TEX_WORD2_SRC_SEL_Z_MASK) >> SQ_TEX_WORD2_SRC_SEL_Z_SHIFT)
1540 #define SQ_TEX_WORD2_GET_SRC_SEL_W(sq_tex_word2) \
1541 ((sq_tex_word2 & SQ_TEX_WORD2_SRC_SEL_W_MASK) >> SQ_TEX_WORD2_SRC_SEL_W_SHIFT)
1542
1543 #define SQ_TEX_WORD2_SET_OFFSET_X(sq_tex_word2_reg, offset_x) \
1544 sq_tex_word2_reg = (sq_tex_word2_reg & ~SQ_TEX_WORD2_OFFSET_X_MASK) | (offset_x << SQ_TEX_WORD2_OFFSET_X_SHIFT)
1545 #define SQ_TEX_WORD2_SET_OFFSET_Y(sq_tex_word2_reg, offset_y) \
1546 sq_tex_word2_reg = (sq_tex_word2_reg & ~SQ_TEX_WORD2_OFFSET_Y_MASK) | (offset_y << SQ_TEX_WORD2_OFFSET_Y_SHIFT)
1547 #define SQ_TEX_WORD2_SET_OFFSET_Z(sq_tex_word2_reg, offset_z) \
1548 sq_tex_word2_reg = (sq_tex_word2_reg & ~SQ_TEX_WORD2_OFFSET_Z_MASK) | (offset_z << SQ_TEX_WORD2_OFFSET_Z_SHIFT)
1549 #define SQ_TEX_WORD2_SET_SAMPLER_ID(sq_tex_word2_reg, sampler_id) \
1550 sq_tex_word2_reg = (sq_tex_word2_reg & ~SQ_TEX_WORD2_SAMPLER_ID_MASK) | (sampler_id << SQ_TEX_WORD2_SAMPLER_ID_SHIFT)
1551 #define SQ_TEX_WORD2_SET_SRC_SEL_X(sq_tex_word2_reg, src_sel_x) \
1552 sq_tex_word2_reg = (sq_tex_word2_reg & ~SQ_TEX_WORD2_SRC_SEL_X_MASK) | (src_sel_x << SQ_TEX_WORD2_SRC_SEL_X_SHIFT)
1553 #define SQ_TEX_WORD2_SET_SRC_SEL_Y(sq_tex_word2_reg, src_sel_y) \
1554 sq_tex_word2_reg = (sq_tex_word2_reg & ~SQ_TEX_WORD2_SRC_SEL_Y_MASK) | (src_sel_y << SQ_TEX_WORD2_SRC_SEL_Y_SHIFT)
1555 #define SQ_TEX_WORD2_SET_SRC_SEL_Z(sq_tex_word2_reg, src_sel_z) \
1556 sq_tex_word2_reg = (sq_tex_word2_reg & ~SQ_TEX_WORD2_SRC_SEL_Z_MASK) | (src_sel_z << SQ_TEX_WORD2_SRC_SEL_Z_SHIFT)
1557 #define SQ_TEX_WORD2_SET_SRC_SEL_W(sq_tex_word2_reg, src_sel_w) \
1558 sq_tex_word2_reg = (sq_tex_word2_reg & ~SQ_TEX_WORD2_SRC_SEL_W_MASK) | (src_sel_w << SQ_TEX_WORD2_SRC_SEL_W_SHIFT)
1559
1560 #if defined(LITTLEENDIAN_CPU)
1561
1562 typedef struct _sq_tex_word2_t {
1563 unsigned int offset_x : SQ_TEX_WORD2_OFFSET_X_SIZE;
1564 unsigned int offset_y : SQ_TEX_WORD2_OFFSET_Y_SIZE;
1565 unsigned int offset_z : SQ_TEX_WORD2_OFFSET_Z_SIZE;
1566 unsigned int sampler_id : SQ_TEX_WORD2_SAMPLER_ID_SIZE;
1567 unsigned int src_sel_x : SQ_TEX_WORD2_SRC_SEL_X_SIZE;
1568 unsigned int src_sel_y : SQ_TEX_WORD2_SRC_SEL_Y_SIZE;
1569 unsigned int src_sel_z : SQ_TEX_WORD2_SRC_SEL_Z_SIZE;
1570 unsigned int src_sel_w : SQ_TEX_WORD2_SRC_SEL_W_SIZE;
1571 } sq_tex_word2_t;
1572
1573 #elif defined(BIGENDIAN_CPU)
1574
1575 typedef struct _sq_tex_word2_t {
1576 unsigned int src_sel_w : SQ_TEX_WORD2_SRC_SEL_W_SIZE;
1577 unsigned int src_sel_z : SQ_TEX_WORD2_SRC_SEL_Z_SIZE;
1578 unsigned int src_sel_y : SQ_TEX_WORD2_SRC_SEL_Y_SIZE;
1579 unsigned int src_sel_x : SQ_TEX_WORD2_SRC_SEL_X_SIZE;
1580 unsigned int sampler_id : SQ_TEX_WORD2_SAMPLER_ID_SIZE;
1581 unsigned int offset_z : SQ_TEX_WORD2_OFFSET_Z_SIZE;
1582 unsigned int offset_y : SQ_TEX_WORD2_OFFSET_Y_SIZE;
1583 unsigned int offset_x : SQ_TEX_WORD2_OFFSET_X_SIZE;
1584 } sq_tex_word2_t;
1585
1586 #endif
1587
1588 typedef union {
1589 unsigned int val : 32;
1590 sq_tex_word2_t f;
1591 } sq_tex_word2_u;
1592
1593
1594 /*
1595 * SQ_VTX_WORD0 struct
1596 */
1597
1598 #define SQ_VTX_WORD0_VTX_INST_SIZE 5
1599 #define SQ_VTX_WORD0_FETCH_TYPE_SIZE 2
1600 #define SQ_VTX_WORD0_FETCH_WHOLE_QUAD_SIZE 1
1601 #define SQ_VTX_WORD0_BUFFER_ID_SIZE 8
1602 #define SQ_VTX_WORD0_SRC_GPR_SIZE 7
1603 #define SQ_VTX_WORD0_SRC_REL_SIZE 1
1604 #define SQ_VTX_WORD0_SRC_SEL_X_SIZE 2
1605 #define SQ_VTX_WORD0_MEGA_FETCH_COUNT_SIZE 6
1606
1607 #define SQ_VTX_WORD0_VTX_INST_SHIFT 0
1608 #define SQ_VTX_WORD0_FETCH_TYPE_SHIFT 5
1609 #define SQ_VTX_WORD0_FETCH_WHOLE_QUAD_SHIFT 7
1610 #define SQ_VTX_WORD0_BUFFER_ID_SHIFT 8
1611 #define SQ_VTX_WORD0_SRC_GPR_SHIFT 16
1612 #define SQ_VTX_WORD0_SRC_REL_SHIFT 23
1613 #define SQ_VTX_WORD0_SRC_SEL_X_SHIFT 24
1614 #define SQ_VTX_WORD0_MEGA_FETCH_COUNT_SHIFT 26
1615
1616 #define SQ_VTX_WORD0_VTX_INST_MASK 0x0000001f
1617 #define SQ_VTX_WORD0_FETCH_TYPE_MASK 0x00000060
1618 #define SQ_VTX_WORD0_FETCH_WHOLE_QUAD_MASK 0x00000080
1619 #define SQ_VTX_WORD0_BUFFER_ID_MASK 0x0000ff00
1620 #define SQ_VTX_WORD0_SRC_GPR_MASK 0x007f0000
1621 #define SQ_VTX_WORD0_SRC_REL_MASK 0x00800000
1622 #define SQ_VTX_WORD0_SRC_SEL_X_MASK 0x03000000
1623 #define SQ_VTX_WORD0_MEGA_FETCH_COUNT_MASK 0xfc000000
1624
1625 #define SQ_VTX_WORD0_MASK \
1626 (SQ_VTX_WORD0_VTX_INST_MASK | \
1627 SQ_VTX_WORD0_FETCH_TYPE_MASK | \
1628 SQ_VTX_WORD0_FETCH_WHOLE_QUAD_MASK | \
1629 SQ_VTX_WORD0_BUFFER_ID_MASK | \
1630 SQ_VTX_WORD0_SRC_GPR_MASK | \
1631 SQ_VTX_WORD0_SRC_REL_MASK | \
1632 SQ_VTX_WORD0_SRC_SEL_X_MASK | \
1633 SQ_VTX_WORD0_MEGA_FETCH_COUNT_MASK)
1634
1635 #define SQ_VTX_WORD0_DEFAULT 0xcdcdcdcd
1636
1637 #define SQ_VTX_WORD0_GET_VTX_INST(sq_vtx_word0) \
1638 ((sq_vtx_word0 & SQ_VTX_WORD0_VTX_INST_MASK) >> SQ_VTX_WORD0_VTX_INST_SHIFT)
1639 #define SQ_VTX_WORD0_GET_FETCH_TYPE(sq_vtx_word0) \
1640 ((sq_vtx_word0 & SQ_VTX_WORD0_FETCH_TYPE_MASK) >> SQ_VTX_WORD0_FETCH_TYPE_SHIFT)
1641 #define SQ_VTX_WORD0_GET_FETCH_WHOLE_QUAD(sq_vtx_word0) \
1642 ((sq_vtx_word0 & SQ_VTX_WORD0_FETCH_WHOLE_QUAD_MASK) >> SQ_VTX_WORD0_FETCH_WHOLE_QUAD_SHIFT)
1643 #define SQ_VTX_WORD0_GET_BUFFER_ID(sq_vtx_word0) \
1644 ((sq_vtx_word0 & SQ_VTX_WORD0_BUFFER_ID_MASK) >> SQ_VTX_WORD0_BUFFER_ID_SHIFT)
1645 #define SQ_VTX_WORD0_GET_SRC_GPR(sq_vtx_word0) \
1646 ((sq_vtx_word0 & SQ_VTX_WORD0_SRC_GPR_MASK) >> SQ_VTX_WORD0_SRC_GPR_SHIFT)
1647 #define SQ_VTX_WORD0_GET_SRC_REL(sq_vtx_word0) \
1648 ((sq_vtx_word0 & SQ_VTX_WORD0_SRC_REL_MASK) >> SQ_VTX_WORD0_SRC_REL_SHIFT)
1649 #define SQ_VTX_WORD0_GET_SRC_SEL_X(sq_vtx_word0) \
1650 ((sq_vtx_word0 & SQ_VTX_WORD0_SRC_SEL_X_MASK) >> SQ_VTX_WORD0_SRC_SEL_X_SHIFT)
1651 #define SQ_VTX_WORD0_GET_MEGA_FETCH_COUNT(sq_vtx_word0) \
1652 ((sq_vtx_word0 & SQ_VTX_WORD0_MEGA_FETCH_COUNT_MASK) >> SQ_VTX_WORD0_MEGA_FETCH_COUNT_SHIFT)
1653
1654 #define SQ_VTX_WORD0_SET_VTX_INST(sq_vtx_word0_reg, vtx_inst) \
1655 sq_vtx_word0_reg = (sq_vtx_word0_reg & ~SQ_VTX_WORD0_VTX_INST_MASK) | (vtx_inst << SQ_VTX_WORD0_VTX_INST_SHIFT)
1656 #define SQ_VTX_WORD0_SET_FETCH_TYPE(sq_vtx_word0_reg, fetch_type) \
1657 sq_vtx_word0_reg = (sq_vtx_word0_reg & ~SQ_VTX_WORD0_FETCH_TYPE_MASK) | (fetch_type << SQ_VTX_WORD0_FETCH_TYPE_SHIFT)
1658 #define SQ_VTX_WORD0_SET_FETCH_WHOLE_QUAD(sq_vtx_word0_reg, fetch_whole_quad) \
1659 sq_vtx_word0_reg = (sq_vtx_word0_reg & ~SQ_VTX_WORD0_FETCH_WHOLE_QUAD_MASK) | (fetch_whole_quad << SQ_VTX_WORD0_FETCH_WHOLE_QUAD_SHIFT)
1660 #define SQ_VTX_WORD0_SET_BUFFER_ID(sq_vtx_word0_reg, buffer_id) \
1661 sq_vtx_word0_reg = (sq_vtx_word0_reg & ~SQ_VTX_WORD0_BUFFER_ID_MASK) | (buffer_id << SQ_VTX_WORD0_BUFFER_ID_SHIFT)
1662 #define SQ_VTX_WORD0_SET_SRC_GPR(sq_vtx_word0_reg, src_gpr) \
1663 sq_vtx_word0_reg = (sq_vtx_word0_reg & ~SQ_VTX_WORD0_SRC_GPR_MASK) | (src_gpr << SQ_VTX_WORD0_SRC_GPR_SHIFT)
1664 #define SQ_VTX_WORD0_SET_SRC_REL(sq_vtx_word0_reg, src_rel) \
1665 sq_vtx_word0_reg = (sq_vtx_word0_reg & ~SQ_VTX_WORD0_SRC_REL_MASK) | (src_rel << SQ_VTX_WORD0_SRC_REL_SHIFT)
1666 #define SQ_VTX_WORD0_SET_SRC_SEL_X(sq_vtx_word0_reg, src_sel_x) \
1667 sq_vtx_word0_reg = (sq_vtx_word0_reg & ~SQ_VTX_WORD0_SRC_SEL_X_MASK) | (src_sel_x << SQ_VTX_WORD0_SRC_SEL_X_SHIFT)
1668 #define SQ_VTX_WORD0_SET_MEGA_FETCH_COUNT(sq_vtx_word0_reg, mega_fetch_count) \
1669 sq_vtx_word0_reg = (sq_vtx_word0_reg & ~SQ_VTX_WORD0_MEGA_FETCH_COUNT_MASK) | (mega_fetch_count << SQ_VTX_WORD0_MEGA_FETCH_COUNT_SHIFT)
1670
1671 #if defined(LITTLEENDIAN_CPU)
1672
1673 typedef struct _sq_vtx_word0_t {
1674 unsigned int vtx_inst : SQ_VTX_WORD0_VTX_INST_SIZE;
1675 unsigned int fetch_type : SQ_VTX_WORD0_FETCH_TYPE_SIZE;
1676 unsigned int fetch_whole_quad : SQ_VTX_WORD0_FETCH_WHOLE_QUAD_SIZE;
1677 unsigned int buffer_id : SQ_VTX_WORD0_BUFFER_ID_SIZE;
1678 unsigned int src_gpr : SQ_VTX_WORD0_SRC_GPR_SIZE;
1679 unsigned int src_rel : SQ_VTX_WORD0_SRC_REL_SIZE;
1680 unsigned int src_sel_x : SQ_VTX_WORD0_SRC_SEL_X_SIZE;
1681 unsigned int mega_fetch_count : SQ_VTX_WORD0_MEGA_FETCH_COUNT_SIZE;
1682 } sq_vtx_word0_t;
1683
1684 #elif defined(BIGENDIAN_CPU)
1685
1686 typedef struct _sq_vtx_word0_t {
1687 unsigned int mega_fetch_count : SQ_VTX_WORD0_MEGA_FETCH_COUNT_SIZE;
1688 unsigned int src_sel_x : SQ_VTX_WORD0_SRC_SEL_X_SIZE;
1689 unsigned int src_rel : SQ_VTX_WORD0_SRC_REL_SIZE;
1690 unsigned int src_gpr : SQ_VTX_WORD0_SRC_GPR_SIZE;
1691 unsigned int buffer_id : SQ_VTX_WORD0_BUFFER_ID_SIZE;
1692 unsigned int fetch_whole_quad : SQ_VTX_WORD0_FETCH_WHOLE_QUAD_SIZE;
1693 unsigned int fetch_type : SQ_VTX_WORD0_FETCH_TYPE_SIZE;
1694 unsigned int vtx_inst : SQ_VTX_WORD0_VTX_INST_SIZE;
1695 } sq_vtx_word0_t;
1696
1697 #endif
1698
1699 typedef union {
1700 unsigned int val : 32;
1701 sq_vtx_word0_t f;
1702 } sq_vtx_word0_u;
1703
1704
1705 /*
1706 * SQ_VTX_WORD1 struct
1707 */
1708
1709 #define SQ_VTX_WORD1_DST_SEL_X_SIZE 3
1710 #define SQ_VTX_WORD1_DST_SEL_Y_SIZE 3
1711 #define SQ_VTX_WORD1_DST_SEL_Z_SIZE 3
1712 #define SQ_VTX_WORD1_DST_SEL_W_SIZE 3
1713 #define SQ_VTX_WORD1_USE_CONST_FIELDS_SIZE 1
1714 #define SQ_VTX_WORD1_DATA_FORMAT_SIZE 6
1715 #define SQ_VTX_WORD1_NUM_FORMAT_ALL_SIZE 2
1716 #define SQ_VTX_WORD1_FORMAT_COMP_ALL_SIZE 1
1717 #define SQ_VTX_WORD1_SRF_MODE_ALL_SIZE 1
1718
1719 #define SQ_VTX_WORD1_DST_SEL_X_SHIFT 9
1720 #define SQ_VTX_WORD1_DST_SEL_Y_SHIFT 12
1721 #define SQ_VTX_WORD1_DST_SEL_Z_SHIFT 15
1722 #define SQ_VTX_WORD1_DST_SEL_W_SHIFT 18
1723 #define SQ_VTX_WORD1_USE_CONST_FIELDS_SHIFT 21
1724 #define SQ_VTX_WORD1_DATA_FORMAT_SHIFT 22
1725 #define SQ_VTX_WORD1_NUM_FORMAT_ALL_SHIFT 28
1726 #define SQ_VTX_WORD1_FORMAT_COMP_ALL_SHIFT 30
1727 #define SQ_VTX_WORD1_SRF_MODE_ALL_SHIFT 31
1728
1729 #define SQ_VTX_WORD1_DST_SEL_X_MASK 0x00000e00
1730 #define SQ_VTX_WORD1_DST_SEL_Y_MASK 0x00007000
1731 #define SQ_VTX_WORD1_DST_SEL_Z_MASK 0x00038000
1732 #define SQ_VTX_WORD1_DST_SEL_W_MASK 0x001c0000
1733 #define SQ_VTX_WORD1_USE_CONST_FIELDS_MASK 0x00200000
1734 #define SQ_VTX_WORD1_DATA_FORMAT_MASK 0x0fc00000
1735 #define SQ_VTX_WORD1_NUM_FORMAT_ALL_MASK 0x30000000
1736 #define SQ_VTX_WORD1_FORMAT_COMP_ALL_MASK 0x40000000
1737 #define SQ_VTX_WORD1_SRF_MODE_ALL_MASK 0x80000000
1738
1739 #define SQ_VTX_WORD1_MASK \
1740 (SQ_VTX_WORD1_DST_SEL_X_MASK | \
1741 SQ_VTX_WORD1_DST_SEL_Y_MASK | \
1742 SQ_VTX_WORD1_DST_SEL_Z_MASK | \
1743 SQ_VTX_WORD1_DST_SEL_W_MASK | \
1744 SQ_VTX_WORD1_USE_CONST_FIELDS_MASK | \
1745 SQ_VTX_WORD1_DATA_FORMAT_MASK | \
1746 SQ_VTX_WORD1_NUM_FORMAT_ALL_MASK | \
1747 SQ_VTX_WORD1_FORMAT_COMP_ALL_MASK | \
1748 SQ_VTX_WORD1_SRF_MODE_ALL_MASK)
1749
1750 #define SQ_VTX_WORD1_DEFAULT 0xcdcdcc00
1751
1752 #define SQ_VTX_WORD1_GET_DST_SEL_X(sq_vtx_word1) \
1753 ((sq_vtx_word1 & SQ_VTX_WORD1_DST_SEL_X_MASK) >> SQ_VTX_WORD1_DST_SEL_X_SHIFT)
1754 #define SQ_VTX_WORD1_GET_DST_SEL_Y(sq_vtx_word1) \
1755 ((sq_vtx_word1 & SQ_VTX_WORD1_DST_SEL_Y_MASK) >> SQ_VTX_WORD1_DST_SEL_Y_SHIFT)
1756 #define SQ_VTX_WORD1_GET_DST_SEL_Z(sq_vtx_word1) \
1757 ((sq_vtx_word1 & SQ_VTX_WORD1_DST_SEL_Z_MASK) >> SQ_VTX_WORD1_DST_SEL_Z_SHIFT)
1758 #define SQ_VTX_WORD1_GET_DST_SEL_W(sq_vtx_word1) \
1759 ((sq_vtx_word1 & SQ_VTX_WORD1_DST_SEL_W_MASK) >> SQ_VTX_WORD1_DST_SEL_W_SHIFT)
1760 #define SQ_VTX_WORD1_GET_USE_CONST_FIELDS(sq_vtx_word1) \
1761 ((sq_vtx_word1 & SQ_VTX_WORD1_USE_CONST_FIELDS_MASK) >> SQ_VTX_WORD1_USE_CONST_FIELDS_SHIFT)
1762 #define SQ_VTX_WORD1_GET_DATA_FORMAT(sq_vtx_word1) \
1763 ((sq_vtx_word1 & SQ_VTX_WORD1_DATA_FORMAT_MASK) >> SQ_VTX_WORD1_DATA_FORMAT_SHIFT)
1764 #define SQ_VTX_WORD1_GET_NUM_FORMAT_ALL(sq_vtx_word1) \
1765 ((sq_vtx_word1 & SQ_VTX_WORD1_NUM_FORMAT_ALL_MASK) >> SQ_VTX_WORD1_NUM_FORMAT_ALL_SHIFT)
1766 #define SQ_VTX_WORD1_GET_FORMAT_COMP_ALL(sq_vtx_word1) \
1767 ((sq_vtx_word1 & SQ_VTX_WORD1_FORMAT_COMP_ALL_MASK) >> SQ_VTX_WORD1_FORMAT_COMP_ALL_SHIFT)
1768 #define SQ_VTX_WORD1_GET_SRF_MODE_ALL(sq_vtx_word1) \
1769 ((sq_vtx_word1 & SQ_VTX_WORD1_SRF_MODE_ALL_MASK) >> SQ_VTX_WORD1_SRF_MODE_ALL_SHIFT)
1770
1771 #define SQ_VTX_WORD1_SET_DST_SEL_X(sq_vtx_word1_reg, dst_sel_x) \
1772 sq_vtx_word1_reg = (sq_vtx_word1_reg & ~SQ_VTX_WORD1_DST_SEL_X_MASK) | (dst_sel_x << SQ_VTX_WORD1_DST_SEL_X_SHIFT)
1773 #define SQ_VTX_WORD1_SET_DST_SEL_Y(sq_vtx_word1_reg, dst_sel_y) \
1774 sq_vtx_word1_reg = (sq_vtx_word1_reg & ~SQ_VTX_WORD1_DST_SEL_Y_MASK) | (dst_sel_y << SQ_VTX_WORD1_DST_SEL_Y_SHIFT)
1775 #define SQ_VTX_WORD1_SET_DST_SEL_Z(sq_vtx_word1_reg, dst_sel_z) \
1776 sq_vtx_word1_reg = (sq_vtx_word1_reg & ~SQ_VTX_WORD1_DST_SEL_Z_MASK) | (dst_sel_z << SQ_VTX_WORD1_DST_SEL_Z_SHIFT)
1777 #define SQ_VTX_WORD1_SET_DST_SEL_W(sq_vtx_word1_reg, dst_sel_w) \
1778 sq_vtx_word1_reg = (sq_vtx_word1_reg & ~SQ_VTX_WORD1_DST_SEL_W_MASK) | (dst_sel_w << SQ_VTX_WORD1_DST_SEL_W_SHIFT)
1779 #define SQ_VTX_WORD1_SET_USE_CONST_FIELDS(sq_vtx_word1_reg, use_const_fields) \
1780 sq_vtx_word1_reg = (sq_vtx_word1_reg & ~SQ_VTX_WORD1_USE_CONST_FIELDS_MASK) | (use_const_fields << SQ_VTX_WORD1_USE_CONST_FIELDS_SHIFT)
1781 #define SQ_VTX_WORD1_SET_DATA_FORMAT(sq_vtx_word1_reg, data_format) \
1782 sq_vtx_word1_reg = (sq_vtx_word1_reg & ~SQ_VTX_WORD1_DATA_FORMAT_MASK) | (data_format << SQ_VTX_WORD1_DATA_FORMAT_SHIFT)
1783 #define SQ_VTX_WORD1_SET_NUM_FORMAT_ALL(sq_vtx_word1_reg, num_format_all) \
1784 sq_vtx_word1_reg = (sq_vtx_word1_reg & ~SQ_VTX_WORD1_NUM_FORMAT_ALL_MASK) | (num_format_all << SQ_VTX_WORD1_NUM_FORMAT_ALL_SHIFT)
1785 #define SQ_VTX_WORD1_SET_FORMAT_COMP_ALL(sq_vtx_word1_reg, format_comp_all) \
1786 sq_vtx_word1_reg = (sq_vtx_word1_reg & ~SQ_VTX_WORD1_FORMAT_COMP_ALL_MASK) | (format_comp_all << SQ_VTX_WORD1_FORMAT_COMP_ALL_SHIFT)
1787 #define SQ_VTX_WORD1_SET_SRF_MODE_ALL(sq_vtx_word1_reg, srf_mode_all) \
1788 sq_vtx_word1_reg = (sq_vtx_word1_reg & ~SQ_VTX_WORD1_SRF_MODE_ALL_MASK) | (srf_mode_all << SQ_VTX_WORD1_SRF_MODE_ALL_SHIFT)
1789
1790 #if defined(LITTLEENDIAN_CPU)
1791
1792 typedef struct _sq_vtx_word1_t {
1793 unsigned int : 9;
1794 unsigned int dst_sel_x : SQ_VTX_WORD1_DST_SEL_X_SIZE;
1795 unsigned int dst_sel_y : SQ_VTX_WORD1_DST_SEL_Y_SIZE;
1796 unsigned int dst_sel_z : SQ_VTX_WORD1_DST_SEL_Z_SIZE;
1797 unsigned int dst_sel_w : SQ_VTX_WORD1_DST_SEL_W_SIZE;
1798 unsigned int use_const_fields : SQ_VTX_WORD1_USE_CONST_FIELDS_SIZE;
1799 unsigned int data_format : SQ_VTX_WORD1_DATA_FORMAT_SIZE;
1800 unsigned int num_format_all : SQ_VTX_WORD1_NUM_FORMAT_ALL_SIZE;
1801 unsigned int format_comp_all : SQ_VTX_WORD1_FORMAT_COMP_ALL_SIZE;
1802 unsigned int srf_mode_all : SQ_VTX_WORD1_SRF_MODE_ALL_SIZE;
1803 } sq_vtx_word1_t;
1804
1805 #elif defined(BIGENDIAN_CPU)
1806
1807 typedef struct _sq_vtx_word1_t {
1808 unsigned int srf_mode_all : SQ_VTX_WORD1_SRF_MODE_ALL_SIZE;
1809 unsigned int format_comp_all : SQ_VTX_WORD1_FORMAT_COMP_ALL_SIZE;
1810 unsigned int num_format_all : SQ_VTX_WORD1_NUM_FORMAT_ALL_SIZE;
1811 unsigned int data_format : SQ_VTX_WORD1_DATA_FORMAT_SIZE;
1812 unsigned int use_const_fields : SQ_VTX_WORD1_USE_CONST_FIELDS_SIZE;
1813 unsigned int dst_sel_w : SQ_VTX_WORD1_DST_SEL_W_SIZE;
1814 unsigned int dst_sel_z : SQ_VTX_WORD1_DST_SEL_Z_SIZE;
1815 unsigned int dst_sel_y : SQ_VTX_WORD1_DST_SEL_Y_SIZE;
1816 unsigned int dst_sel_x : SQ_VTX_WORD1_DST_SEL_X_SIZE;
1817 unsigned int : 9;
1818 } sq_vtx_word1_t;
1819
1820 #endif
1821
1822 typedef union {
1823 unsigned int val : 32;
1824 sq_vtx_word1_t f;
1825 } sq_vtx_word1_u;
1826
1827
1828 /*
1829 * SQ_VTX_WORD1_GPR struct
1830 */
1831
1832 #define SQ_VTX_WORD1_GPR_DST_GPR_SIZE 7
1833 #define SQ_VTX_WORD1_GPR_DST_REL_SIZE 1
1834
1835 #define SQ_VTX_WORD1_GPR_DST_GPR_SHIFT 0
1836 #define SQ_VTX_WORD1_GPR_DST_REL_SHIFT 7
1837
1838 #define SQ_VTX_WORD1_GPR_DST_GPR_MASK 0x0000007f
1839 #define SQ_VTX_WORD1_GPR_DST_REL_MASK 0x00000080
1840
1841 #define SQ_VTX_WORD1_GPR_MASK \
1842 (SQ_VTX_WORD1_GPR_DST_GPR_MASK | \
1843 SQ_VTX_WORD1_GPR_DST_REL_MASK)
1844
1845 #define SQ_VTX_WORD1_GPR_DEFAULT 0x000000cd
1846
1847 #define SQ_VTX_WORD1_GPR_GET_DST_GPR(sq_vtx_word1_gpr) \
1848 ((sq_vtx_word1_gpr & SQ_VTX_WORD1_GPR_DST_GPR_MASK) >> SQ_VTX_WORD1_GPR_DST_GPR_SHIFT)
1849 #define SQ_VTX_WORD1_GPR_GET_DST_REL(sq_vtx_word1_gpr) \
1850 ((sq_vtx_word1_gpr & SQ_VTX_WORD1_GPR_DST_REL_MASK) >> SQ_VTX_WORD1_GPR_DST_REL_SHIFT)
1851
1852 #define SQ_VTX_WORD1_GPR_SET_DST_GPR(sq_vtx_word1_gpr_reg, dst_gpr) \
1853 sq_vtx_word1_gpr_reg = (sq_vtx_word1_gpr_reg & ~SQ_VTX_WORD1_GPR_DST_GPR_MASK) | (dst_gpr << SQ_VTX_WORD1_GPR_DST_GPR_SHIFT)
1854 #define SQ_VTX_WORD1_GPR_SET_DST_REL(sq_vtx_word1_gpr_reg, dst_rel) \
1855 sq_vtx_word1_gpr_reg = (sq_vtx_word1_gpr_reg & ~SQ_VTX_WORD1_GPR_DST_REL_MASK) | (dst_rel << SQ_VTX_WORD1_GPR_DST_REL_SHIFT)
1856
1857 #if defined(LITTLEENDIAN_CPU)
1858
1859 typedef struct _sq_vtx_word1_gpr_t {
1860 unsigned int dst_gpr : SQ_VTX_WORD1_GPR_DST_GPR_SIZE;
1861 unsigned int dst_rel : SQ_VTX_WORD1_GPR_DST_REL_SIZE;
1862 unsigned int : 24;
1863 } sq_vtx_word1_gpr_t;
1864
1865 #elif defined(BIGENDIAN_CPU)
1866
1867 typedef struct _sq_vtx_word1_gpr_t {
1868 unsigned int : 24;
1869 unsigned int dst_rel : SQ_VTX_WORD1_GPR_DST_REL_SIZE;
1870 unsigned int dst_gpr : SQ_VTX_WORD1_GPR_DST_GPR_SIZE;
1871 } sq_vtx_word1_gpr_t;
1872
1873 #endif
1874
1875 typedef union {
1876 unsigned int val : 32;
1877 sq_vtx_word1_gpr_t f;
1878 } sq_vtx_word1_gpr_u;
1879
1880
1881 /*
1882 * SQ_VTX_WORD1_SEM struct
1883 */
1884
1885 #define SQ_VTX_WORD1_SEM_SEMANTIC_ID_SIZE 8
1886
1887 #define SQ_VTX_WORD1_SEM_SEMANTIC_ID_SHIFT 0
1888
1889 #define SQ_VTX_WORD1_SEM_SEMANTIC_ID_MASK 0x000000ff
1890
1891 #define SQ_VTX_WORD1_SEM_MASK \
1892 (SQ_VTX_WORD1_SEM_SEMANTIC_ID_MASK)
1893
1894 #define SQ_VTX_WORD1_SEM_DEFAULT 0x000000cd
1895
1896 #define SQ_VTX_WORD1_SEM_GET_SEMANTIC_ID(sq_vtx_word1_sem) \
1897 ((sq_vtx_word1_sem & SQ_VTX_WORD1_SEM_SEMANTIC_ID_MASK) >> SQ_VTX_WORD1_SEM_SEMANTIC_ID_SHIFT)
1898
1899 #define SQ_VTX_WORD1_SEM_SET_SEMANTIC_ID(sq_vtx_word1_sem_reg, semantic_id) \
1900 sq_vtx_word1_sem_reg = (sq_vtx_word1_sem_reg & ~SQ_VTX_WORD1_SEM_SEMANTIC_ID_MASK) | (semantic_id << SQ_VTX_WORD1_SEM_SEMANTIC_ID_SHIFT)
1901
1902 #if defined(LITTLEENDIAN_CPU)
1903
1904 typedef struct _sq_vtx_word1_sem_t {
1905 unsigned int semantic_id : SQ_VTX_WORD1_SEM_SEMANTIC_ID_SIZE;
1906 unsigned int : 24;
1907 } sq_vtx_word1_sem_t;
1908
1909 #elif defined(BIGENDIAN_CPU)
1910
1911 typedef struct _sq_vtx_word1_sem_t {
1912 unsigned int : 24;
1913 unsigned int semantic_id : SQ_VTX_WORD1_SEM_SEMANTIC_ID_SIZE;
1914 } sq_vtx_word1_sem_t;
1915
1916 #endif
1917
1918 typedef union {
1919 unsigned int val : 32;
1920 sq_vtx_word1_sem_t f;
1921 } sq_vtx_word1_sem_u;
1922
1923
1924 /*
1925 * SQ_VTX_WORD2 struct
1926 */
1927
1928 #define SQ_VTX_WORD2_OFFSET_SIZE 16
1929 #define SQ_VTX_WORD2_ENDIAN_SWAP_SIZE 2
1930 #define SQ_VTX_WORD2_CONST_BUF_NO_STRIDE_SIZE 1
1931 #define SQ_VTX_WORD2_MEGA_FETCH_SIZE 1
1932 #define SQ_VTX_WORD2_ALT_CONST_SIZE 1
1933
1934 #define SQ_VTX_WORD2_OFFSET_SHIFT 0
1935 #define SQ_VTX_WORD2_ENDIAN_SWAP_SHIFT 16
1936 #define SQ_VTX_WORD2_CONST_BUF_NO_STRIDE_SHIFT 18
1937 #define SQ_VTX_WORD2_MEGA_FETCH_SHIFT 19
1938 #define SQ_VTX_WORD2_ALT_CONST_SHIFT 20
1939
1940 #define SQ_VTX_WORD2_OFFSET_MASK 0x0000ffff
1941 #define SQ_VTX_WORD2_ENDIAN_SWAP_MASK 0x00030000
1942 #define SQ_VTX_WORD2_CONST_BUF_NO_STRIDE_MASK 0x00040000
1943 #define SQ_VTX_WORD2_MEGA_FETCH_MASK 0x00080000
1944 #define SQ_VTX_WORD2_ALT_CONST_MASK 0x00100000
1945
1946 #define SQ_VTX_WORD2_MASK \
1947 (SQ_VTX_WORD2_OFFSET_MASK | \
1948 SQ_VTX_WORD2_ENDIAN_SWAP_MASK | \
1949 SQ_VTX_WORD2_CONST_BUF_NO_STRIDE_MASK | \
1950 SQ_VTX_WORD2_MEGA_FETCH_MASK | \
1951 SQ_VTX_WORD2_ALT_CONST_MASK)
1952
1953 #define SQ_VTX_WORD2_DEFAULT 0x000dcdcd
1954
1955 #define SQ_VTX_WORD2_GET_OFFSET(sq_vtx_word2) \
1956 ((sq_vtx_word2 & SQ_VTX_WORD2_OFFSET_MASK) >> SQ_VTX_WORD2_OFFSET_SHIFT)
1957 #define SQ_VTX_WORD2_GET_ENDIAN_SWAP(sq_vtx_word2) \
1958 ((sq_vtx_word2 & SQ_VTX_WORD2_ENDIAN_SWAP_MASK) >> SQ_VTX_WORD2_ENDIAN_SWAP_SHIFT)
1959 #define SQ_VTX_WORD2_GET_CONST_BUF_NO_STRIDE(sq_vtx_word2) \
1960 ((sq_vtx_word2 & SQ_VTX_WORD2_CONST_BUF_NO_STRIDE_MASK) >> SQ_VTX_WORD2_CONST_BUF_NO_STRIDE_SHIFT)
1961 #define SQ_VTX_WORD2_GET_MEGA_FETCH(sq_vtx_word2) \
1962 ((sq_vtx_word2 & SQ_VTX_WORD2_MEGA_FETCH_MASK) >> SQ_VTX_WORD2_MEGA_FETCH_SHIFT)
1963 #define SQ_VTX_WORD2_GET_ALT_CONST(sq_vtx_word2) \
1964 ((sq_vtx_word2 & SQ_VTX_WORD2_ALT_CONST_MASK) >> SQ_VTX_WORD2_ALT_CONST_SHIFT)
1965
1966 #define SQ_VTX_WORD2_SET_OFFSET(sq_vtx_word2_reg, offset) \
1967 sq_vtx_word2_reg = (sq_vtx_word2_reg & ~SQ_VTX_WORD2_OFFSET_MASK) | (offset << SQ_VTX_WORD2_OFFSET_SHIFT)
1968 #define SQ_VTX_WORD2_SET_ENDIAN_SWAP(sq_vtx_word2_reg, endian_swap) \
1969 sq_vtx_word2_reg = (sq_vtx_word2_reg & ~SQ_VTX_WORD2_ENDIAN_SWAP_MASK) | (endian_swap << SQ_VTX_WORD2_ENDIAN_SWAP_SHIFT)
1970 #define SQ_VTX_WORD2_SET_CONST_BUF_NO_STRIDE(sq_vtx_word2_reg, const_buf_no_stride) \
1971 sq_vtx_word2_reg = (sq_vtx_word2_reg & ~SQ_VTX_WORD2_CONST_BUF_NO_STRIDE_MASK) | (const_buf_no_stride << SQ_VTX_WORD2_CONST_BUF_NO_STRIDE_SHIFT)
1972 #define SQ_VTX_WORD2_SET_MEGA_FETCH(sq_vtx_word2_reg, mega_fetch) \
1973 sq_vtx_word2_reg = (sq_vtx_word2_reg & ~SQ_VTX_WORD2_MEGA_FETCH_MASK) | (mega_fetch << SQ_VTX_WORD2_MEGA_FETCH_SHIFT)
1974 #define SQ_VTX_WORD2_SET_ALT_CONST(sq_vtx_word2_reg, alt_const) \
1975 sq_vtx_word2_reg = (sq_vtx_word2_reg & ~SQ_VTX_WORD2_ALT_CONST_MASK) | (alt_const << SQ_VTX_WORD2_ALT_CONST_SHIFT)
1976
1977 #if defined(LITTLEENDIAN_CPU)
1978
1979 typedef struct _sq_vtx_word2_t {
1980 unsigned int offset : SQ_VTX_WORD2_OFFSET_SIZE;
1981 unsigned int endian_swap : SQ_VTX_WORD2_ENDIAN_SWAP_SIZE;
1982 unsigned int const_buf_no_stride : SQ_VTX_WORD2_CONST_BUF_NO_STRIDE_SIZE;
1983 unsigned int mega_fetch : SQ_VTX_WORD2_MEGA_FETCH_SIZE;
1984 unsigned int alt_const : SQ_VTX_WORD2_ALT_CONST_SIZE;
1985 unsigned int : 11;
1986 } sq_vtx_word2_t;
1987
1988 #elif defined(BIGENDIAN_CPU)
1989
1990 typedef struct _sq_vtx_word2_t {
1991 unsigned int : 11;
1992 unsigned int alt_const : SQ_VTX_WORD2_ALT_CONST_SIZE;
1993 unsigned int mega_fetch : SQ_VTX_WORD2_MEGA_FETCH_SIZE;
1994 unsigned int const_buf_no_stride : SQ_VTX_WORD2_CONST_BUF_NO_STRIDE_SIZE;
1995 unsigned int endian_swap : SQ_VTX_WORD2_ENDIAN_SWAP_SIZE;
1996 unsigned int offset : SQ_VTX_WORD2_OFFSET_SIZE;
1997 } sq_vtx_word2_t;
1998
1999 #endif
2000
2001 typedef union {
2002 unsigned int val : 32;
2003 sq_vtx_word2_t f;
2004 } sq_vtx_word2_u;
2005
2006 #endif /* _SQ_MICRO_REG_H */
2007
2008