src/mesa/drivers/dri/radeon/common_cmdbuf.h

   1 #ifndef COMMON_CMDBUF_H
   2 #define COMMON_CMDBUF_H
   3
   4 void rcommonEnsureCmdBufSpace(radeonContextPtr rmesa, int dwords, const char *caller);
   5 int rcommonFlushCmdBuf(radeonContextPtr rmesa, const char *caller);
   6 int rcommonFlushCmdBufLocked(radeonContextPtr rmesa, const char *caller);
   7 void rcommonInitCmdBuf(radeonContextPtr rmesa, int max_state_size);
   8 void rcommonDestroyCmdBuf(radeonContextPtr rmesa);
   9
  10 void rcommonBeginBatch(radeonContextPtr rmesa,
  11                        int n,
  12                        int dostate,
  13                        const char *file,
  14                        const char *function,
  15                        int line);
  16
  17 #define RADEON_CP_PACKET3_NOP                       0xC0001000
  18 #define RADEON_CP_PACKET3_NEXT_CHAR                 0xC0001900
  19 #define RADEON_CP_PACKET3_PLY_NEXTSCAN              0xC0001D00
  20 #define RADEON_CP_PACKET3_SET_SCISSORS              0xC0001E00
  21 #define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM     0xC0002300
  22 #define RADEON_CP_PACKET3_LOAD_MICROCODE            0xC0002400
  23 #define RADEON_CP_PACKET3_WAIT_FOR_IDLE             0xC0002600
  24 #define RADEON_CP_PACKET3_3D_DRAW_VBUF              0xC0002800
  25 #define RADEON_CP_PACKET3_3D_DRAW_IMMD              0xC0002900
  26 #define RADEON_CP_PACKET3_3D_DRAW_INDX              0xC0002A00
  27 #define RADEON_CP_PACKET3_LOAD_PALETTE              0xC0002C00
  28 #define RADEON_CP_PACKET3_3D_LOAD_VBPNTR            0xC0002F00
  29 #define RADEON_CP_PACKET3_CNTL_PAINT                0xC0009100
  30 #define RADEON_CP_PACKET3_CNTL_BITBLT               0xC0009200
  31 #define RADEON_CP_PACKET3_CNTL_SMALLTEXT            0xC0009300
  32 #define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT         0xC0009400
  33 #define RADEON_CP_PACKET3_CNTL_POLYLINE             0xC0009500
  34 #define RADEON_CP_PACKET3_CNTL_POLYSCANLINES        0xC0009800
  35 #define RADEON_CP_PACKET3_CNTL_PAINT_MULTI          0xC0009A00
  36 #define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI         0xC0009B00
  37 #define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT         0xC0009C00
  38
  39 #define CP_PACKET2  (2 << 30)
  40 #define CP_PACKET0(reg, n)      (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2))
  41 #define CP_PACKET0_ONE(reg, n)  (RADEON_CP_PACKET0 | RADEON_CP_PACKET0_ONE_REG_WR | ((n)<<16) | ((reg)>>2))
  42 #define CP_PACKET3( pkt, n )                                            \
  43         (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
  44
  45 /**
  46  * Every function writing to the command buffer needs to declare this
  47  * to get the necessary local variables.
  48  */
  49 #define BATCH_LOCALS(rmesa) \
  50         const radeonContextPtr b_l_rmesa = rmesa
  51
  52 /**
  53  * Prepare writing n dwords to the command buffer,
  54  * including producing any necessary state emits on buffer wraparound.
  55  */
  56 #define BEGIN_BATCH(n) rcommonBeginBatch(b_l_rmesa, n, 1, __FILE__, __FUNCTION__, __LINE__)
  57
  58 /**
  59  * Same as BEGIN_BATCH, but do not cause automatic state emits.
  60  */
  61 #define BEGIN_BATCH_NO_AUTOSTATE(n) rcommonBeginBatch(b_l_rmesa, n, 0, __FILE__, __FUNCTION__, __LINE__)
  62
  63 /**
  64  * Write one dword to the command buffer.
  65  */
  66 #define OUT_BATCH(data) \
  67         do { \
  68         radeon_cs_write_dword(b_l_rmesa->cmdbuf.cs, data);\
  69         } while(0)
  70
  71 /**
  72  * Write a relocated dword to the command buffer.
  73  */
  74 #define OUT_BATCH_RELOC(data, bo, offset, rd, wd, flags)        \
  75         do {                                                    \
  76         if (0 && offset) {                                      \
  77             fprintf(stderr, "(%s:%s:%d) offset : %d\n",         \
  78             __FILE__, __FUNCTION__, __LINE__, offset);          \
  79         }                                                       \
  80         radeon_cs_write_dword(b_l_rmesa->cmdbuf.cs, offset);    \
  81         radeon_cs_write_reloc(b_l_rmesa->cmdbuf.cs,             \
  82                               bo, rd, wd, flags);               \
  83         if (!b_l_rmesa->radeonScreen->kernel_mm)                \
  84                 b_l_rmesa->cmdbuf.cs->section_cdw += 2;         \
  85         } while(0)
  86
  87
  88 /**
  89  * Write n dwords from ptr to the command buffer.
  90  */
  91 #define OUT_BATCH_TABLE(ptr,n) \
  92         do { \
  93                 int _i; \
  94         for (_i=0; _i < n; _i++) {\
  95             radeon_cs_write_dword(b_l_rmesa->cmdbuf.cs, ptr[_i]);\
  96         }\
  97         } while(0)
  98
  99 /**
 100  * Finish writing dwords to the command buffer.
 101  * The number of (direct or indirect) OUT_BATCH calls between the previous
 102  * BEGIN_BATCH and END_BATCH must match the number specified at BEGIN_BATCH time.
 103  */
 104 #define END_BATCH() \
 105         do { \
 106         radeon_cs_end(b_l_rmesa->cmdbuf.cs, __FILE__, __FUNCTION__, __LINE__);\
 107         } while(0)
 108
 109 /**
 110  * After the last END_BATCH() of rendering, this indicates that flushing
 111  * the command buffer now is okay.
 112  */
 113 #define COMMIT_BATCH() \
 114         do { \
 115         } while(0)
 116
 117
 118 /** Single register write to command buffer; requires 2 dwords. */
 119 #define OUT_BATCH_REGVAL(reg, val) \
 120         OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), 1)); \
 121         OUT_BATCH((val))
 122
 123 /** Continuous register range write to command buffer; requires 1 dword,
 124  * expects count dwords afterwards for register contents. */
 125 #define OUT_BATCH_REGSEQ(reg, count) \
 126         OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), (count)));
 127
 128 /** Write a 32 bit float to the ring; requires 1 dword. */
 129 #define OUT_BATCH_FLOAT32(f) \
 130         OUT_BATCH(radeonPackFloat32((f)));
 131 #endif