2 #ifndef COMMON_CONTEXT_H
3 #define COMMON_CONTEXT_H
6 #include "math/m_vector.h"
8 #include "tnl/t_context.h"
9 #include "main/colormac.h"
11 #include "radeon_screen.h"
12 #include "radeon_drm.h"
14 #include "tnl/t_vertex.h"
16 /* This union is used to avoid warnings/miscompilation
17 with float to uint32_t casts due to strict-aliasing */
18 typedef union { GLfloat f
; uint32_t ui32
; } float_ui32_type
;
20 struct radeon_context
;
21 typedef struct radeon_context radeonContextRec
;
22 typedef struct radeon_context
*radeonContextPtr
;
32 /* Rasterizing fallbacks */
33 /* See correponding strings in r200_swtcl.c */
34 #define RADEON_FALLBACK_TEXTURE 0x0001
35 #define RADEON_FALLBACK_DRAW_BUFFER 0x0002
36 #define RADEON_FALLBACK_STENCIL 0x0004
37 #define RADEON_FALLBACK_RENDER_MODE 0x0008
38 #define RADEON_FALLBACK_BLEND_EQ 0x0010
39 #define RADEON_FALLBACK_BLEND_FUNC 0x0020
40 #define RADEON_FALLBACK_DISABLE 0x0040
41 #define RADEON_FALLBACK_BORDER_MODE 0x0080
43 #define R200_FALLBACK_TEXTURE 0x01
44 #define R200_FALLBACK_DRAW_BUFFER 0x02
45 #define R200_FALLBACK_STENCIL 0x04
46 #define R200_FALLBACK_RENDER_MODE 0x08
47 #define R200_FALLBACK_DISABLE 0x10
48 #define R200_FALLBACK_BORDER_MODE 0x20
50 #define RADEON_TCL_FALLBACK_RASTER 0x1 /* rasterization */
51 #define RADEON_TCL_FALLBACK_UNFILLED 0x2 /* unfilled tris */
52 #define RADEON_TCL_FALLBACK_LIGHT_TWOSIDE 0x4 /* twoside tris */
53 #define RADEON_TCL_FALLBACK_MATERIAL 0x8 /* material in vb */
54 #define RADEON_TCL_FALLBACK_TEXGEN_0 0x10 /* texgen, unit 0 */
55 #define RADEON_TCL_FALLBACK_TEXGEN_1 0x20 /* texgen, unit 1 */
56 #define RADEON_TCL_FALLBACK_TEXGEN_2 0x40 /* texgen, unit 2 */
57 #define RADEON_TCL_FALLBACK_TCL_DISABLE 0x80 /* user disable */
58 #define RADEON_TCL_FALLBACK_FOGCOORDSPEC 0x100 /* fogcoord, sep. spec light */
60 /* The blit width for texture uploads
62 #define BLIT_WIDTH_BYTES 1024
64 /* Use the templated vertex format:
67 #define TAG(x) radeon##x
68 #include "tnl_dd/t_dd_vertex.h"
71 struct radeon_colorbuffer_state
{
74 struct radeon_renderbuffer
*rrb
;
77 struct radeon_depthbuffer_state
{
80 struct radeon_renderbuffer
*rrb
;
83 struct radeon_scissor_state
{
87 GLuint numClipRects
; /* Cliprects active */
88 GLuint numAllocedClipRects
; /* Cliprects available */
89 drm_clip_rect_t
*pClipRects
;
92 struct radeon_stencilbuffer_state
{
94 GLuint clear
; /* rb3d_stencilrefmask value */
97 struct radeon_stipple_state
{
101 struct radeon_state_atom
{
102 struct radeon_state_atom
*next
, *prev
;
103 const char *name
; /* for debug */
104 int cmd_size
; /* size in bytes */
107 GLuint
*cmd
; /* one or more cmd's */
108 GLuint
*lastcmd
; /* one or more cmd's */
109 GLboolean dirty
; /* dirty-mark in emit_state_list */
110 int (*check
) (GLcontext
*, struct radeon_state_atom
*atom
); /* is this state active? */
111 void (*emit
) (GLcontext
*, struct radeon_state_atom
*atom
);
115 /* Texture related */
116 typedef struct _radeon_texture_image radeon_texture_image
;
118 struct _radeon_texture_image
{
119 struct gl_texture_image base
;
122 * If mt != 0, the image is stored in hardware format in the
123 * given mipmap tree. In this case, base.Data may point into the
124 * mapping of the buffer object that contains the mipmap tree.
126 * If mt == 0, the image is stored in normal memory pointed to
129 struct _radeon_mipmap_tree
*mt
;
130 struct radeon_bo
*bo
;
132 int mtlevel
; /** if mt != 0, this is the image's level in the mipmap tree */
133 int mtface
; /** if mt != 0, this is the image's face in the mipmap tree */
137 static INLINE radeon_texture_image
*get_radeon_texture_image(struct gl_texture_image
*image
)
139 return (radeon_texture_image
*)image
;
143 typedef struct radeon_tex_obj radeonTexObj
, *radeonTexObjPtr
;
145 #define RADEON_TXO_MICRO_TILE (1 << 3)
147 /* Texture object in locally shared texture space.
149 struct radeon_tex_obj
{
150 // driTextureObject base;
151 struct gl_texture_object base
;
152 struct _radeon_mipmap_tree
*mt
;
155 * This is true if we've verified that the mipmap tree above is complete
160 GLuint override_offset
;
161 GLboolean image_override
; /* Image overridden by GLX_EXT_tfp */
162 GLuint tile_bits
; /* hw texture tile bits used on this texture */
163 struct radeon_bo
*bo
;
165 GLuint bufAddr
; /* Offset to start of locally
166 shared texture block */
168 GLuint dirty_state
; /* Flags (1 per texunit) for
169 whether or not this texobj
170 has dirty hardware state
171 (pp_*) that needs to be
175 drm_radeon_tex_image_t image
[6][RADEON_MAX_TEXTURE_LEVELS
];
176 /* Six, for the cube faces */
180 GLuint pp_txfilter
; /* hardware register values */
182 GLuint pp_txformat_x
;
183 GLuint pp_txoffset
; /* Image location in texmem.
184 All cube faces follow. */
185 GLuint pp_txsize
; /* npot only */
186 GLuint pp_txpitch
; /* npot only */
187 GLuint pp_border_color
;
188 GLuint pp_cubic_faces
; /* cube face 1,2,3,4 log2 sizes */
190 GLuint pp_txfilter_1
; /* r300 */
192 GLboolean border_fallback
;
197 static INLINE radeonTexObj
* radeon_tex_obj(struct gl_texture_object
*texObj
)
199 return (radeonTexObj
*)texObj
;
202 /* Need refcounting on dma buffers:
204 struct radeon_dma_buffer
{
205 int refcount
; /* the number of retained regions in buf */
209 /* A retained region, eg vertices for indexed vertices.
211 struct radeon_dma_region
{
212 struct radeon_dma_buffer
*buf
;
213 char *address
; /* == buf->address */
214 int start
, end
, ptr
; /* offsets from start of buf */
221 struct radeon_bo
*bo
; /** Buffer object where vertex data is stored */
222 int offset
; /** Offset into buffer object, in bytes */
223 int components
; /** Number of components per vertex */
224 int stride
; /** Stride in dwords (may be 0 for repeating) */
225 int count
; /** Number of vertices */
229 /* Active dma region. Allocations for vertices and retained
230 * regions come from here. Also used for emitting random vertices,
231 * these may be flushed by calling flush_current();
233 struct radeon_bo
*current
; /** Buffer that DMA memory is allocated from */
234 int current_used
; /** Number of bytes allocated and forgotten about */
235 int current_vertexptr
; /** End of active vertex region */
238 * If current_vertexptr != current_used then flush must be non-zero.
239 * flush must be called before non-active vertex allocations can be
242 void (*flush
) (GLcontext
*);
244 /* Number of "in-flight" DMA buffers, i.e. the number of buffers
245 * for which a DISCARD command is currently queued in the command buffer
248 GLuint nr_released_bufs
;
253 struct radeon_swtcl_info
{
259 /* Fallback rasterization functions
262 GLenum render_primitive
;
265 struct tnl_attr_map vertex_attrs
[VERT_ATTRIB_MAX
];
266 GLuint vertex_attr_count
;
270 struct radeon_ioctl
{
271 GLuint vertex_offset
;
275 #define RADEON_MAX_PRIMS 64
283 static INLINE GLuint
radeonPackColor(GLuint cpp
,
284 GLubyte r
, GLubyte g
,
285 GLubyte b
, GLubyte a
)
289 return PACK_COLOR_565(r
, g
, b
);
291 return PACK_COLOR_8888(a
, r
, g
, b
);
297 #define MAX_CMD_BUF_SZ (16*1024)
299 #define MAX_DMA_BUF_SZ (64*1024)
301 struct radeon_store
{
304 char cmd_buf
[MAX_CMD_BUF_SZ
];
309 struct radeon_dri_mirror
{
310 __DRIcontextPrivate
*context
; /* DRI context */
311 __DRIscreenPrivate
*screen
; /* DRI screen */
314 * DRI drawable bound to this context for drawing.
316 __DRIdrawablePrivate
*drawable
;
319 * DRI drawable bound to this context for reading.
321 __DRIdrawablePrivate
*readable
;
323 drm_context_t hwContext
;
324 drm_hw_lock_t
*hwLock
;
329 #define DEBUG_TEXTURE 0x001
330 #define DEBUG_STATE 0x002
331 #define DEBUG_IOCTL 0x004
332 #define DEBUG_PRIMS 0x008
333 #define DEBUG_VERTS 0x010
334 #define DEBUG_FALLBACKS 0x020
335 #define DEBUG_VFMT 0x040
336 #define DEBUG_CODEGEN 0x080
337 #define DEBUG_VERBOSE 0x100
338 #define DEBUG_DRI 0x200
339 #define DEBUG_DMA 0x400
340 #define DEBUG_SANITY 0x800
341 #define DEBUG_SYNC 0x1000
342 #define DEBUG_PIXEL 0x2000
343 #define DEBUG_MEMORY 0x4000
347 typedef void (*radeon_tri_func
) (radeonContextPtr
,
349 radeonVertex
*, radeonVertex
*);
351 typedef void (*radeon_line_func
) (radeonContextPtr
,
352 radeonVertex
*, radeonVertex
*);
354 typedef void (*radeon_point_func
) (radeonContextPtr
, radeonVertex
*);
356 struct radeon_state
{
357 struct radeon_colorbuffer_state color
;
358 struct radeon_depthbuffer_state depth
;
359 struct radeon_scissor_state scissor
;
360 struct radeon_stencilbuffer_state stencil
;
364 * This structure holds the command buffer while it is being constructed.
366 * The first batch of commands in the buffer is always the state that needs
367 * to be re-emitted when the context is lost. This batch can be skipped
370 struct radeon_cmdbuf
{
371 struct radeon_cs_manager
*csm
;
372 struct radeon_cs
*cs
;
373 int size
; /** # of dwords total */
374 unsigned int flushing
:1; /** whether we're currently in FlushCmdBufLocked */
377 struct radeon_context
{
379 radeonScreenPtr radeonScreen
; /* Screen private DRI data */
381 /* Texture object bookkeeping
384 driTexHeap
* texture_heaps
[ RADEON_NR_TEX_HEAPS
];
385 driTextureObject swapped
;
387 float initialMaxAnisotropy
;
389 struct radeon_dma dma
;
390 /* Rasterization and vertex state:
395 DECLARE_RENDERINPUTS(tnl_index_bitset
); /* index of bits for last tnl_install_attrs */
400 /* Drawable, cliprect and scissor information */
401 GLuint numClipRects
; /* Cliprects for the draw buffer */
402 drm_clip_rect_t
*pClipRects
;
403 unsigned int lastStamp
;
404 GLboolean lost_context
;
405 drm_radeon_sarea_t
*sarea
; /* Private SAREA data */
407 /* Mirrors of some DRI state */
408 struct radeon_dri_mirror dri
;
414 drm_radeon_irq_wait_t iw
;
418 int64_t swap_missed_ust
;
421 GLuint swap_missed_count
;
423 /* Derived state - for r300 only */
424 struct radeon_state state
;
426 struct radeon_swtcl_info swtcl
;
427 /* Configuration cache
429 driOptionCache optionCache
;
431 struct radeon_cmdbuf cmdbuf
;
434 void (*get_lock
)(radeonContextPtr radeon
);
435 void (*update_viewport_offset
)(GLcontext
*ctx
);
436 void (*flush
)(GLcontext
*ctx
);
437 void (*set_all_dirty
)(GLcontext
*ctx
);
438 void (*update_draw_buffer
)(GLcontext
*ctx
);
439 void (*emit_cs_header
)(struct radeon_cs
*cs
, radeonContextPtr rmesa
);
440 void (*emit_state
)(radeonContextPtr rmesa
);
441 void (*flush_vertices
)(radeonContextPtr rmesa
);
442 void (*swtcl_flush
)(GLcontext
*ctx
, uint32_t offset
);
446 #define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx))
449 * This function takes a float and packs it into a uint32_t
451 static INLINE
uint32_t radeonPackFloat32(float fl
)
462 /* This is probably wrong for some values, I need to test this
463 * some more. Range checking would be a good idea also..
465 * But it works for most things. I'll fix it later if someone
466 * else with a better clue doesn't
468 static INLINE
uint32_t radeonPackFloat24(float f
)
472 uint32_t float24
= 0;
477 mantissa
= frexpf(f
, &exponent
);
481 float24
|= (1 << 23);
482 mantissa
= mantissa
* -1.0;
484 /* Handle exponent, bias of 63 */
486 float24
|= (exponent
<< 16);
487 /* Kill 7 LSB of mantissa */
488 float24
|= (radeonPackFloat32(mantissa
) & 0x7FFFFF) >> 7;
493 /* ================================================================
499 extern int RADEON_DEBUG
;
501 #define RADEON_DEBUG 0