src/mesa/drivers/dri/radeon/common_context.h

   1
   2 #ifndef COMMON_CONTEXT_H
   3 #define COMMON_CONTEXT_H
   4 /* This union is used to avoid warnings/miscompilation
   5    with float to uint32_t casts due to strict-aliasing */
   6 typedef union { GLfloat f; uint32_t ui32; } float_ui32_type;
   7
   8 struct radeon_context;
   9 typedef struct radeon_context radeonContextRec;
  10 typedef struct radeon_context *radeonContextPtr;
  11
  12 #include "main/mm.h"
  13 #include "math/m_vector.h"
  14 #include "texmem.h"
  15 #include "tnl/t_context.h"
  16
  17
  18 #define TEX_0   0x1
  19 #define TEX_1   0x2
  20 #define TEX_2   0x4
  21 #define TEX_3   0x8
  22 #define TEX_4   0x10
  23 #define TEX_5   0x20
  24
  25 /* Rasterizing fallbacks */
  26 /* See correponding strings in r200_swtcl.c */
  27 #define RADEON_FALLBACK_TEXTURE         0x0001
  28 #define RADEON_FALLBACK_DRAW_BUFFER     0x0002
  29 #define RADEON_FALLBACK_STENCIL         0x0004
  30 #define RADEON_FALLBACK_RENDER_MODE     0x0008
  31 #define RADEON_FALLBACK_BLEND_EQ        0x0010
  32 #define RADEON_FALLBACK_BLEND_FUNC      0x0020
  33 #define RADEON_FALLBACK_DISABLE         0x0040
  34 #define RADEON_FALLBACK_BORDER_MODE     0x0080
  35
  36 #define R200_FALLBACK_TEXTURE           0x01
  37 #define R200_FALLBACK_DRAW_BUFFER       0x02
  38 #define R200_FALLBACK_STENCIL           0x04
  39 #define R200_FALLBACK_RENDER_MODE       0x08
  40 #define R200_FALLBACK_DISABLE           0x10
  41 #define R200_FALLBACK_BORDER_MODE       0x20
  42
  43 /* The blit width for texture uploads
  44  */
  45 #define BLIT_WIDTH_BYTES 1024
  46
  47 /* Use the templated vertex format:
  48  */
  49 #define COLOR_IS_RGBA
  50 #define TAG(x) radeon##x
  51 #include "tnl_dd/t_dd_vertex.h"
  52 #undef TAG
  53
  54 struct radeon_colorbuffer_state {
  55         GLuint clear;
  56         int roundEnable;
  57         struct radeon_renderbuffer *rrb;
  58 };
  59
  60 struct radeon_depthbuffer_state {
  61         GLuint clear;
  62         GLfloat scale;
  63         struct radeon_renderbuffer *rrb;
  64 };
  65
  66 struct radeon_scissor_state {
  67         drm_clip_rect_t rect;
  68         GLboolean enabled;
  69
  70         GLuint numClipRects;    /* Cliprects active */
  71         GLuint numAllocedClipRects;     /* Cliprects available */
  72         drm_clip_rect_t *pClipRects;
  73 };
  74
  75 struct radeon_stencilbuffer_state {
  76         GLboolean hwBuffer;
  77         GLuint clear;           /* rb3d_stencilrefmask value */
  78 };
  79
  80 struct radeon_stipple_state {
  81         GLuint mask[32];
  82 };
  83
  84 struct radeon_state_atom {
  85         struct radeon_state_atom *next, *prev;
  86         const char *name;       /* for debug */
  87         int cmd_size;           /* size in bytes */
  88         GLuint idx;
  89         GLuint is_tcl;
  90         GLuint *cmd;            /* one or more cmd's */
  91         GLuint *lastcmd;                /* one or more cmd's */
  92         GLboolean dirty;        /* dirty-mark in emit_state_list */
  93         int (*check) (GLcontext *, struct radeon_state_atom *atom); /* is this state active? */
  94         void (*emit) (GLcontext *, struct radeon_state_atom *atom);
  95 };
  96
  97 typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr;
  98
  99 /* Texture object in locally shared texture space.
 100  */
 101 #ifndef RADEON_COMMON_FOR_R300
 102 struct radeon_tex_obj {
 103         driTextureObject base;
 104
 105         GLuint bufAddr;         /* Offset to start of locally
 106                                    shared texture block */
 107
 108         GLuint dirty_state;     /* Flags (1 per texunit) for
 109                                    whether or not this texobj
 110                                    has dirty hardware state
 111                                    (pp_*) that needs to be
 112                                    brought into the
 113                                    texunit. */
 114
 115         drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
 116         /* Six, for the cube faces */
 117
 118         GLboolean image_override; /* Image overridden by GLX_EXT_tfp */
 119
 120         GLuint pp_txfilter;     /* hardware register values */
 121         GLuint pp_txformat;
 122         GLuint pp_txformat_x;
 123         GLuint pp_txoffset;     /* Image location in texmem.
 124                                    All cube faces follow. */
 125         GLuint pp_txsize;       /* npot only */
 126         GLuint pp_txpitch;      /* npot only */
 127         GLuint pp_border_color;
 128         GLuint pp_cubic_faces;  /* cube face 1,2,3,4 log2 sizes */
 129
 130         GLboolean border_fallback;
 131
 132         GLuint tile_bits;       /* hw texture tile bits used on this texture */
 133 };
 134 #endif
 135
 136 /* Need refcounting on dma buffers:
 137  */
 138 struct radeon_dma_buffer {
 139         int refcount;           /* the number of retained regions in buf */
 140         drmBufPtr buf;
 141 };
 142
 143 /* A retained region, eg vertices for indexed vertices.
 144  */
 145 struct radeon_dma_region {
 146    struct radeon_dma_buffer *buf;
 147    char *address;               /* == buf->address */
 148    int start, end, ptr;         /* offsets from start of buf */
 149    int aos_start;
 150    int aos_stride;
 151    int aos_size;
 152 };
 153
 154
 155 struct radeon_dma {
 156    /* Active dma region.  Allocations for vertices and retained
 157     * regions come from here.  Also used for emitting random vertices,
 158     * these may be flushed by calling flush_current();
 159     */
 160    struct radeon_dma_region current;
 161
 162    void (*flush)( GLcontext *ctx );
 163
 164    char *buf0_address;          /* start of buf[0], for index calcs */
 165    GLuint nr_released_bufs;     /* flush after so many buffers released */
 166 };
 167
 168 struct radeon_ioctl {
 169         GLuint vertex_offset;
 170         GLuint vertex_size;
 171 };
 172
 173 #define RADEON_MAX_PRIMS 64
 174
 175 struct radeon_prim {
 176         GLuint start;
 177         GLuint end;
 178         GLuint prim;
 179 };
 180
 181 static INLINE GLuint radeonPackColor(GLuint cpp,
 182                                      GLubyte r, GLubyte g,
 183                                      GLubyte b, GLubyte a)
 184 {
 185         switch (cpp) {
 186         case 2:
 187                 return PACK_COLOR_565(r, g, b);
 188         case 4:
 189                 return PACK_COLOR_8888(a, r, g, b);
 190         default:
 191                 return 0;
 192         }
 193 }
 194
 195 #define MAX_CMD_BUF_SZ (16*1024)
 196
 197 struct radeon_store {
 198         GLuint statenr;
 199         GLuint primnr;
 200         char cmd_buf[MAX_CMD_BUF_SZ];
 201         int cmd_used;
 202         int elts_start;
 203 };
 204
 205 struct radeon_dri_mirror {
 206         __DRIcontextPrivate *context;   /* DRI context */
 207         __DRIscreenPrivate *screen;     /* DRI screen */
 208
 209    /**
 210     * DRI drawable bound to this context for drawing.
 211     */
 212         __DRIdrawablePrivate *drawable;
 213
 214    /**
 215     * DRI drawable bound to this context for reading.
 216     */
 217         __DRIdrawablePrivate *readable;
 218
 219         drm_context_t hwContext;
 220         drm_hw_lock_t *hwLock;
 221         int fd;
 222         int drmMinor;
 223 };
 224
 225 #define DEBUG_TEXTURE   0x001
 226 #define DEBUG_STATE     0x002
 227 #define DEBUG_IOCTL     0x004
 228 #define DEBUG_PRIMS     0x008
 229 #define DEBUG_VERTS     0x010
 230 #define DEBUG_FALLBACKS 0x020
 231 #define DEBUG_VFMT      0x040
 232 #define DEBUG_CODEGEN   0x080
 233 #define DEBUG_VERBOSE   0x100
 234 #define DEBUG_DRI       0x200
 235 #define DEBUG_DMA       0x400
 236 #define DEBUG_SANITY    0x800
 237 #define DEBUG_SYNC      0x1000
 238 #define DEBUG_PIXEL     0x2000
 239 #define DEBUG_MEMORY    0x4000
 240
 241
 242
 243 typedef void (*radeon_tri_func) (radeonContextPtr,
 244                                  radeonVertex *,
 245                                  radeonVertex *, radeonVertex *);
 246
 247 typedef void (*radeon_line_func) (radeonContextPtr,
 248                                   radeonVertex *, radeonVertex *);
 249
 250 typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *);
 251
 252 struct radeon_state {
 253         struct radeon_colorbuffer_state color;
 254         struct radeon_depthbuffer_state depth;
 255         struct radeon_scissor_state scissor;
 256         struct radeon_stencilbuffer_state stencil;
 257 };
 258
 259 struct radeon_context {
 260    GLcontext *glCtx;
 261    radeonScreenPtr radeonScreen;        /* Screen private DRI data */
 262
 263    /* Texture object bookkeeping
 264     */
 265    unsigned              nr_heaps;
 266    driTexHeap          * texture_heaps[ RADEON_NR_TEX_HEAPS ];
 267    driTextureObject      swapped;
 268    int                   texture_depth;
 269    float                 initialMaxAnisotropy;
 270
 271    /* Rasterization and vertex state:
 272     */
 273    GLuint TclFallback;
 274    GLuint Fallback;
 275    GLuint NewGLState;
 276    DECLARE_RENDERINPUTS(tnl_index_bitset);      /* index of bits for last tnl_install_attrs */
 277
 278    /* Page flipping */
 279    GLuint doPageFlip;
 280
 281    /* Drawable, cliprect and scissor information */
 282    GLuint numClipRects; /* Cliprects for the draw buffer */
 283    drm_clip_rect_t *pClipRects;
 284    unsigned int lastStamp;
 285    GLboolean lost_context;
 286    drm_radeon_sarea_t *sarea;   /* Private SAREA data */
 287
 288    /* Mirrors of some DRI state */
 289    struct radeon_dri_mirror dri;
 290
 291    /* Busy waiting */
 292    GLuint do_usleeps;
 293    GLuint do_irqs;
 294    GLuint irqsEmitted;
 295    drm_radeon_irq_wait_t iw;
 296
 297    /* buffer swap */
 298    int64_t swap_ust;
 299    int64_t swap_missed_ust;
 300
 301    GLuint swap_count;
 302    GLuint swap_missed_count;
 303
 304    /* Derived state - for r300 only */
 305    struct radeon_state state;
 306
 307    /* Configuration cache
 308     */
 309    driOptionCache optionCache;
 310
 311    struct {
 312       void (*get_lock)(radeonContextPtr radeon);
 313       void (*update_viewport_offset)(GLcontext *ctx);
 314       void (*flush)(GLcontext *ctx);
 315       void (*set_all_dirty)(GLcontext *ctx);
 316       void (*update_draw_buffer)(GLcontext *ctx);
 317    } vtbl;
 318 };
 319
 320 #define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx))
 321
 322 /* ================================================================
 323  * Debugging:
 324  */
 325 #define DO_DEBUG                1
 326
 327 #if DO_DEBUG
 328 extern int RADEON_DEBUG;
 329 #else
 330 #define RADEON_DEBUG            0
 331 #endif
 332
 333 #endif