2 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "radeon_common.h"
29 #include "radeon_context.h"
30 #include "radeon_blit.h"
32 static inline uint32_t cmdpacket0(struct radeon_screen
*rscrn
,
36 return CP_PACKET0(reg
, count
- 1);
40 /* common formats supported as both textures and render targets */
41 static unsigned is_blit_supported(gl_format mesa_format
)
43 /* XXX others? BE/LE? */
44 switch (mesa_format
) {
45 case MESA_FORMAT_ARGB8888
:
46 case MESA_FORMAT_XRGB8888
:
47 case MESA_FORMAT_RGB565
:
48 case MESA_FORMAT_ARGB4444
:
49 case MESA_FORMAT_ARGB1555
:
57 if (_mesa_get_format_bits(mesa_format
, GL_DEPTH_BITS
) > 0)
63 static inline void emit_vtx_state(struct r100_context
*r100
)
65 BATCH_LOCALS(&r100
->radeon
);
68 if (r100
->radeon
.radeonScreen
->chip_flags
& RADEON_CHIPSET_TCL
) {
69 OUT_BATCH_REGVAL(RADEON_SE_CNTL_STATUS
, 0);
71 OUT_BATCH_REGVAL(RADEON_SE_CNTL_STATUS
, RADEON_TCL_BYPASS
);
74 OUT_BATCH_REGVAL(RADEON_SE_COORD_FMT
, (RADEON_VTX_XY_PRE_MULT_1_OVER_W0
|
75 RADEON_TEX1_W_ROUTING_USE_W0
));
76 OUT_BATCH_REGVAL(RADEON_SE_VTX_FMT
, RADEON_SE_VTX_FMT_XY
| RADEON_SE_VTX_FMT_ST0
);
77 OUT_BATCH_REGVAL(RADEON_SE_CNTL
, (RADEON_DIFFUSE_SHADE_GOURAUD
|
80 RADEON_VTX_PIX_CENTER_OGL
|
81 RADEON_ROUND_MODE_ROUND
|
82 RADEON_ROUND_PREC_4TH_PIX
));
86 static void inline emit_tx_setup(struct r100_context
*r100
,
87 gl_format mesa_format
,
94 uint32_t txformat
= RADEON_TXFORMAT_NON_POWER2
;
95 BATCH_LOCALS(&r100
->radeon
);
97 assert(width
<= 2047);
98 assert(height
<= 2047);
99 assert(offset
% 32 == 0);
101 /* XXX others? BE/LE? */
102 switch (mesa_format
) {
103 case MESA_FORMAT_ARGB8888
:
104 txformat
|= RADEON_TXFORMAT_ARGB8888
| RADEON_TXFORMAT_ALPHA_IN_MAP
;
106 case MESA_FORMAT_XRGB8888
:
107 txformat
|= RADEON_TXFORMAT_ARGB8888
;
109 case MESA_FORMAT_RGB565
:
110 txformat
|= RADEON_TXFORMAT_RGB565
;
112 case MESA_FORMAT_ARGB4444
:
113 txformat
|= RADEON_TXFORMAT_ARGB4444
| RADEON_TXFORMAT_ALPHA_IN_MAP
;
115 case MESA_FORMAT_ARGB1555
:
116 txformat
|= RADEON_TXFORMAT_ARGB1555
| RADEON_TXFORMAT_ALPHA_IN_MAP
;
119 txformat
|= RADEON_TXFORMAT_I8
| RADEON_TXFORMAT_ALPHA_IN_MAP
;
126 OUT_BATCH_REGVAL(RADEON_PP_CNTL
, RADEON_TEX_0_ENABLE
| RADEON_TEX_BLEND_0_ENABLE
);
127 OUT_BATCH_REGVAL(RADEON_PP_TXCBLEND_0
, (RADEON_COLOR_ARG_A_ZERO
|
128 RADEON_COLOR_ARG_B_ZERO
|
129 RADEON_COLOR_ARG_C_T0_COLOR
|
130 RADEON_BLEND_CTL_ADD
|
132 OUT_BATCH_REGVAL(RADEON_PP_TXABLEND_0
, (RADEON_ALPHA_ARG_A_ZERO
|
133 RADEON_ALPHA_ARG_B_ZERO
|
134 RADEON_ALPHA_ARG_C_T0_ALPHA
|
135 RADEON_BLEND_CTL_ADD
|
137 OUT_BATCH_REGVAL(RADEON_PP_TXFILTER_0
, (RADEON_CLAMP_S_CLAMP_LAST
|
138 RADEON_CLAMP_T_CLAMP_LAST
|
139 RADEON_MAG_FILTER_NEAREST
|
140 RADEON_MIN_FILTER_NEAREST
));
141 OUT_BATCH_REGVAL(RADEON_PP_TXFORMAT_0
, txformat
);
142 OUT_BATCH_REGVAL(RADEON_PP_TEX_SIZE_0
, ((width
- 1) |
143 ((height
- 1) << RADEON_TEX_VSIZE_SHIFT
)));
144 OUT_BATCH_REGVAL(RADEON_PP_TEX_PITCH_0
, pitch
- 32);
146 OUT_BATCH_REGSEQ(RADEON_PP_TXOFFSET_0
, 1);
147 OUT_BATCH_RELOC(0, bo
, 0, RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0, 0);
152 static inline void emit_cb_setup(struct r100_context
*r100
,
153 struct radeon_bo
*bo
,
155 gl_format mesa_format
,
160 uint32_t dst_pitch
= pitch
;
161 uint32_t dst_format
= 0;
162 BATCH_LOCALS(&r100
->radeon
);
164 /* XXX others? BE/LE? */
165 switch (mesa_format
) {
166 case MESA_FORMAT_ARGB8888
:
167 case MESA_FORMAT_XRGB8888
:
168 dst_format
= RADEON_COLOR_FORMAT_ARGB8888
;
170 case MESA_FORMAT_RGB565
:
171 dst_format
= RADEON_COLOR_FORMAT_RGB565
;
173 case MESA_FORMAT_ARGB4444
:
174 dst_format
= RADEON_COLOR_FORMAT_ARGB4444
;
176 case MESA_FORMAT_ARGB1555
:
177 dst_format
= RADEON_COLOR_FORMAT_ARGB1555
;
180 dst_format
= RADEON_COLOR_FORMAT_RGB8
;
186 BEGIN_BATCH_NO_AUTOSTATE(18);
187 OUT_BATCH_REGVAL(RADEON_RE_TOP_LEFT
, 0);
188 OUT_BATCH_REGVAL(RADEON_RE_WIDTH_HEIGHT
, ((width
<< RADEON_RE_WIDTH_SHIFT
) |
189 (height
<< RADEON_RE_HEIGHT_SHIFT
)));
190 OUT_BATCH_REGVAL(RADEON_RB3D_PLANEMASK
, 0xffffffff);
191 OUT_BATCH_REGVAL(RADEON_RB3D_BLENDCNTL
, RADEON_SRC_BLEND_GL_ONE
| RADEON_DST_BLEND_GL_ZERO
);
192 OUT_BATCH_REGVAL(RADEON_RB3D_CNTL
, dst_format
);
194 OUT_BATCH_REGSEQ(RADEON_RB3D_COLOROFFSET
, 1);
195 OUT_BATCH_RELOC(0, bo
, 0, 0, RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0);
196 OUT_BATCH_REGSEQ(RADEON_RB3D_COLORPITCH
, 1);
197 OUT_BATCH_RELOC(dst_pitch
, bo
, dst_pitch
, 0, RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0);
202 static GLboolean
validate_buffers(struct r100_context
*r100
,
203 struct radeon_bo
*src_bo
,
204 struct radeon_bo
*dst_bo
)
207 radeon_cs_space_add_persistent_bo(r100
->radeon
.cmdbuf
.cs
,
208 src_bo
, RADEON_GEM_DOMAIN_VRAM
, 0);
210 radeon_cs_space_add_persistent_bo(r100
->radeon
.cmdbuf
.cs
,
211 dst_bo
, 0, RADEON_GEM_DOMAIN_VRAM
);
213 ret
= radeon_cs_space_check_with_bo(r100
->radeon
.cmdbuf
.cs
,
214 first_elem(&r100
->radeon
.dma
.reserved
)->bo
,
215 RADEON_GEM_DOMAIN_GTT
, 0);
223 * Calculate texcoords for given image region.
224 * Output values are [minx, maxx, miny, maxy]
226 static inline void calc_tex_coords(float img_width
, float img_height
,
228 float reg_width
, float reg_height
,
229 unsigned flip_y
, float *buf
)
231 buf
[0] = x
/ img_width
;
232 buf
[1] = buf
[0] + reg_width
/ img_width
;
233 buf
[2] = y
/ img_height
;
234 buf
[3] = buf
[2] + reg_height
/ img_height
;
238 buf
[2] = 1.0 - buf
[3];
243 static inline void emit_draw_packet(struct r100_context
*r100
,
244 unsigned src_width
, unsigned src_height
,
245 unsigned src_x_offset
, unsigned src_y_offset
,
246 unsigned dst_x_offset
, unsigned dst_y_offset
,
247 unsigned reg_width
, unsigned reg_height
,
252 BATCH_LOCALS(&r100
->radeon
);
254 calc_tex_coords(src_width
, src_height
,
255 src_x_offset
, src_y_offset
,
256 reg_width
, reg_height
,
259 verts
[0] = dst_x_offset
;
260 verts
[1] = dst_y_offset
+ reg_height
;
261 verts
[2] = texcoords
[0];
262 verts
[3] = texcoords
[2];
264 verts
[4] = dst_x_offset
+ reg_width
;
265 verts
[5] = dst_y_offset
+ reg_height
;
266 verts
[6] = texcoords
[1];
267 verts
[7] = texcoords
[2];
269 verts
[8] = dst_x_offset
+ reg_width
;
270 verts
[9] = dst_y_offset
;
271 verts
[10] = texcoords
[1];
272 verts
[11] = texcoords
[3];
275 OUT_BATCH(RADEON_CP_PACKET3_3D_DRAW_IMMD
| (13 << 16));
276 OUT_BATCH(RADEON_CP_VC_FRMT_XY
| RADEON_CP_VC_FRMT_ST0
);
277 OUT_BATCH(RADEON_CP_VC_CNTL_PRIM_WALK_RING
|
278 RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST
|
279 RADEON_CP_VC_CNTL_MAOS_ENABLE
|
280 RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE
|
282 OUT_BATCH_TABLE(verts
, 12);
287 * Copy a region of [@a width x @a height] pixels from source buffer
288 * to destination buffer.
289 * @param[in] r100 r100 context
290 * @param[in] src_bo source radeon buffer object
291 * @param[in] src_offset offset of the source image in the @a src_bo
292 * @param[in] src_mesaformat source image format
293 * @param[in] src_pitch aligned source image width
294 * @param[in] src_width source image width
295 * @param[in] src_height source image height
296 * @param[in] src_x_offset x offset in the source image
297 * @param[in] src_y_offset y offset in the source image
298 * @param[in] dst_bo destination radeon buffer object
299 * @param[in] dst_offset offset of the destination image in the @a dst_bo
300 * @param[in] dst_mesaformat destination image format
301 * @param[in] dst_pitch aligned destination image width
302 * @param[in] dst_width destination image width
303 * @param[in] dst_height destination image height
304 * @param[in] dst_x_offset x offset in the destination image
305 * @param[in] dst_y_offset y offset in the destination image
306 * @param[in] width region width
307 * @param[in] height region height
308 * @param[in] flip_y set if y coords of the source image need to be flipped
310 GLboolean
r100_blit(struct r100_context
*r100
,
311 struct radeon_bo
*src_bo
,
313 gl_format src_mesaformat
,
317 unsigned src_x_offset
,
318 unsigned src_y_offset
,
319 struct radeon_bo
*dst_bo
,
321 gl_format dst_mesaformat
,
325 unsigned dst_x_offset
,
326 unsigned dst_y_offset
,
331 if (!is_blit_supported(dst_mesaformat
))
334 /* Make sure that colorbuffer has even width - hw limitation */
335 if (dst_pitch
% 2 > 0)
338 /* Rendering to small buffer doesn't work.
339 * Looks like a hw limitation.
344 /* Need to clamp the region size to make sure
345 * we don't read outside of the source buffer
346 * or write outside of the destination buffer.
348 if (reg_width
+ src_x_offset
> src_width
)
349 reg_width
= src_width
- src_x_offset
;
350 if (reg_height
+ src_y_offset
> src_height
)
351 reg_height
= src_height
- src_y_offset
;
352 if (reg_width
+ dst_x_offset
> dst_width
)
353 reg_width
= dst_width
- dst_x_offset
;
354 if (reg_height
+ dst_y_offset
> dst_height
)
355 reg_height
= dst_height
- dst_y_offset
;
357 if (src_bo
== dst_bo
) {
362 fprintf(stderr
, "src: size [%d x %d], pitch %d, "
363 "offset [%d x %d], format %s, bo %p\n",
364 src_width
, src_height
, src_pitch
,
365 src_x_offset
, src_y_offset
,
366 _mesa_get_format_name(src_mesaformat
),
368 fprintf(stderr
, "dst: pitch %d, offset[%d x %d], format %s, bo %p\n",
369 dst_pitch
, dst_x_offset
, dst_y_offset
,
370 _mesa_get_format_name(dst_mesaformat
), dst_bo
);
371 fprintf(stderr
, "region: %d x %d\n", reg_width
, reg_height
);
374 /* Flush is needed to make sure that source buffer has correct data */
375 radeonFlush(r100
->radeon
.glCtx
);
377 rcommonEnsureCmdBufSpace(&r100
->radeon
, 59, __FUNCTION__
);
379 if (!validate_buffers(r100
, src_bo
, dst_bo
))
383 emit_vtx_state(r100
);
385 emit_tx_setup(r100
, src_mesaformat
, src_bo
, src_offset
, src_width
, src_height
, src_pitch
);
387 emit_cb_setup(r100
, dst_bo
, dst_offset
, dst_mesaformat
, dst_pitch
, dst_width
, dst_height
);
389 emit_draw_packet(r100
, src_width
, src_height
,
390 src_x_offset
, src_y_offset
,
391 dst_x_offset
, dst_y_offset
,
392 reg_width
, reg_height
,
395 radeonFlush(r100
->radeon
.glCtx
);