2 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "radeon_common.h"
29 #include "radeon_context.h"
30 #include "radeon_blit.h"
32 static inline uint32_t cmdpacket0(struct radeon_screen
*rscrn
,
36 return CP_PACKET0(reg
, count
- 1);
40 /* common formats supported as both textures and render targets */
41 unsigned r100_check_blit(mesa_format mesa_format
, uint32_t dst_pitch
)
43 /* XXX others? BE/LE? */
44 switch (mesa_format
) {
45 case MESA_FORMAT_B8G8R8A8_UNORM
:
46 case MESA_FORMAT_B8G8R8X8_UNORM
:
47 case MESA_FORMAT_B5G6R5_UNORM
:
48 case MESA_FORMAT_B4G4R4A4_UNORM
:
49 case MESA_FORMAT_B5G5R5A1_UNORM
:
50 case MESA_FORMAT_A_UNORM8
:
51 case MESA_FORMAT_L_UNORM8
:
52 case MESA_FORMAT_I_UNORM8
:
58 /* Rendering to small buffer doesn't work.
59 * Looks like a hw limitation.
65 if (_mesa_get_format_bits(mesa_format
, GL_DEPTH_BITS
) > 0)
71 static inline void emit_vtx_state(struct r100_context
*r100
)
73 BATCH_LOCALS(&r100
->radeon
);
76 if (r100
->radeon
.radeonScreen
->chip_flags
& RADEON_CHIPSET_TCL
) {
77 OUT_BATCH_REGVAL(RADEON_SE_CNTL_STATUS
, 0);
79 OUT_BATCH_REGVAL(RADEON_SE_CNTL_STATUS
, RADEON_TCL_BYPASS
);
82 OUT_BATCH_REGVAL(RADEON_SE_COORD_FMT
, (RADEON_VTX_XY_PRE_MULT_1_OVER_W0
|
83 RADEON_TEX1_W_ROUTING_USE_W0
));
84 OUT_BATCH_REGVAL(RADEON_SE_VTX_FMT
, RADEON_SE_VTX_FMT_XY
| RADEON_SE_VTX_FMT_ST0
);
85 OUT_BATCH_REGVAL(RADEON_SE_CNTL
, (RADEON_DIFFUSE_SHADE_GOURAUD
|
88 RADEON_VTX_PIX_CENTER_OGL
|
89 RADEON_ROUND_MODE_ROUND
|
90 RADEON_ROUND_PREC_4TH_PIX
));
94 static void inline emit_tx_setup(struct r100_context
*r100
,
95 mesa_format mesa_format
,
102 uint32_t txformat
= RADEON_TXFORMAT_NON_POWER2
;
103 BATCH_LOCALS(&r100
->radeon
);
105 assert(width
<= 2048);
106 assert(height
<= 2048);
107 assert(offset
% 32 == 0);
109 /* XXX others? BE/LE? */
110 switch (mesa_format
) {
111 case MESA_FORMAT_B8G8R8A8_UNORM
:
112 txformat
|= RADEON_TXFORMAT_ARGB8888
| RADEON_TXFORMAT_ALPHA_IN_MAP
;
114 case MESA_FORMAT_A8B8G8R8_UNORM
:
115 txformat
|= RADEON_TXFORMAT_RGBA8888
| RADEON_TXFORMAT_ALPHA_IN_MAP
;
117 case MESA_FORMAT_B8G8R8X8_UNORM
:
118 txformat
|= RADEON_TXFORMAT_ARGB8888
;
120 case MESA_FORMAT_B5G6R5_UNORM
:
121 txformat
|= RADEON_TXFORMAT_RGB565
;
123 case MESA_FORMAT_B4G4R4A4_UNORM
:
124 txformat
|= RADEON_TXFORMAT_ARGB4444
| RADEON_TXFORMAT_ALPHA_IN_MAP
;
126 case MESA_FORMAT_B5G5R5A1_UNORM
:
127 txformat
|= RADEON_TXFORMAT_ARGB1555
| RADEON_TXFORMAT_ALPHA_IN_MAP
;
129 case MESA_FORMAT_A_UNORM8
:
130 case MESA_FORMAT_I_UNORM8
:
131 txformat
|= RADEON_TXFORMAT_I8
| RADEON_TXFORMAT_ALPHA_IN_MAP
;
133 case MESA_FORMAT_L_UNORM8
:
134 txformat
|= RADEON_TXFORMAT_I8
;
136 case MESA_FORMAT_L8A8_UNORM
:
137 txformat
|= RADEON_TXFORMAT_AI88
| RADEON_TXFORMAT_ALPHA_IN_MAP
;
143 if (bo
->flags
& RADEON_BO_FLAGS_MACRO_TILE
)
144 offset
|= RADEON_TXO_MACRO_TILE
;
145 if (bo
->flags
& RADEON_BO_FLAGS_MICRO_TILE
)
146 offset
|= RADEON_TXO_MICRO_TILE_X2
;
149 OUT_BATCH_REGVAL(RADEON_PP_CNTL
, RADEON_TEX_0_ENABLE
| RADEON_TEX_BLEND_0_ENABLE
);
150 OUT_BATCH_REGVAL(RADEON_PP_TXCBLEND_0
, (RADEON_COLOR_ARG_A_ZERO
|
151 RADEON_COLOR_ARG_B_ZERO
|
152 RADEON_COLOR_ARG_C_T0_COLOR
|
153 RADEON_BLEND_CTL_ADD
|
155 OUT_BATCH_REGVAL(RADEON_PP_TXABLEND_0
, (RADEON_ALPHA_ARG_A_ZERO
|
156 RADEON_ALPHA_ARG_B_ZERO
|
157 RADEON_ALPHA_ARG_C_T0_ALPHA
|
158 RADEON_BLEND_CTL_ADD
|
160 OUT_BATCH_REGVAL(RADEON_PP_TXFILTER_0
, (RADEON_CLAMP_S_CLAMP_LAST
|
161 RADEON_CLAMP_T_CLAMP_LAST
|
162 RADEON_MAG_FILTER_NEAREST
|
163 RADEON_MIN_FILTER_NEAREST
));
164 OUT_BATCH_REGVAL(RADEON_PP_TXFORMAT_0
, txformat
);
165 OUT_BATCH_REGVAL(RADEON_PP_TEX_SIZE_0
, ((width
- 1) |
166 ((height
- 1) << RADEON_TEX_VSIZE_SHIFT
)));
167 OUT_BATCH_REGVAL(RADEON_PP_TEX_PITCH_0
, pitch
* _mesa_get_format_bytes(mesa_format
) - 32);
169 OUT_BATCH_REGSEQ(RADEON_PP_TXOFFSET_0
, 1);
170 OUT_BATCH_RELOC(offset
, bo
, offset
, RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0, 0);
175 static inline void emit_cb_setup(struct r100_context
*r100
,
176 struct radeon_bo
*bo
,
178 mesa_format mesa_format
,
183 uint32_t dst_pitch
= pitch
;
184 uint32_t dst_format
= 0;
185 BATCH_LOCALS(&r100
->radeon
);
187 /* XXX others? BE/LE? */
188 switch (mesa_format
) {
189 case MESA_FORMAT_B8G8R8A8_UNORM
:
190 case MESA_FORMAT_B8G8R8X8_UNORM
:
191 dst_format
= RADEON_COLOR_FORMAT_ARGB8888
;
193 case MESA_FORMAT_B5G6R5_UNORM
:
194 dst_format
= RADEON_COLOR_FORMAT_RGB565
;
196 case MESA_FORMAT_B4G4R4A4_UNORM
:
197 dst_format
= RADEON_COLOR_FORMAT_ARGB4444
;
199 case MESA_FORMAT_B5G5R5A1_UNORM
:
200 dst_format
= RADEON_COLOR_FORMAT_ARGB1555
;
202 case MESA_FORMAT_A_UNORM8
:
203 case MESA_FORMAT_L_UNORM8
:
204 case MESA_FORMAT_I_UNORM8
:
205 dst_format
= RADEON_COLOR_FORMAT_RGB8
;
211 if (bo
->flags
& RADEON_BO_FLAGS_MACRO_TILE
)
212 dst_pitch
|= RADEON_COLOR_TILE_ENABLE
;
214 if (bo
->flags
& RADEON_BO_FLAGS_MICRO_TILE
)
215 dst_pitch
|= RADEON_COLOR_MICROTILE_ENABLE
;
218 OUT_BATCH_REGVAL(RADEON_RE_TOP_LEFT
, 0);
219 OUT_BATCH_REGVAL(RADEON_RE_WIDTH_HEIGHT
, (((width
- 1) << RADEON_RE_WIDTH_SHIFT
) |
220 ((height
- 1) << RADEON_RE_HEIGHT_SHIFT
)));
221 OUT_BATCH_REGVAL(RADEON_RB3D_PLANEMASK
, 0xffffffff);
222 OUT_BATCH_REGVAL(RADEON_RB3D_BLENDCNTL
, RADEON_SRC_BLEND_GL_ONE
| RADEON_DST_BLEND_GL_ZERO
);
223 OUT_BATCH_REGVAL(RADEON_RB3D_CNTL
, dst_format
);
225 OUT_BATCH_REGSEQ(RADEON_RB3D_COLOROFFSET
, 1);
226 OUT_BATCH_RELOC(offset
, bo
, offset
, 0, RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0);
227 OUT_BATCH_REGSEQ(RADEON_RB3D_COLORPITCH
, 1);
228 OUT_BATCH_RELOC(dst_pitch
, bo
, dst_pitch
, 0, RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0);
233 static GLboolean
validate_buffers(struct r100_context
*r100
,
234 struct radeon_bo
*src_bo
,
235 struct radeon_bo
*dst_bo
)
239 radeon_cs_space_reset_bos(r100
->radeon
.cmdbuf
.cs
);
241 ret
= radeon_cs_space_check_with_bo(r100
->radeon
.cmdbuf
.cs
,
242 src_bo
, RADEON_GEM_DOMAIN_VRAM
| RADEON_GEM_DOMAIN_GTT
, 0);
246 ret
= radeon_cs_space_check_with_bo(r100
->radeon
.cmdbuf
.cs
,
247 dst_bo
, 0, RADEON_GEM_DOMAIN_VRAM
| RADEON_GEM_DOMAIN_GTT
);
255 * Calculate texcoords for given image region.
256 * Output values are [minx, maxx, miny, maxy]
258 static inline void calc_tex_coords(float img_width
, float img_height
,
260 float reg_width
, float reg_height
,
261 unsigned flip_y
, float *buf
)
263 buf
[0] = x
/ img_width
;
264 buf
[1] = buf
[0] + reg_width
/ img_width
;
265 buf
[2] = y
/ img_height
;
266 buf
[3] = buf
[2] + reg_height
/ img_height
;
269 buf
[2] = 1.0 - buf
[2];
270 buf
[3] = 1.0 - buf
[3];
274 static inline void emit_draw_packet(struct r100_context
*r100
,
275 unsigned src_width
, unsigned src_height
,
276 unsigned src_x_offset
, unsigned src_y_offset
,
277 unsigned dst_x_offset
, unsigned dst_y_offset
,
278 unsigned reg_width
, unsigned reg_height
,
283 BATCH_LOCALS(&r100
->radeon
);
285 calc_tex_coords(src_width
, src_height
,
286 src_x_offset
, src_y_offset
,
287 reg_width
, reg_height
,
290 verts
[0] = dst_x_offset
;
291 verts
[1] = dst_y_offset
+ reg_height
;
292 verts
[2] = texcoords
[0];
293 verts
[3] = texcoords
[3];
295 verts
[4] = dst_x_offset
+ reg_width
;
296 verts
[5] = dst_y_offset
+ reg_height
;
297 verts
[6] = texcoords
[1];
298 verts
[7] = texcoords
[3];
300 verts
[8] = dst_x_offset
+ reg_width
;
301 verts
[9] = dst_y_offset
;
302 verts
[10] = texcoords
[1];
303 verts
[11] = texcoords
[2];
306 OUT_BATCH(RADEON_CP_PACKET3_3D_DRAW_IMMD
| (13 << 16));
307 OUT_BATCH(RADEON_CP_VC_FRMT_XY
| RADEON_CP_VC_FRMT_ST0
);
308 OUT_BATCH(RADEON_CP_VC_CNTL_PRIM_WALK_RING
|
309 RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST
|
310 RADEON_CP_VC_CNTL_MAOS_ENABLE
|
311 RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE
|
313 OUT_BATCH_TABLE(verts
, 12);
318 * Copy a region of [@a width x @a height] pixels from source buffer
319 * to destination buffer.
320 * @param[in] r100 r100 context
321 * @param[in] src_bo source radeon buffer object
322 * @param[in] src_offset offset of the source image in the @a src_bo
323 * @param[in] src_mesaformat source image format
324 * @param[in] src_pitch aligned source image width
325 * @param[in] src_width source image width
326 * @param[in] src_height source image height
327 * @param[in] src_x_offset x offset in the source image
328 * @param[in] src_y_offset y offset in the source image
329 * @param[in] dst_bo destination radeon buffer object
330 * @param[in] dst_offset offset of the destination image in the @a dst_bo
331 * @param[in] dst_mesaformat destination image format
332 * @param[in] dst_pitch aligned destination image width
333 * @param[in] dst_width destination image width
334 * @param[in] dst_height destination image height
335 * @param[in] dst_x_offset x offset in the destination image
336 * @param[in] dst_y_offset y offset in the destination image
337 * @param[in] width region width
338 * @param[in] height region height
339 * @param[in] flip_y set if y coords of the source image need to be flipped
341 unsigned r100_blit(struct gl_context
*ctx
,
342 struct radeon_bo
*src_bo
,
344 mesa_format src_mesaformat
,
348 unsigned src_x_offset
,
349 unsigned src_y_offset
,
350 struct radeon_bo
*dst_bo
,
352 mesa_format dst_mesaformat
,
356 unsigned dst_x_offset
,
357 unsigned dst_y_offset
,
362 struct r100_context
*r100
= R100_CONTEXT(ctx
);
364 if (!r100_check_blit(dst_mesaformat
, dst_pitch
))
367 /* Make sure that colorbuffer has even width - hw limitation */
368 if (dst_pitch
% 2 > 0)
371 /* Need to clamp the region size to make sure
372 * we don't read outside of the source buffer
373 * or write outside of the destination buffer.
375 if (reg_width
+ src_x_offset
> src_width
)
376 reg_width
= src_width
- src_x_offset
;
377 if (reg_height
+ src_y_offset
> src_height
)
378 reg_height
= src_height
- src_y_offset
;
379 if (reg_width
+ dst_x_offset
> dst_width
)
380 reg_width
= dst_width
- dst_x_offset
;
381 if (reg_height
+ dst_y_offset
> dst_height
)
382 reg_height
= dst_height
- dst_y_offset
;
384 if (src_bo
== dst_bo
) {
388 if (src_offset
% 32 || dst_offset
% 32) {
393 fprintf(stderr
, "src: size [%d x %d], pitch %d, offset %zd "
394 "offset [%d x %d], format %s, bo %p\n",
395 src_width
, src_height
, src_pitch
, src_offset
,
396 src_x_offset
, src_y_offset
,
397 _mesa_get_format_name(src_mesaformat
),
399 fprintf(stderr
, "dst: pitch %d offset %zd, offset[%d x %d], format %s, bo %p\n",
400 dst_pitch
, dst_offset
, dst_x_offset
, dst_y_offset
,
401 _mesa_get_format_name(dst_mesaformat
), dst_bo
);
402 fprintf(stderr
, "region: %d x %d\n", reg_width
, reg_height
);
405 /* Flush is needed to make sure that source buffer has correct data */
408 rcommonEnsureCmdBufSpace(&r100
->radeon
, 59, __FUNCTION__
);
410 if (!validate_buffers(r100
, src_bo
, dst_bo
))
414 emit_vtx_state(r100
);
416 emit_tx_setup(r100
, src_mesaformat
, src_bo
, src_offset
, src_width
, src_height
, src_pitch
);
418 emit_cb_setup(r100
, dst_bo
, dst_offset
, dst_mesaformat
, dst_pitch
, dst_width
, dst_height
);
420 emit_draw_packet(r100
, src_width
, src_height
,
421 src_x_offset
, src_y_offset
,
422 dst_x_offset
, dst_y_offset
,
423 reg_width
, reg_height
,