2 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #include "radeon_common.h"
29 #include "radeon_context.h"
30 #include "radeon_blit.h"
32 static inline uint32_t cmdpacket0(struct radeon_screen
*rscrn
,
36 return CP_PACKET0(reg
, count
- 1);
40 /* common formats supported as both textures and render targets */
41 unsigned r100_check_blit(gl_format mesa_format
)
43 /* XXX others? BE/LE? */
44 switch (mesa_format
) {
45 case MESA_FORMAT_ARGB8888
:
46 case MESA_FORMAT_XRGB8888
:
47 case MESA_FORMAT_RGB565
:
48 case MESA_FORMAT_ARGB4444
:
49 case MESA_FORMAT_ARGB1555
:
59 if (_mesa_get_format_bits(mesa_format
, GL_DEPTH_BITS
) > 0)
65 static inline void emit_vtx_state(struct r100_context
*r100
)
67 BATCH_LOCALS(&r100
->radeon
);
70 if (r100
->radeon
.radeonScreen
->chip_flags
& RADEON_CHIPSET_TCL
) {
71 OUT_BATCH_REGVAL(RADEON_SE_CNTL_STATUS
, 0);
73 OUT_BATCH_REGVAL(RADEON_SE_CNTL_STATUS
, RADEON_TCL_BYPASS
);
76 OUT_BATCH_REGVAL(RADEON_SE_COORD_FMT
, (RADEON_VTX_XY_PRE_MULT_1_OVER_W0
|
77 RADEON_TEX1_W_ROUTING_USE_W0
));
78 OUT_BATCH_REGVAL(RADEON_SE_VTX_FMT
, RADEON_SE_VTX_FMT_XY
| RADEON_SE_VTX_FMT_ST0
);
79 OUT_BATCH_REGVAL(RADEON_SE_CNTL
, (RADEON_DIFFUSE_SHADE_GOURAUD
|
82 RADEON_VTX_PIX_CENTER_OGL
|
83 RADEON_ROUND_MODE_ROUND
|
84 RADEON_ROUND_PREC_4TH_PIX
));
88 static void inline emit_tx_setup(struct r100_context
*r100
,
89 gl_format mesa_format
,
96 uint32_t txformat
= RADEON_TXFORMAT_NON_POWER2
;
97 BATCH_LOCALS(&r100
->radeon
);
99 assert(width
<= 2047);
100 assert(height
<= 2047);
101 assert(offset
% 32 == 0);
103 /* XXX others? BE/LE? */
104 switch (mesa_format
) {
105 case MESA_FORMAT_ARGB8888
:
106 txformat
|= RADEON_TXFORMAT_ARGB8888
| RADEON_TXFORMAT_ALPHA_IN_MAP
;
108 case MESA_FORMAT_RGBA8888
:
109 txformat
|= RADEON_TXFORMAT_RGBA8888
| RADEON_TXFORMAT_ALPHA_IN_MAP
;
111 case MESA_FORMAT_XRGB8888
:
112 txformat
|= RADEON_TXFORMAT_ARGB8888
;
114 case MESA_FORMAT_RGB565
:
115 txformat
|= RADEON_TXFORMAT_RGB565
;
117 case MESA_FORMAT_ARGB4444
:
118 txformat
|= RADEON_TXFORMAT_ARGB4444
| RADEON_TXFORMAT_ALPHA_IN_MAP
;
120 case MESA_FORMAT_ARGB1555
:
121 txformat
|= RADEON_TXFORMAT_ARGB1555
| RADEON_TXFORMAT_ALPHA_IN_MAP
;
125 txformat
|= RADEON_TXFORMAT_I8
| RADEON_TXFORMAT_ALPHA_IN_MAP
;
128 txformat
|= RADEON_TXFORMAT_I8
;
130 case MESA_FORMAT_AL88
:
131 txformat
|= RADEON_TXFORMAT_AI88
| RADEON_TXFORMAT_ALPHA_IN_MAP
;
138 OUT_BATCH_REGVAL(RADEON_PP_CNTL
, RADEON_TEX_0_ENABLE
| RADEON_TEX_BLEND_0_ENABLE
);
139 OUT_BATCH_REGVAL(RADEON_PP_TXCBLEND_0
, (RADEON_COLOR_ARG_A_ZERO
|
140 RADEON_COLOR_ARG_B_ZERO
|
141 RADEON_COLOR_ARG_C_T0_COLOR
|
142 RADEON_BLEND_CTL_ADD
|
144 OUT_BATCH_REGVAL(RADEON_PP_TXABLEND_0
, (RADEON_ALPHA_ARG_A_ZERO
|
145 RADEON_ALPHA_ARG_B_ZERO
|
146 RADEON_ALPHA_ARG_C_T0_ALPHA
|
147 RADEON_BLEND_CTL_ADD
|
149 OUT_BATCH_REGVAL(RADEON_PP_TXFILTER_0
, (RADEON_CLAMP_S_CLAMP_LAST
|
150 RADEON_CLAMP_T_CLAMP_LAST
|
151 RADEON_MAG_FILTER_NEAREST
|
152 RADEON_MIN_FILTER_NEAREST
));
153 OUT_BATCH_REGVAL(RADEON_PP_TXFORMAT_0
, txformat
);
154 OUT_BATCH_REGVAL(RADEON_PP_TEX_SIZE_0
, ((width
- 1) |
155 ((height
- 1) << RADEON_TEX_VSIZE_SHIFT
)));
156 OUT_BATCH_REGVAL(RADEON_PP_TEX_PITCH_0
, pitch
* _mesa_get_format_bytes(mesa_format
) - 32);
158 OUT_BATCH_REGSEQ(RADEON_PP_TXOFFSET_0
, 1);
159 OUT_BATCH_RELOC(0, bo
, 0, RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0, 0);
164 static inline void emit_cb_setup(struct r100_context
*r100
,
165 struct radeon_bo
*bo
,
167 gl_format mesa_format
,
172 uint32_t dst_pitch
= pitch
;
173 uint32_t dst_format
= 0;
174 BATCH_LOCALS(&r100
->radeon
);
176 /* XXX others? BE/LE? */
177 switch (mesa_format
) {
178 case MESA_FORMAT_ARGB8888
:
179 case MESA_FORMAT_XRGB8888
:
180 dst_format
= RADEON_COLOR_FORMAT_ARGB8888
;
182 case MESA_FORMAT_RGB565
:
183 dst_format
= RADEON_COLOR_FORMAT_RGB565
;
185 case MESA_FORMAT_ARGB4444
:
186 dst_format
= RADEON_COLOR_FORMAT_ARGB4444
;
188 case MESA_FORMAT_ARGB1555
:
189 dst_format
= RADEON_COLOR_FORMAT_ARGB1555
;
194 dst_format
= RADEON_COLOR_FORMAT_RGB8
;
200 BEGIN_BATCH_NO_AUTOSTATE(18);
201 OUT_BATCH_REGVAL(RADEON_RE_TOP_LEFT
, 0);
202 OUT_BATCH_REGVAL(RADEON_RE_WIDTH_HEIGHT
, ((width
<< RADEON_RE_WIDTH_SHIFT
) |
203 (height
<< RADEON_RE_HEIGHT_SHIFT
)));
204 OUT_BATCH_REGVAL(RADEON_RB3D_PLANEMASK
, 0xffffffff);
205 OUT_BATCH_REGVAL(RADEON_RB3D_BLENDCNTL
, RADEON_SRC_BLEND_GL_ONE
| RADEON_DST_BLEND_GL_ZERO
);
206 OUT_BATCH_REGVAL(RADEON_RB3D_CNTL
, dst_format
);
208 OUT_BATCH_REGSEQ(RADEON_RB3D_COLOROFFSET
, 1);
209 OUT_BATCH_RELOC(0, bo
, 0, 0, RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0);
210 OUT_BATCH_REGSEQ(RADEON_RB3D_COLORPITCH
, 1);
211 OUT_BATCH_RELOC(dst_pitch
, bo
, dst_pitch
, 0, RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0);
216 static GLboolean
validate_buffers(struct r100_context
*r100
,
217 struct radeon_bo
*src_bo
,
218 struct radeon_bo
*dst_bo
)
222 radeon_cs_space_reset_bos(r100
->radeon
.cmdbuf
.cs
);
224 ret
= radeon_cs_space_check_with_bo(r100
->radeon
.cmdbuf
.cs
,
225 src_bo
, RADEON_GEM_DOMAIN_VRAM
| RADEON_GEM_DOMAIN_GTT
, 0);
229 ret
= radeon_cs_space_check_with_bo(r100
->radeon
.cmdbuf
.cs
,
230 dst_bo
, 0, RADEON_GEM_DOMAIN_VRAM
| RADEON_GEM_DOMAIN_GTT
);
238 * Calculate texcoords for given image region.
239 * Output values are [minx, maxx, miny, maxy]
241 static inline void calc_tex_coords(float img_width
, float img_height
,
243 float reg_width
, float reg_height
,
244 unsigned flip_y
, float *buf
)
246 buf
[0] = x
/ img_width
;
247 buf
[1] = buf
[0] + reg_width
/ img_width
;
248 buf
[2] = y
/ img_height
;
249 buf
[3] = buf
[2] + reg_height
/ img_height
;
252 buf
[2] = 1.0 - buf
[2];
253 buf
[3] = 1.0 - buf
[3];
257 static inline void emit_draw_packet(struct r100_context
*r100
,
258 unsigned src_width
, unsigned src_height
,
259 unsigned src_x_offset
, unsigned src_y_offset
,
260 unsigned dst_x_offset
, unsigned dst_y_offset
,
261 unsigned reg_width
, unsigned reg_height
,
266 BATCH_LOCALS(&r100
->radeon
);
268 calc_tex_coords(src_width
, src_height
,
269 src_x_offset
, src_y_offset
,
270 reg_width
, reg_height
,
273 verts
[0] = dst_x_offset
;
274 verts
[1] = dst_y_offset
+ reg_height
;
275 verts
[2] = texcoords
[0];
276 verts
[3] = texcoords
[3];
278 verts
[4] = dst_x_offset
+ reg_width
;
279 verts
[5] = dst_y_offset
+ reg_height
;
280 verts
[6] = texcoords
[1];
281 verts
[7] = texcoords
[3];
283 verts
[8] = dst_x_offset
+ reg_width
;
284 verts
[9] = dst_y_offset
;
285 verts
[10] = texcoords
[1];
286 verts
[11] = texcoords
[2];
289 OUT_BATCH(RADEON_CP_PACKET3_3D_DRAW_IMMD
| (13 << 16));
290 OUT_BATCH(RADEON_CP_VC_FRMT_XY
| RADEON_CP_VC_FRMT_ST0
);
291 OUT_BATCH(RADEON_CP_VC_CNTL_PRIM_WALK_RING
|
292 RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST
|
293 RADEON_CP_VC_CNTL_MAOS_ENABLE
|
294 RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE
|
296 OUT_BATCH_TABLE(verts
, 12);
301 * Copy a region of [@a width x @a height] pixels from source buffer
302 * to destination buffer.
303 * @param[in] r100 r100 context
304 * @param[in] src_bo source radeon buffer object
305 * @param[in] src_offset offset of the source image in the @a src_bo
306 * @param[in] src_mesaformat source image format
307 * @param[in] src_pitch aligned source image width
308 * @param[in] src_width source image width
309 * @param[in] src_height source image height
310 * @param[in] src_x_offset x offset in the source image
311 * @param[in] src_y_offset y offset in the source image
312 * @param[in] dst_bo destination radeon buffer object
313 * @param[in] dst_offset offset of the destination image in the @a dst_bo
314 * @param[in] dst_mesaformat destination image format
315 * @param[in] dst_pitch aligned destination image width
316 * @param[in] dst_width destination image width
317 * @param[in] dst_height destination image height
318 * @param[in] dst_x_offset x offset in the destination image
319 * @param[in] dst_y_offset y offset in the destination image
320 * @param[in] width region width
321 * @param[in] height region height
322 * @param[in] flip_y set if y coords of the source image need to be flipped
324 unsigned r100_blit(GLcontext
*ctx
,
325 struct radeon_bo
*src_bo
,
327 gl_format src_mesaformat
,
331 unsigned src_x_offset
,
332 unsigned src_y_offset
,
333 struct radeon_bo
*dst_bo
,
335 gl_format dst_mesaformat
,
339 unsigned dst_x_offset
,
340 unsigned dst_y_offset
,
345 struct r100_context
*r100
= R100_CONTEXT(ctx
);
347 if (!r100_check_blit(dst_mesaformat
))
350 /* Make sure that colorbuffer has even width - hw limitation */
351 if (dst_pitch
% 2 > 0)
354 /* Rendering to small buffer doesn't work.
355 * Looks like a hw limitation.
360 /* Need to clamp the region size to make sure
361 * we don't read outside of the source buffer
362 * or write outside of the destination buffer.
364 if (reg_width
+ src_x_offset
> src_width
)
365 reg_width
= src_width
- src_x_offset
;
366 if (reg_height
+ src_y_offset
> src_height
)
367 reg_height
= src_height
- src_y_offset
;
368 if (reg_width
+ dst_x_offset
> dst_width
)
369 reg_width
= dst_width
- dst_x_offset
;
370 if (reg_height
+ dst_y_offset
> dst_height
)
371 reg_height
= dst_height
- dst_y_offset
;
373 if (src_bo
== dst_bo
) {
377 if (src_offset
% 32 || dst_offset
% 32) {
382 fprintf(stderr
, "src: size [%d x %d], pitch %d, "
383 "offset [%d x %d], format %s, bo %p\n",
384 src_width
, src_height
, src_pitch
,
385 src_x_offset
, src_y_offset
,
386 _mesa_get_format_name(src_mesaformat
),
388 fprintf(stderr
, "dst: pitch %d, offset[%d x %d], format %s, bo %p\n",
389 dst_pitch
, dst_x_offset
, dst_y_offset
,
390 _mesa_get_format_name(dst_mesaformat
), dst_bo
);
391 fprintf(stderr
, "region: %d x %d\n", reg_width
, reg_height
);
394 /* Flush is needed to make sure that source buffer has correct data */
397 rcommonEnsureCmdBufSpace(&r100
->radeon
, 59, __FUNCTION__
);
399 if (!validate_buffers(r100
, src_bo
, dst_bo
))
403 emit_vtx_state(r100
);
405 emit_tx_setup(r100
, src_mesaformat
, src_bo
, src_offset
, src_width
, src_height
, src_pitch
);
407 emit_cb_setup(r100
, dst_bo
, dst_offset
, dst_mesaformat
, dst_pitch
, dst_width
, dst_height
);
409 emit_draw_packet(r100
, src_width
, src_height
,
410 src_x_offset
, src_y_offset
,
411 dst_x_offset
, dst_y_offset
,
412 reg_width
, reg_height
,