src/mesa/drivers/dri/radeon/radeon_bo_legacy.c

   1 /*
   2  * Copyright © 2008 Nicolai Haehnle
   3  * Copyright © 2008 Dave Airlie
   4  * Copyright © 2008 Jérôme Glisse
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * The above copyright notice and this permission notice (including the
  24  * next paragraph) shall be included in all copies or substantial portions
  25  * of the Software.
  26  */
  27 /*
  28  * Authors:
  29  *      Aapo Tahkola <aet@rasterburn.org>
  30  *      Nicolai Haehnle <prefect_@gmx.net>
  31  *      Dave Airlie
  32  *      Jérôme Glisse <glisse@freedesktop.org>
  33  */
  34 #include <stdio.h>
  35 #include <stdint.h>
  36 #include <stdlib.h>
  37 #include <string.h>
  38 #include <errno.h>
  39 #include <unistd.h>
  40 #include <sys/mman.h>
  41 #include <sys/ioctl.h>
  42 #include "xf86drm.h"
  43 #include "drm.h"
  44 #include "radeon_drm.h"
  45 #include "radeon_bo.h"
  46 #include "radeon_bo_legacy.h"
  47 #include "radeon_ioctl.h"
  48 #include "texmem.h"
  49
  50 struct bo_legacy {
  51     struct radeon_bo    base;
  52     driTextureObject    tobj_base;
  53     int                 map_count;
  54     uint32_t            pending;
  55     int                 is_pending;
  56     int                 validated;
  57     int                 static_bo;
  58     int                 got_dri_texture_obj;
  59     int                 dirty;
  60     uint32_t            offset;
  61     driTextureObject    dri_texture_obj;
  62     void                *ptr;
  63     struct bo_legacy    *next, *prev;
  64     struct bo_legacy    *pnext, *pprev;
  65 };
  66
  67 struct bo_manager_legacy {
  68     struct radeon_bo_manager    base;
  69     unsigned                    nhandle;
  70     unsigned                    nfree_handles;
  71     unsigned                    cfree_handles;
  72     uint32_t                    current_age;
  73     struct bo_legacy            bos;
  74     struct bo_legacy            pending_bos;
  75     uint32_t                    fb_location;
  76     uint32_t                    texture_offset;
  77     unsigned                    dma_alloc_size;
  78     unsigned                    cpendings;
  79     driTextureObject            texture_swapped;
  80     driTexHeap                  *texture_heap;
  81     struct radeon_screen        *screen;
  82     unsigned                    *free_handles;
  83 };
  84
  85 static void bo_legacy_tobj_destroy(void *data, driTextureObject *t)
  86 {
  87     struct bo_legacy *bo_legacy;
  88
  89     bo_legacy = (struct bo_legacy*)((char*)t)-sizeof(struct radeon_bo);
  90     bo_legacy->got_dri_texture_obj = 0;
  91     bo_legacy->validated = 0;
  92 }
  93
  94 static int legacy_new_handle(struct bo_manager_legacy *bom, uint32_t *handle)
  95 {
  96     uint32_t tmp;
  97
  98     *handle = 0;
  99     if (bom->nhandle == 0xFFFFFFFF) {
 100         return -EINVAL;
 101     }
 102     if (bom->cfree_handles > 0) {
 103         tmp = bom->free_handles[--bom->cfree_handles];
 104         while (!bom->free_handles[bom->cfree_handles - 1]) {
 105             bom->cfree_handles--;
 106             if (bom->cfree_handles <= 0) {
 107                 bom->cfree_handles = 0;
 108             }
 109         }
 110     } else {
 111         bom->cfree_handles = 0;
 112         tmp = bom->nhandle++;
 113     }
 114     assert(tmp);
 115     *handle = tmp;
 116     return 0;
 117 }
 118
 119 static int legacy_free_handle(struct bo_manager_legacy *bom, uint32_t handle)
 120 {
 121     uint32_t *handles;
 122
 123     if (!handle) {
 124         return 0;
 125     }
 126     if (handle == (bom->nhandle - 1)) {
 127         int i;
 128
 129         bom->nhandle--;
 130         for (i = bom->cfree_handles - 1; i >= 0; i--) {
 131             if (bom->free_handles[i] == (bom->nhandle - 1)) {
 132                 bom->nhandle--;
 133                 bom->free_handles[i] = 0;
 134             }
 135         }
 136         while (!bom->free_handles[bom->cfree_handles - 1]) {
 137             bom->cfree_handles--;
 138             if (bom->cfree_handles <= 0) {
 139                 bom->cfree_handles = 0;
 140             }
 141         }
 142         return 0;
 143     }
 144     if (bom->cfree_handles < bom->nfree_handles) {
 145         bom->free_handles[bom->cfree_handles++] = handle;
 146         return 0;
 147     }
 148     bom->nfree_handles += 0x100;
 149     handles = (uint32_t*)realloc(bom->free_handles, bom->nfree_handles * 4);
 150     if (handles == NULL) {
 151         bom->nfree_handles -= 0x100;
 152         return -ENOMEM;
 153     }
 154     bom->free_handles = handles;
 155     bom->free_handles[bom->cfree_handles++] = handle;
 156     return 0;
 157 }
 158
 159 static void legacy_get_current_age(struct bo_manager_legacy *boml)
 160 {
 161     drm_radeon_getparam_t gp;
 162     int r;
 163
 164     gp.param = RADEON_PARAM_LAST_CLEAR;
 165     gp.value = (int *)&boml->current_age;
 166     r = drmCommandWriteRead(boml->base.fd, DRM_RADEON_GETPARAM,
 167                             &gp, sizeof(gp));
 168     if (r) {
 169         fprintf(stderr, "%s: drmRadeonGetParam: %d\n", __FUNCTION__, r);
 170         exit(1);
 171     }
 172 }
 173
 174 static int legacy_is_pending(struct radeon_bo *bo)
 175 {
 176     struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bo->bom;
 177     struct bo_legacy *bo_legacy = (struct bo_legacy*)bo;
 178
 179     if (bo_legacy->is_pending <= 0) {
 180         bo_legacy->is_pending = 0;
 181         return 0;
 182     }
 183     if (boml->current_age >= bo_legacy->pending) {
 184         if (boml->pending_bos.pprev == bo_legacy) {
 185             boml->pending_bos.pprev = bo_legacy->pprev;
 186         }
 187         bo_legacy->pprev->pnext = bo_legacy->pnext;
 188         if (bo_legacy->pnext) {
 189             bo_legacy->pnext->pprev = bo_legacy->pprev;
 190         }
 191         while (bo_legacy->is_pending--) {
 192             radeon_bo_unref(bo);
 193         }
 194         bo_legacy->is_pending = 0;
 195         boml->cpendings--;
 196         return 0;
 197     }
 198     return 1;
 199 }
 200
 201 static int legacy_wait_pending(struct radeon_bo *bo)
 202 {
 203     struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bo->bom;
 204     struct bo_legacy *bo_legacy = (struct bo_legacy*)bo;
 205
 206     if (!bo_legacy->is_pending) {
 207         return 0;
 208     }
 209     /* FIXME: lockup and userspace busy looping that's all the folks */
 210     legacy_get_current_age(boml);
 211     while (legacy_is_pending(bo)) {
 212         usleep(10);
 213         legacy_get_current_age(boml);
 214     }
 215     return 0;
 216 }
 217
 218 static void legacy_track_pending(struct bo_manager_legacy *boml)
 219 {
 220     struct bo_legacy *bo_legacy;
 221     struct bo_legacy *next;
 222
 223     legacy_get_current_age(boml);
 224     bo_legacy = boml->pending_bos.pnext;
 225     while (bo_legacy) {
 226         next = bo_legacy->pnext;
 227         if (legacy_is_pending(&(bo_legacy->base))) {
 228         }
 229         bo_legacy = next;
 230     }
 231 }
 232
 233 static struct bo_legacy *bo_allocate(struct bo_manager_legacy *boml,
 234                                      uint32_t size,
 235                                      uint32_t alignment,
 236                                      uint32_t flags)
 237 {
 238     struct bo_legacy *bo_legacy;
 239
 240     bo_legacy = (struct bo_legacy*)calloc(1, sizeof(struct bo_legacy));
 241     if (bo_legacy == NULL) {
 242         return NULL;
 243     }
 244     bo_legacy->base.bom = (struct radeon_bo_manager*)boml;
 245     bo_legacy->base.handle = 0;
 246     bo_legacy->base.size = size;
 247     bo_legacy->base.alignment = alignment;
 248     bo_legacy->base.flags = flags;
 249     bo_legacy->base.ptr = NULL;
 250     bo_legacy->map_count = 0;
 251     bo_legacy->next = NULL;
 252     bo_legacy->prev = NULL;
 253     bo_legacy->got_dri_texture_obj = 0;
 254     bo_legacy->pnext = NULL;
 255     bo_legacy->pprev = NULL;
 256     bo_legacy->next = boml->bos.next;
 257     bo_legacy->prev = &boml->bos;
 258     boml->bos.next = bo_legacy;
 259     if (bo_legacy->next) {
 260         bo_legacy->next->prev = bo_legacy;
 261     }
 262     return bo_legacy;
 263 }
 264
 265 static int bo_dma_alloc(struct radeon_bo *bo)
 266 {
 267     struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bo->bom;
 268     struct bo_legacy *bo_legacy = (struct bo_legacy*)bo;
 269     drm_radeon_mem_alloc_t alloc;
 270     unsigned size;
 271     int base_offset;
 272     int r;
 273
 274     /* align size on 4Kb */
 275     size = (((4 * 1024) - 1) + bo->size) & ~((4 * 1024) - 1);
 276     alloc.region = RADEON_MEM_REGION_GART;
 277     alloc.alignment = bo_legacy->base.alignment;
 278     alloc.size = size;
 279     alloc.region_offset = &base_offset;
 280     r = drmCommandWriteRead(bo->bom->fd,
 281                             DRM_RADEON_ALLOC,
 282                             &alloc,
 283                             sizeof(alloc));
 284     if (r) {
 285         /* ptr is set to NULL if dma allocation failed */
 286         bo_legacy->ptr = NULL;
 287         exit(0);
 288         return r;
 289     }
 290     bo_legacy->ptr = boml->screen->gartTextures.map + base_offset;
 291     bo_legacy->offset = boml->screen->gart_texture_offset + base_offset;
 292     bo->size = size;
 293     boml->dma_alloc_size += size;
 294     return 0;
 295 }
 296
 297 static int bo_dma_free(struct radeon_bo *bo)
 298 {
 299     struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bo->bom;
 300     struct bo_legacy *bo_legacy = (struct bo_legacy*)bo;
 301     drm_radeon_mem_free_t memfree;
 302     int r;
 303
 304     if (bo_legacy->ptr == NULL) {
 305         /* ptr is set to NULL if dma allocation failed */
 306         return 0;
 307     }
 308     legacy_get_current_age(boml);
 309     memfree.region = RADEON_MEM_REGION_GART;
 310     memfree.region_offset  = bo_legacy->offset;
 311     memfree.region_offset -= boml->screen->gart_texture_offset;
 312     r = drmCommandWrite(boml->base.fd,
 313                         DRM_RADEON_FREE,
 314                         &memfree,
 315                         sizeof(memfree));
 316     if (r) {
 317         fprintf(stderr, "Failed to free bo[%p] at %08x\n",
 318                 &bo_legacy->base, memfree.region_offset);
 319         fprintf(stderr, "ret = %s\n", strerror(-r));
 320         return r;
 321     }
 322     boml->dma_alloc_size -= bo_legacy->base.size;
 323     return 0;
 324 }
 325
 326 static void bo_free(struct bo_legacy *bo_legacy)
 327 {
 328     struct bo_manager_legacy *boml;
 329
 330     if (bo_legacy == NULL) {
 331         return;
 332     }
 333     boml = (struct bo_manager_legacy *)bo_legacy->base.bom;
 334     bo_legacy->prev->next = bo_legacy->next;
 335     if (bo_legacy->next) {
 336         bo_legacy->next->prev = bo_legacy->prev;
 337     }
 338     if (!bo_legacy->static_bo) {
 339         legacy_free_handle(boml, bo_legacy->base.handle);
 340         if (bo_legacy->base.flags & RADEON_GEM_DOMAIN_GTT) {
 341             /* dma buffers */
 342             bo_dma_free(&bo_legacy->base);
 343         } else {
 344             /* free backing store */
 345             free(bo_legacy->ptr);
 346         }
 347     }
 348     memset(bo_legacy, 0 , sizeof(struct bo_legacy));
 349     free(bo_legacy);
 350 }
 351
 352 static struct radeon_bo *bo_open(struct radeon_bo_manager *bom,
 353                                  uint32_t handle,
 354                                  uint32_t size,
 355                                  uint32_t alignment,
 356                                  uint32_t flags)
 357 {
 358     struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bom;
 359     struct bo_legacy *bo_legacy;
 360     int r;
 361
 362     if (handle) {
 363         bo_legacy = boml->bos.next;
 364         while (bo_legacy) {
 365             if (bo_legacy->base.handle == handle) {
 366                 radeon_bo_ref(&(bo_legacy->base));
 367                 return (struct radeon_bo*)bo_legacy;
 368             }
 369             bo_legacy = bo_legacy->next;
 370         }
 371         return NULL;
 372     }
 373
 374     bo_legacy = bo_allocate(boml, size, alignment, flags);
 375     bo_legacy->static_bo = 0;
 376     r = legacy_new_handle(boml, &bo_legacy->base.handle);
 377     if (r) {
 378         bo_free(bo_legacy);
 379         return NULL;
 380     }
 381     if (bo_legacy->base.flags & RADEON_GEM_DOMAIN_GTT) {
 382         legacy_track_pending(boml);
 383         /* dma buffers */
 384         r = bo_dma_alloc(&(bo_legacy->base));
 385         if (r) {
 386             fprintf(stderr, "Ran out of GART memory (for %d)!\n", size);
 387             fprintf(stderr, "Please consider adjusting GARTSize option.\n");
 388             bo_free(bo_legacy);
 389             exit(-1);
 390             return NULL;
 391         }
 392     } else {
 393         bo_legacy->ptr = malloc(bo_legacy->base.size);
 394         if (bo_legacy->ptr == NULL) {
 395             bo_free(bo_legacy);
 396             return NULL;
 397         }
 398     }
 399     radeon_bo_ref(&(bo_legacy->base));
 400     return (struct radeon_bo*)bo_legacy;
 401 }
 402
 403 static void bo_ref(struct radeon_bo *bo)
 404 {
 405 }
 406
 407 static void bo_unref(struct radeon_bo *bo)
 408 {
 409     struct bo_legacy *bo_legacy = (struct bo_legacy*)bo;
 410
 411     if (bo->cref <= 0) {
 412         bo_legacy->prev->next = bo_legacy->next;
 413         if (bo_legacy->next) {
 414             bo_legacy->next->prev = bo_legacy->prev;
 415         }
 416         if (!bo_legacy->is_pending) {
 417             bo_free(bo_legacy);
 418         }
 419     }
 420 }
 421
 422 static int bo_map(struct radeon_bo *bo, int write)
 423 {
 424     struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bo->bom;
 425     struct bo_legacy *bo_legacy = (struct bo_legacy*)bo;
 426
 427     legacy_wait_pending(bo);
 428     bo_legacy->validated = 0;
 429     bo_legacy->dirty = 1;
 430     bo_legacy->map_count++;
 431     bo->ptr = bo_legacy->ptr;
 432     /* Read the first pixel in the frame buffer.  This should
 433      * be a noop, right?  In fact without this conform fails as reading
 434      * from the framebuffer sometimes produces old results -- the
 435      * on-card read cache gets mixed up and doesn't notice that the
 436      * framebuffer has been updated.
 437      *
 438      * Note that we should probably be reading some otherwise unused
 439      * region of VRAM, otherwise we might get incorrect results when
 440      * reading pixels from the top left of the screen.
 441      *
 442      * I found this problem on an R420 with glean's texCube test.
 443      * Note that the R200 span code also *writes* the first pixel in the
 444      * framebuffer, but I've found this to be unnecessary.
 445      *  -- Nicolai Hähnle, June 2008
 446      */
 447     {
 448         int p;
 449         volatile int *buf = (int*)boml->screen->driScreen->pFB;
 450         p = *buf;
 451     }
 452
 453     return 0;
 454 }
 455
 456 static int bo_unmap(struct radeon_bo *bo)
 457 {
 458     struct bo_legacy *bo_legacy = (struct bo_legacy*)bo;
 459
 460     if (--bo_legacy->map_count > 0) {
 461         return 0;
 462     }
 463     bo->ptr = NULL;
 464     return 0;
 465 }
 466
 467 static struct radeon_bo_funcs bo_legacy_funcs = {
 468     bo_open,
 469     bo_ref,
 470     bo_unref,
 471     bo_map,
 472     bo_unmap
 473 };
 474
 475 static int bo_vram_validate(struct radeon_bo *bo,
 476                             uint32_t *soffset,
 477                             uint32_t *eoffset)
 478 {
 479     struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bo->bom;
 480     struct bo_legacy *bo_legacy = (struct bo_legacy*)bo;
 481     int r;
 482
 483     if (!bo_legacy->got_dri_texture_obj) {
 484         make_empty_list(&bo_legacy->dri_texture_obj);
 485         bo_legacy->dri_texture_obj.totalSize = bo->size;
 486         r = driAllocateTexture(&boml->texture_heap, 1,
 487                                &bo_legacy->dri_texture_obj);
 488         if (r) {
 489             uint8_t *segfault=NULL;
 490             fprintf(stderr, "Ouch! vram_validate failed %d\n", r);
 491             *segfault=1;
 492             return -1;
 493         }
 494         bo_legacy->offset = boml->texture_offset +
 495                             bo_legacy->dri_texture_obj.memBlock->ofs;
 496         bo_legacy->got_dri_texture_obj = 1;
 497         bo_legacy->dirty = 1;
 498     }
 499     if (bo_legacy->dirty) {
 500         /* Copy to VRAM using a blit.
 501          * All memory is 4K aligned. We're using 1024 pixels wide blits.
 502          */
 503         drm_radeon_texture_t tex;
 504         drm_radeon_tex_image_t tmp;
 505         int ret;
 506
 507         tex.offset = bo_legacy->offset;
 508         tex.image = &tmp;
 509         assert(!(tex.offset & 1023));
 510
 511         tmp.x = 0;
 512         tmp.y = 0;
 513         if (bo->size < 4096) {
 514             tmp.width = (bo->size + 3) / 4;
 515             tmp.height = 1;
 516         } else {
 517             tmp.width = 1024;
 518             tmp.height = (bo->size + 4095) / 4096;
 519         }
 520         tmp.data = bo_legacy->ptr;
 521         tex.format = RADEON_TXFORMAT_ARGB8888;
 522         tex.width = tmp.width;
 523         tex.height = tmp.height;
 524         tex.pitch = MAX2(tmp.width / 16, 1);
 525         do {
 526             ret = drmCommandWriteRead(bo->bom->fd,
 527                                       DRM_RADEON_TEXTURE,
 528                                       &tex,
 529                                       sizeof(drm_radeon_texture_t));
 530             if (ret) {
 531                 if (RADEON_DEBUG & DEBUG_IOCTL)
 532                     fprintf(stderr, "DRM_RADEON_TEXTURE:  again!\n");
 533                 usleep(1);
 534             }
 535         } while (ret == -EAGAIN);
 536         bo_legacy->dirty = 0;
 537     }
 538     return 0;
 539 }
 540
 541 int radeon_bo_legacy_validate(struct radeon_bo *bo,
 542                               uint32_t *soffset,
 543                               uint32_t *eoffset)
 544 {
 545     struct bo_legacy *bo_legacy = (struct bo_legacy*)bo;
 546     int r;
 547
 548     if (bo_legacy->map_count) {
 549         fprintf(stderr, "bo(%p, %d) is mapped (%d) can't valide it.\n",
 550                 bo, bo->size, bo_legacy->map_count);
 551         return -EINVAL;
 552     }
 553     if (bo_legacy->static_bo || bo_legacy->validated) {
 554         *soffset = bo_legacy->offset;
 555         *eoffset = bo_legacy->offset + bo->size;
 556         return 0;
 557     }
 558     if (!(bo->flags & RADEON_GEM_DOMAIN_GTT)) {
 559         r = bo_vram_validate(bo, soffset, eoffset);
 560         if (r) {
 561             return r;
 562         }
 563     }
 564     *soffset = bo_legacy->offset;
 565     *eoffset = bo_legacy->offset + bo->size;
 566     bo_legacy->validated = 1;
 567     return 0;
 568 }
 569
 570 void radeon_bo_legacy_pending(struct radeon_bo *bo, uint32_t pending)
 571 {
 572     struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bo->bom;
 573     struct bo_legacy *bo_legacy = (struct bo_legacy*)bo;
 574
 575     bo_legacy->pending = pending;
 576     bo_legacy->is_pending += 1;
 577     /* add to pending list */
 578     radeon_bo_ref(bo);
 579     if (bo_legacy->is_pending > 1) {
 580         return;
 581     }
 582     bo_legacy->pprev = boml->pending_bos.pprev;
 583     bo_legacy->pnext = NULL;
 584     bo_legacy->pprev->pnext = bo_legacy;
 585     boml->pending_bos.pprev = bo_legacy;
 586     boml->cpendings++;
 587 }
 588
 589 void radeon_bo_manager_legacy_shutdown(struct radeon_bo_manager *bom)
 590 {
 591     struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bom;
 592     struct bo_legacy *bo_legacy;
 593
 594     if (bom == NULL) {
 595         return;
 596     }
 597     bo_legacy = boml->bos.next;
 598     while (bo_legacy) {
 599         struct bo_legacy *next;
 600
 601         next = bo_legacy->next;
 602         bo_free(bo_legacy);
 603         bo_legacy = next;
 604     }
 605     free(boml->free_handles);
 606     free(boml);
 607 }
 608
 609 struct radeon_bo_manager *radeon_bo_manager_legacy(struct radeon_screen *scrn)
 610 {
 611     struct bo_manager_legacy *bom;
 612     struct bo_legacy *bo;
 613     unsigned size;
 614
 615     bom = (struct bo_manager_legacy*)
 616           calloc(1, sizeof(struct bo_manager_legacy));
 617     if (bom == NULL) {
 618         return NULL;
 619     }
 620
 621     bom->texture_heap = driCreateTextureHeap(0,
 622                                              bom,
 623                                              scrn->texSize[0],
 624                                              12,
 625                                              RADEON_NR_TEX_REGIONS,
 626                                              (drmTextureRegionPtr)scrn->sarea->tex_list[0],
 627                                              &scrn->sarea->tex_age[0],
 628                                              &bom->texture_swapped,
 629                                              sizeof(struct bo_legacy),
 630                                              &bo_legacy_tobj_destroy);
 631     bom->texture_offset = scrn->texOffset[0];
 632
 633     bom->base.funcs = &bo_legacy_funcs;
 634     bom->base.fd = scrn->driScreen->fd;
 635     bom->bos.next = NULL;
 636     bom->bos.prev = NULL;
 637     bom->pending_bos.pprev = &bom->pending_bos;
 638     bom->pending_bos.pnext = NULL;
 639     bom->screen = scrn;
 640     bom->fb_location = scrn->fbLocation;
 641     bom->nhandle = 1;
 642     bom->cfree_handles = 0;
 643     bom->nfree_handles = 0x400;
 644     bom->free_handles = (uint32_t*)malloc(bom->nfree_handles * 4);
 645     if (bom->free_handles == NULL) {
 646         radeon_bo_manager_legacy_shutdown((struct radeon_bo_manager*)bom);
 647         return NULL;
 648     }
 649
 650     /* biggest framebuffer size */
 651     size = 4096*4096*4;
 652     /* allocate front */
 653     bo = bo_allocate(bom, size, 0, 0);
 654     if (bo == NULL) {
 655         radeon_bo_manager_legacy_shutdown((struct radeon_bo_manager*)bom);
 656         return NULL;
 657     }
 658     if (scrn->sarea->tiling_enabled) {
 659         bo->base.flags = RADEON_BO_FLAGS_MACRO_TILE;
 660     }
 661     bo->static_bo = 1;
 662     bo->offset = bom->screen->frontOffset + bom->fb_location;
 663     bo->base.handle = bo->offset;
 664     bo->ptr = scrn->driScreen->pFB + bom->screen->frontOffset;
 665     if (bo->base.handle > bom->nhandle) {
 666         bom->nhandle = bo->base.handle + 1;
 667     }
 668     /* allocate back */
 669     bo = bo_allocate(bom, size, 0, 0);
 670     if (bo == NULL) {
 671         radeon_bo_manager_legacy_shutdown((struct radeon_bo_manager*)bom);
 672         return NULL;
 673     }
 674     if (scrn->sarea->tiling_enabled) {
 675         bo->base.flags = RADEON_BO_FLAGS_MACRO_TILE;
 676     }
 677     bo->static_bo = 1;
 678     bo->offset = bom->screen->backOffset + bom->fb_location;
 679     bo->base.handle = bo->offset;
 680     bo->ptr = scrn->driScreen->pFB + bom->screen->backOffset;
 681     if (bo->base.handle > bom->nhandle) {
 682         bom->nhandle = bo->base.handle + 1;
 683     }
 684     /* allocate depth */
 685     bo = bo_allocate(bom, size, 0, 0);
 686     if (bo == NULL) {
 687         radeon_bo_manager_legacy_shutdown((struct radeon_bo_manager*)bom);
 688         return NULL;
 689     }
 690     bo->base.flags = 0;
 691     if (scrn->sarea->tiling_enabled) {
 692         bo->base.flags = RADEON_BO_FLAGS_MACRO_TILE;
 693     }
 694     bo->static_bo = 1;
 695     bo->offset = bom->screen->depthOffset + bom->fb_location;
 696     bo->base.handle = bo->offset;
 697     bo->ptr = scrn->driScreen->pFB + bom->screen->depthOffset;
 698     if (bo->base.handle > bom->nhandle) {
 699         bom->nhandle = bo->base.handle + 1;
 700     }
 701     return (struct radeon_bo_manager*)bom;
 702 }
 703
 704 void radeon_bo_legacy_texture_age(struct radeon_bo_manager *bom)
 705 {
 706     struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bom;
 707     DRI_AGE_TEXTURES(boml->texture_heap);
 708 }
 709
 710 unsigned radeon_bo_legacy_relocs_size(struct radeon_bo *bo)
 711 {
 712     struct bo_legacy *bo_legacy = (struct bo_legacy*)bo;
 713
 714     if (bo_legacy->static_bo || (bo->flags & RADEON_GEM_DOMAIN_GTT)) {
 715         return 0;
 716     }
 717     return bo->size;
 718 }