src/mesa/drivers/dri/radeon/radeon_bo_legacy.c

   1 /*
   2  * Copyright © 2008 Nicolai Haehnle
   3  * Copyright © 2008 Dave Airlie
   4  * Copyright © 2008 Jérôme Glisse
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * The above copyright notice and this permission notice (including the
  24  * next paragraph) shall be included in all copies or substantial portions
  25  * of the Software.
  26  */
  27 /*
  28  * Authors:
  29  *      Aapo Tahkola <aet@rasterburn.org>
  30  *      Nicolai Haehnle <prefect_@gmx.net>
  31  *      Dave Airlie
  32  *      Jérôme Glisse <glisse@freedesktop.org>
  33  */
  34 #include <stdio.h>
  35 #include <stdint.h>
  36 #include <stdlib.h>
  37 #include <string.h>
  38 #include <errno.h>
  39 #include <unistd.h>
  40 #include <sys/mman.h>
  41 #include <sys/ioctl.h>
  42 #include "xf86drm.h"
  43 #include "texmem.h"
  44 #include "main/simple_list.h"
  45
  46 #include "drm.h"
  47 #include "radeon_drm.h"
  48 #include "radeon_bo.h"
  49 #include "radeon_bo_legacy.h"
  50 #include "radeon_common.h"
  51
  52 struct bo_legacy {
  53     struct radeon_bo    base;
  54     driTextureObject    tobj_base;
  55     int                 map_count;
  56     uint32_t            pending;
  57     int                 is_pending;
  58     int                 validated;
  59     int                 static_bo;
  60     int                 got_dri_texture_obj;
  61     int                 dirty;
  62     uint32_t            offset;
  63     driTextureObject    dri_texture_obj;
  64     void                *ptr;
  65     struct bo_legacy    *next, *prev;
  66     struct bo_legacy    *pnext, *pprev;
  67 };
  68
  69 struct bo_manager_legacy {
  70     struct radeon_bo_manager    base;
  71     unsigned                    nhandle;
  72     unsigned                    nfree_handles;
  73     unsigned                    cfree_handles;
  74     uint32_t                    current_age;
  75     struct bo_legacy            bos;
  76     struct bo_legacy            pending_bos;
  77     uint32_t                    fb_location;
  78     uint32_t                    texture_offset;
  79     unsigned                    dma_alloc_size;
  80     uint32_t                    dma_buf_count;
  81     unsigned                    cpendings;
  82     driTextureObject            texture_swapped;
  83     driTexHeap                  *texture_heap;
  84     struct radeon_screen        *screen;
  85     unsigned                    *free_handles;
  86 };
  87
  88 static void bo_legacy_tobj_destroy(void *data, driTextureObject *t)
  89 {
  90     struct bo_legacy *bo_legacy;
  91
  92     bo_legacy = (struct bo_legacy*)((char*)t)-sizeof(struct radeon_bo);
  93     bo_legacy->got_dri_texture_obj = 0;
  94     bo_legacy->validated = 0;
  95 }
  96
  97 static void inline clean_handles(struct bo_manager_legacy *bom)
  98 {
  99   while (bom->cfree_handles > 0 &&
 100          !bom->free_handles[bom->cfree_handles - 1])
 101     bom->cfree_handles--;
 102
 103 }
 104 static int legacy_new_handle(struct bo_manager_legacy *bom, uint32_t *handle)
 105 {
 106     uint32_t tmp;
 107
 108     *handle = 0;
 109     if (bom->nhandle == 0xFFFFFFFF) {
 110         return -EINVAL;
 111     }
 112     if (bom->cfree_handles > 0) {
 113         tmp = bom->free_handles[--bom->cfree_handles];
 114         clean_handles(bom);
 115     } else {
 116         bom->cfree_handles = 0;
 117         tmp = bom->nhandle++;
 118     }
 119     assert(tmp);
 120     *handle = tmp;
 121     return 0;
 122 }
 123
 124 static int legacy_free_handle(struct bo_manager_legacy *bom, uint32_t handle)
 125 {
 126     uint32_t *handles;
 127
 128     if (!handle) {
 129         return 0;
 130     }
 131     if (handle == (bom->nhandle - 1)) {
 132         int i;
 133
 134         bom->nhandle--;
 135         for (i = bom->cfree_handles - 1; i >= 0; i--) {
 136             if (bom->free_handles[i] == (bom->nhandle - 1)) {
 137                 bom->nhandle--;
 138                 bom->free_handles[i] = 0;
 139             }
 140         }
 141         clean_handles(bom);
 142         return 0;
 143     }
 144     if (bom->cfree_handles < bom->nfree_handles) {
 145         bom->free_handles[bom->cfree_handles++] = handle;
 146         return 0;
 147     }
 148     bom->nfree_handles += 0x100;
 149     handles = (uint32_t*)realloc(bom->free_handles, bom->nfree_handles * 4);
 150     if (handles == NULL) {
 151         bom->nfree_handles -= 0x100;
 152         return -ENOMEM;
 153     }
 154     bom->free_handles = handles;
 155     bom->free_handles[bom->cfree_handles++] = handle;
 156     return 0;
 157 }
 158
 159 static void legacy_get_current_age(struct bo_manager_legacy *boml)
 160 {
 161     drm_radeon_getparam_t gp;
 162     int r;
 163
 164     if (IS_R300_CLASS(boml->screen)) {
 165         gp.param = RADEON_PARAM_LAST_CLEAR;
 166         gp.value = (int *)&boml->current_age;
 167         r = drmCommandWriteRead(boml->base.fd, DRM_RADEON_GETPARAM,
 168                              &gp, sizeof(gp));
 169         if (r) {
 170          fprintf(stderr, "%s: drmRadeonGetParam: %d\n", __FUNCTION__, r);
 171          exit(1);
 172        }
 173     } else
 174         boml->current_age = boml->screen->scratch[3];
 175 }
 176
 177 static int legacy_is_pending(struct radeon_bo *bo)
 178 {
 179     struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bo->bom;
 180     struct bo_legacy *bo_legacy = (struct bo_legacy*)bo;
 181
 182     if (bo_legacy->is_pending <= 0) {
 183         bo_legacy->is_pending = 0;
 184         return 0;
 185     }
 186     if (boml->current_age >= bo_legacy->pending) {
 187         if (boml->pending_bos.pprev == bo_legacy) {
 188             boml->pending_bos.pprev = bo_legacy->pprev;
 189         }
 190         bo_legacy->pprev->pnext = bo_legacy->pnext;
 191         if (bo_legacy->pnext) {
 192             bo_legacy->pnext->pprev = bo_legacy->pprev;
 193         }
 194         assert(bo_legacy->is_pending <= bo->cref);
 195         while (bo_legacy->is_pending--) {
 196             bo = radeon_bo_unref(bo);
 197             if (!bo)
 198               break;
 199         }
 200         if (bo)
 201           bo_legacy->is_pending = 0;
 202         boml->cpendings--;
 203         return 0;
 204     }
 205     return 1;
 206 }
 207
 208 static int legacy_wait_pending(struct radeon_bo *bo)
 209 {
 210     struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bo->bom;
 211     struct bo_legacy *bo_legacy = (struct bo_legacy*)bo;
 212
 213     if (!bo_legacy->is_pending) {
 214         return 0;
 215     }
 216     /* FIXME: lockup and userspace busy looping that's all the folks */
 217     legacy_get_current_age(boml);
 218     while (legacy_is_pending(bo)) {
 219         usleep(10);
 220         legacy_get_current_age(boml);
 221     }
 222     return 0;
 223 }
 224
 225 static void legacy_track_pending(struct bo_manager_legacy *boml, int debug)
 226 {
 227     struct bo_legacy *bo_legacy;
 228     struct bo_legacy *next;
 229
 230     legacy_get_current_age(boml);
 231     bo_legacy = boml->pending_bos.pnext;
 232     while (bo_legacy) {
 233         if (debug)
 234           fprintf(stderr,"pending %p %d %d %d\n", bo_legacy, bo_legacy->base.size,
 235                   boml->current_age, bo_legacy->pending);
 236         next = bo_legacy->pnext;
 237         if (legacy_is_pending(&(bo_legacy->base))) {
 238         }
 239         bo_legacy = next;
 240     }
 241 }
 242
 243 static int legacy_wait_any_pending(struct bo_manager_legacy *boml)
 244 {
 245     struct bo_legacy *bo_legacy;
 246     struct bo_legacy *next;
 247
 248     legacy_get_current_age(boml);
 249     bo_legacy = boml->pending_bos.pnext;
 250     if (!bo_legacy)
 251       return -1;
 252     legacy_wait_pending(&bo_legacy->base);
 253     return 0;
 254 }
 255
 256 static struct bo_legacy *bo_allocate(struct bo_manager_legacy *boml,
 257                                      uint32_t size,
 258                                      uint32_t alignment,
 259                                      uint32_t domains,
 260                                      uint32_t flags)
 261 {
 262     struct bo_legacy *bo_legacy;
 263     static int pgsize;
 264
 265     if (pgsize == 0)
 266         pgsize = getpagesize() - 1;
 267
 268     size = (size + pgsize) & ~pgsize;
 269
 270     bo_legacy = (struct bo_legacy*)calloc(1, sizeof(struct bo_legacy));
 271     if (bo_legacy == NULL) {
 272         return NULL;
 273     }
 274     bo_legacy->base.bom = (struct radeon_bo_manager*)boml;
 275     bo_legacy->base.handle = 0;
 276     bo_legacy->base.size = size;
 277     bo_legacy->base.alignment = alignment;
 278     bo_legacy->base.domains = domains;
 279     bo_legacy->base.flags = flags;
 280     bo_legacy->base.ptr = NULL;
 281     bo_legacy->map_count = 0;
 282     bo_legacy->next = NULL;
 283     bo_legacy->prev = NULL;
 284     bo_legacy->got_dri_texture_obj = 0;
 285     bo_legacy->pnext = NULL;
 286     bo_legacy->pprev = NULL;
 287     bo_legacy->next = boml->bos.next;
 288     bo_legacy->prev = &boml->bos;
 289     boml->bos.next = bo_legacy;
 290     if (bo_legacy->next) {
 291         bo_legacy->next->prev = bo_legacy;
 292     }
 293     return bo_legacy;
 294 }
 295
 296 static int bo_dma_alloc(struct radeon_bo *bo)
 297 {
 298     struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bo->bom;
 299     struct bo_legacy *bo_legacy = (struct bo_legacy*)bo;
 300     drm_radeon_mem_alloc_t alloc;
 301     unsigned size;
 302     int base_offset;
 303     int r;
 304
 305     /* align size on 4Kb */
 306     size = (((4 * 1024) - 1) + bo->size) & ~((4 * 1024) - 1);
 307     alloc.region = RADEON_MEM_REGION_GART;
 308     alloc.alignment = bo_legacy->base.alignment;
 309     alloc.size = size;
 310     alloc.region_offset = &base_offset;
 311     r = drmCommandWriteRead(bo->bom->fd,
 312                             DRM_RADEON_ALLOC,
 313                             &alloc,
 314                             sizeof(alloc));
 315     if (r) {
 316         /* ptr is set to NULL if dma allocation failed */
 317         bo_legacy->ptr = NULL;
 318         return r;
 319     }
 320     bo_legacy->ptr = boml->screen->gartTextures.map + base_offset;
 321     bo_legacy->offset = boml->screen->gart_texture_offset + base_offset;
 322     bo->size = size;
 323     boml->dma_alloc_size += size;
 324     boml->dma_buf_count++;
 325     return 0;
 326 }
 327
 328 static int bo_dma_free(struct radeon_bo *bo)
 329 {
 330     struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bo->bom;
 331     struct bo_legacy *bo_legacy = (struct bo_legacy*)bo;
 332     drm_radeon_mem_free_t memfree;
 333     int r;
 334
 335     if (bo_legacy->ptr == NULL) {
 336         /* ptr is set to NULL if dma allocation failed */
 337         return 0;
 338     }
 339     legacy_get_current_age(boml);
 340     memfree.region = RADEON_MEM_REGION_GART;
 341     memfree.region_offset  = bo_legacy->offset;
 342     memfree.region_offset -= boml->screen->gart_texture_offset;
 343     r = drmCommandWrite(boml->base.fd,
 344                         DRM_RADEON_FREE,
 345                         &memfree,
 346                         sizeof(memfree));
 347     if (r) {
 348         fprintf(stderr, "Failed to free bo[%p] at %08x\n",
 349                 &bo_legacy->base, memfree.region_offset);
 350         fprintf(stderr, "ret = %s\n", strerror(-r));
 351         return r;
 352     }
 353     boml->dma_alloc_size -= bo_legacy->base.size;
 354     boml->dma_buf_count--;
 355     return 0;
 356 }
 357
 358 static void bo_free(struct bo_legacy *bo_legacy)
 359 {
 360     struct bo_manager_legacy *boml;
 361
 362     if (bo_legacy == NULL) {
 363         return;
 364     }
 365     boml = (struct bo_manager_legacy *)bo_legacy->base.bom;
 366     bo_legacy->prev->next = bo_legacy->next;
 367     if (bo_legacy->next) {
 368         bo_legacy->next->prev = bo_legacy->prev;
 369     }
 370     if (!bo_legacy->static_bo) {
 371         legacy_free_handle(boml, bo_legacy->base.handle);
 372         if (bo_legacy->base.domains & RADEON_GEM_DOMAIN_GTT) {
 373             /* dma buffers */
 374             bo_dma_free(&bo_legacy->base);
 375         } else {
 376             /* free backing store */
 377             free(bo_legacy->ptr);
 378         }
 379     }
 380     memset(bo_legacy, 0 , sizeof(struct bo_legacy));
 381     free(bo_legacy);
 382 }
 383
 384 static struct radeon_bo *bo_open(struct radeon_bo_manager *bom,
 385                                  uint32_t handle,
 386                                  uint32_t size,
 387                                  uint32_t alignment,
 388                                  uint32_t domains,
 389                                  uint32_t flags)
 390 {
 391     struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bom;
 392     struct bo_legacy *bo_legacy;
 393     int r;
 394
 395     if (handle) {
 396         bo_legacy = boml->bos.next;
 397         while (bo_legacy) {
 398             if (bo_legacy->base.handle == handle) {
 399                 radeon_bo_ref(&(bo_legacy->base));
 400                 return (struct radeon_bo*)bo_legacy;
 401             }
 402             bo_legacy = bo_legacy->next;
 403         }
 404         return NULL;
 405     }
 406
 407     bo_legacy = bo_allocate(boml, size, alignment, domains, flags);
 408     bo_legacy->static_bo = 0;
 409     r = legacy_new_handle(boml, &bo_legacy->base.handle);
 410     if (r) {
 411         bo_free(bo_legacy);
 412         return NULL;
 413     }
 414     if (bo_legacy->base.domains & RADEON_GEM_DOMAIN_GTT) {
 415     retry:
 416         legacy_track_pending(boml, 0);
 417         /* dma buffers */
 418
 419         r = bo_dma_alloc(&(bo_legacy->base));
 420         if (r) {
 421           if (legacy_wait_any_pending(boml) == -1) {
 422             bo_free(bo_legacy);
 423             return NULL;
 424           }
 425           goto retry;
 426           return NULL;
 427         }
 428     } else {
 429         bo_legacy->ptr = malloc(bo_legacy->base.size);
 430         if (bo_legacy->ptr == NULL) {
 431             bo_free(bo_legacy);
 432             return NULL;
 433         }
 434     }
 435     radeon_bo_ref(&(bo_legacy->base));
 436     return (struct radeon_bo*)bo_legacy;
 437 }
 438
 439 static void bo_ref(struct radeon_bo *bo)
 440 {
 441 }
 442
 443 static struct radeon_bo *bo_unref(struct radeon_bo *bo)
 444 {
 445     struct bo_legacy *bo_legacy = (struct bo_legacy*)bo;
 446
 447     if (bo->cref <= 0) {
 448         bo_legacy->prev->next = bo_legacy->next;
 449         if (bo_legacy->next) {
 450             bo_legacy->next->prev = bo_legacy->prev;
 451         }
 452         if (!bo_legacy->is_pending) {
 453             bo_free(bo_legacy);
 454         }
 455         return NULL;
 456     }
 457     return bo;
 458 }
 459
 460 static int bo_map(struct radeon_bo *bo, int write)
 461 {
 462     struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bo->bom;
 463     struct bo_legacy *bo_legacy = (struct bo_legacy*)bo;
 464
 465     legacy_wait_pending(bo);
 466     bo_legacy->validated = 0;
 467     bo_legacy->dirty = 1;
 468     bo_legacy->map_count++;
 469     bo->ptr = bo_legacy->ptr;
 470     /* Read the first pixel in the frame buffer.  This should
 471      * be a noop, right?  In fact without this conform fails as reading
 472      * from the framebuffer sometimes produces old results -- the
 473      * on-card read cache gets mixed up and doesn't notice that the
 474      * framebuffer has been updated.
 475      *
 476      * Note that we should probably be reading some otherwise unused
 477      * region of VRAM, otherwise we might get incorrect results when
 478      * reading pixels from the top left of the screen.
 479      *
 480      * I found this problem on an R420 with glean's texCube test.
 481      * Note that the R200 span code also *writes* the first pixel in the
 482      * framebuffer, but I've found this to be unnecessary.
 483      *  -- Nicolai Hähnle, June 2008
 484      */
 485     if (!(bo->domains & RADEON_GEM_DOMAIN_GTT)) {
 486         int p;
 487         volatile int *buf = (int*)boml->screen->driScreen->pFB;
 488         p = *buf;
 489     }
 490     return 0;
 491 }
 492
 493 static int bo_unmap(struct radeon_bo *bo)
 494 {
 495     struct bo_legacy *bo_legacy = (struct bo_legacy*)bo;
 496
 497     if (--bo_legacy->map_count > 0) {
 498         return 0;
 499     }
 500     bo->ptr = NULL;
 501     return 0;
 502 }
 503
 504 static struct radeon_bo_funcs bo_legacy_funcs = {
 505     bo_open,
 506     bo_ref,
 507     bo_unref,
 508     bo_map,
 509     bo_unmap
 510 };
 511
 512 static int bo_vram_validate(struct radeon_bo *bo,
 513                             uint32_t *soffset,
 514                             uint32_t *eoffset)
 515 {
 516     struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bo->bom;
 517     struct bo_legacy *bo_legacy = (struct bo_legacy*)bo;
 518     int r;
 519
 520     if (!bo_legacy->got_dri_texture_obj) {
 521         make_empty_list(&bo_legacy->dri_texture_obj);
 522         bo_legacy->dri_texture_obj.totalSize = bo->size;
 523         r = driAllocateTexture(&boml->texture_heap, 1,
 524                                &bo_legacy->dri_texture_obj);
 525         if (r) {
 526             uint8_t *segfault=NULL;
 527             fprintf(stderr, "Ouch! vram_validate failed %d\n", r);
 528             *segfault=1;
 529             return -1;
 530         }
 531         bo_legacy->offset = boml->texture_offset +
 532                             bo_legacy->dri_texture_obj.memBlock->ofs;
 533         bo_legacy->got_dri_texture_obj = 1;
 534         bo_legacy->dirty = 1;
 535     }
 536     if (bo_legacy->dirty) {
 537         /* Copy to VRAM using a blit.
 538          * All memory is 4K aligned. We're using 1024 pixels wide blits.
 539          */
 540         drm_radeon_texture_t tex;
 541         drm_radeon_tex_image_t tmp;
 542         int ret;
 543
 544         tex.offset = bo_legacy->offset;
 545         tex.image = &tmp;
 546         assert(!(tex.offset & 1023));
 547
 548         tmp.x = 0;
 549         tmp.y = 0;
 550         if (bo->size < 4096) {
 551             tmp.width = (bo->size + 3) / 4;
 552             tmp.height = 1;
 553         } else {
 554             tmp.width = 1024;
 555             tmp.height = (bo->size + 4095) / 4096;
 556         }
 557         tmp.data = bo_legacy->ptr;
 558         tex.format = RADEON_TXFORMAT_ARGB8888;
 559         tex.width = tmp.width;
 560         tex.height = tmp.height;
 561         tex.pitch = MAX2(tmp.width / 16, 1);
 562         do {
 563             ret = drmCommandWriteRead(bo->bom->fd,
 564                                       DRM_RADEON_TEXTURE,
 565                                       &tex,
 566                                       sizeof(drm_radeon_texture_t));
 567             if (ret) {
 568                 if (RADEON_DEBUG & DEBUG_IOCTL)
 569                     fprintf(stderr, "DRM_RADEON_TEXTURE:  again!\n");
 570                 usleep(1);
 571             }
 572         } while (ret == -EAGAIN);
 573         bo_legacy->dirty = 0;
 574     }
 575     return 0;
 576 }
 577
 578 int radeon_bo_legacy_validate(struct radeon_bo *bo,
 579                               uint32_t *soffset,
 580                               uint32_t *eoffset)
 581 {
 582     struct bo_legacy *bo_legacy = (struct bo_legacy*)bo;
 583     int r;
 584
 585     if (bo_legacy->map_count) {
 586         fprintf(stderr, "bo(%p, %d) is mapped (%d) can't valide it.\n",
 587                 bo, bo->size, bo_legacy->map_count);
 588         return -EINVAL;
 589     }
 590     if (bo_legacy->static_bo || bo_legacy->validated) {
 591         *soffset = bo_legacy->offset;
 592         *eoffset = bo_legacy->offset + bo->size;
 593         return 0;
 594     }
 595     if (!(bo->domains & RADEON_GEM_DOMAIN_GTT)) {
 596         r = bo_vram_validate(bo, soffset, eoffset);
 597         if (r) {
 598             return r;
 599         }
 600     }
 601     *soffset = bo_legacy->offset;
 602     *eoffset = bo_legacy->offset + bo->size;
 603     bo_legacy->validated = 1;
 604     return 0;
 605 }
 606
 607 void radeon_bo_legacy_pending(struct radeon_bo *bo, uint32_t pending)
 608 {
 609     struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bo->bom;
 610     struct bo_legacy *bo_legacy = (struct bo_legacy*)bo;
 611
 612     bo_legacy->pending = pending;
 613     bo_legacy->is_pending++;
 614     /* add to pending list */
 615     radeon_bo_ref(bo);
 616     if (bo_legacy->is_pending > 1) {
 617         return;
 618     }
 619     bo_legacy->pprev = boml->pending_bos.pprev;
 620     bo_legacy->pnext = NULL;
 621     bo_legacy->pprev->pnext = bo_legacy;
 622     boml->pending_bos.pprev = bo_legacy;
 623     boml->cpendings++;
 624 }
 625
 626 void radeon_bo_manager_legacy_dtor(struct radeon_bo_manager *bom)
 627 {
 628     struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bom;
 629     struct bo_legacy *bo_legacy;
 630
 631     if (bom == NULL) {
 632         return;
 633     }
 634     bo_legacy = boml->bos.next;
 635     while (bo_legacy) {
 636         struct bo_legacy *next;
 637
 638         next = bo_legacy->next;
 639         bo_free(bo_legacy);
 640         bo_legacy = next;
 641     }
 642     free(boml->free_handles);
 643     free(boml);
 644 }
 645
 646 static struct bo_legacy *radeon_legacy_bo_alloc_static(struct bo_manager_legacy *bom,
 647                                                        int size, uint32_t offset)
 648 {
 649     struct bo_legacy *bo;
 650
 651     bo = bo_allocate(bom, size, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 652     if (bo == NULL)
 653         return NULL;
 654     bo->static_bo = 1;
 655     bo->offset = offset + bom->fb_location;
 656     bo->base.handle = bo->offset;
 657     bo->ptr = bom->screen->driScreen->pFB + offset;
 658     if (bo->base.handle > bom->nhandle) {
 659         bom->nhandle = bo->base.handle + 1;
 660     }
 661     radeon_bo_ref(&(bo->base));
 662     return bo;
 663 }
 664
 665 struct radeon_bo_manager *radeon_bo_manager_legacy_ctor(struct radeon_screen *scrn)
 666 {
 667     struct bo_manager_legacy *bom;
 668     struct bo_legacy *bo;
 669     unsigned size;
 670
 671     bom = (struct bo_manager_legacy*)
 672           calloc(1, sizeof(struct bo_manager_legacy));
 673     if (bom == NULL) {
 674         return NULL;
 675     }
 676
 677     bom->texture_heap = driCreateTextureHeap(0,
 678                                              bom,
 679                                              scrn->texSize[0],
 680                                              12,
 681                                              RADEON_NR_TEX_REGIONS,
 682                                              (drmTextureRegionPtr)scrn->sarea->tex_list[0],
 683                                              &scrn->sarea->tex_age[0],
 684                                              &bom->texture_swapped,
 685                                              sizeof(struct bo_legacy),
 686                                              &bo_legacy_tobj_destroy);
 687     bom->texture_offset = scrn->texOffset[0];
 688
 689     bom->base.funcs = &bo_legacy_funcs;
 690     bom->base.fd = scrn->driScreen->fd;
 691     bom->bos.next = NULL;
 692     bom->bos.prev = NULL;
 693     bom->pending_bos.pprev = &bom->pending_bos;
 694     bom->pending_bos.pnext = NULL;
 695     bom->screen = scrn;
 696     bom->fb_location = scrn->fbLocation;
 697     bom->nhandle = 1;
 698     bom->cfree_handles = 0;
 699     bom->nfree_handles = 0x400;
 700     bom->free_handles = (uint32_t*)malloc(bom->nfree_handles * 4);
 701     if (bom->free_handles == NULL) {
 702         radeon_bo_manager_legacy_dtor((struct radeon_bo_manager*)bom);
 703         return NULL;
 704     }
 705
 706     /* biggest framebuffer size */
 707     size = 4096*4096*4;
 708
 709     /* allocate front */
 710     bo = radeon_legacy_bo_alloc_static(bom, size, bom->screen->frontOffset);
 711     if (!bo) {
 712         radeon_bo_manager_legacy_dtor((struct radeon_bo_manager*)bom);
 713         return NULL;
 714     }
 715     if (scrn->sarea->tiling_enabled) {
 716         bo->base.flags = RADEON_BO_FLAGS_MACRO_TILE;
 717     }
 718
 719     /* allocate back */
 720     bo = radeon_legacy_bo_alloc_static(bom, size, bom->screen->backOffset);
 721     if (!bo) {
 722         radeon_bo_manager_legacy_dtor((struct radeon_bo_manager*)bom);
 723         return NULL;
 724     }
 725     if (scrn->sarea->tiling_enabled) {
 726         bo->base.flags = RADEON_BO_FLAGS_MACRO_TILE;
 727     }
 728
 729     /* allocate depth */
 730     bo = radeon_legacy_bo_alloc_static(bom, size, bom->screen->depthOffset);
 731     if (!bo) {
 732         radeon_bo_manager_legacy_dtor((struct radeon_bo_manager*)bom);
 733         return NULL;
 734     }
 735     bo->base.flags = 0;
 736     if (scrn->sarea->tiling_enabled) {
 737         bo->base.flags |= RADEON_BO_FLAGS_MACRO_TILE;
 738         bo->base.flags |= RADEON_BO_FLAGS_MICRO_TILE;
 739     }
 740     return (struct radeon_bo_manager*)bom;
 741 }
 742
 743 void radeon_bo_legacy_texture_age(struct radeon_bo_manager *bom)
 744 {
 745     struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bom;
 746     DRI_AGE_TEXTURES(boml->texture_heap);
 747 }
 748
 749 unsigned radeon_bo_legacy_relocs_size(struct radeon_bo *bo)
 750 {
 751     struct bo_legacy *bo_legacy = (struct bo_legacy*)bo;
 752
 753     if (bo_legacy->static_bo || (bo->domains & RADEON_GEM_DOMAIN_GTT)) {
 754         return 0;
 755     }
 756     return bo->size;
 757 }
 758
 759 int radeon_legacy_bo_is_static(struct radeon_bo *bo)
 760 {
 761     struct bo_legacy *bo_legacy = (struct bo_legacy*)bo;
 762     return bo_legacy->static_bo;
 763 }
 764