2 * Copyright © 2008 Nicolai Haehnle
3 * Copyright © 2008 Dave Airlie
4 * Copyright © 2008 Jérôme Glisse
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
29 * Aapo Tahkola <aet@rasterburn.org>
30 * Nicolai Haehnle <prefect_@gmx.net>
32 * Jérôme Glisse <glisse@freedesktop.org>
42 #include <sys/ioctl.h>
45 #include "main/simple_list.h"
48 #include "radeon_drm.h"
49 #include "radeon_common.h"
50 #include "radeon_bocs_wrapper.h"
51 #include "radeon_macros.h"
53 /* no seriously texmem.c is this screwed up */
54 struct bo_legacy_texture_object
{
55 driTextureObject base
;
56 struct bo_legacy
*parent
;
60 struct radeon_bo base
;
66 struct bo_legacy_texture_object
*tobj
;
70 struct bo_legacy
*next
, *prev
;
71 struct bo_legacy
*pnext
, *pprev
;
74 struct bo_manager_legacy
{
75 struct radeon_bo_manager base
;
77 unsigned nfree_handles
;
78 unsigned cfree_handles
;
81 struct bo_legacy pending_bos
;
83 uint32_t texture_offset
;
84 unsigned dma_alloc_size
;
85 uint32_t dma_buf_count
;
87 driTextureObject texture_swapped
;
88 driTexHeap
*texture_heap
;
89 struct radeon_screen
*screen
;
90 unsigned *free_handles
;
93 static void bo_legacy_tobj_destroy(void *data
, driTextureObject
*t
)
95 struct bo_legacy_texture_object
*tobj
= (struct bo_legacy_texture_object
*)t
;
98 tobj
->parent
->tobj
= NULL
;
99 tobj
->parent
->validated
= 0;
103 static void inline clean_handles(struct bo_manager_legacy
*bom
)
105 while (bom
->cfree_handles
> 0 &&
106 !bom
->free_handles
[bom
->cfree_handles
- 1])
107 bom
->cfree_handles
--;
110 static int legacy_new_handle(struct bo_manager_legacy
*bom
, uint32_t *handle
)
115 if (bom
->nhandle
== 0xFFFFFFFF) {
118 if (bom
->cfree_handles
> 0) {
119 tmp
= bom
->free_handles
[--bom
->cfree_handles
];
122 bom
->cfree_handles
= 0;
123 tmp
= bom
->nhandle
++;
130 static int legacy_free_handle(struct bo_manager_legacy
*bom
, uint32_t handle
)
137 if (handle
== (bom
->nhandle
- 1)) {
141 for (i
= bom
->cfree_handles
- 1; i
>= 0; i
--) {
142 if (bom
->free_handles
[i
] == (bom
->nhandle
- 1)) {
144 bom
->free_handles
[i
] = 0;
150 if (bom
->cfree_handles
< bom
->nfree_handles
) {
151 bom
->free_handles
[bom
->cfree_handles
++] = handle
;
154 bom
->nfree_handles
+= 0x100;
155 handles
= (uint32_t*)realloc(bom
->free_handles
, bom
->nfree_handles
* 4);
156 if (handles
== NULL
) {
157 bom
->nfree_handles
-= 0x100;
160 bom
->free_handles
= handles
;
161 bom
->free_handles
[bom
->cfree_handles
++] = handle
;
165 static void legacy_get_current_age(struct bo_manager_legacy
*boml
)
167 drm_radeon_getparam_t gp
;
168 unsigned char *RADEONMMIO
= NULL
;
171 if (IS_R300_CLASS(boml
->screen
)) {
172 gp
.param
= RADEON_PARAM_LAST_CLEAR
;
173 gp
.value
= (int *)&boml
->current_age
;
174 r
= drmCommandWriteRead(boml
->base
.fd
, DRM_RADEON_GETPARAM
,
177 fprintf(stderr
, "%s: drmRadeonGetParam: %d\n", __FUNCTION__
, r
);
181 RADEONMMIO
= boml
->screen
->mmio
.map
;
182 boml
->current_age
= boml
->screen
->scratch
[3];
183 boml
->current_age
= INREG(RADEON_GUI_SCRATCH_REG3
);
187 static int legacy_is_pending(struct radeon_bo
*bo
)
189 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bo
->bom
;
190 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
192 if (bo_legacy
->is_pending
<= 0) {
193 bo_legacy
->is_pending
= 0;
196 if (boml
->current_age
>= bo_legacy
->pending
) {
197 if (boml
->pending_bos
.pprev
== bo_legacy
) {
198 boml
->pending_bos
.pprev
= bo_legacy
->pprev
;
200 bo_legacy
->pprev
->pnext
= bo_legacy
->pnext
;
201 if (bo_legacy
->pnext
) {
202 bo_legacy
->pnext
->pprev
= bo_legacy
->pprev
;
204 assert(bo_legacy
->is_pending
<= bo
->cref
);
205 while (bo_legacy
->is_pending
--) {
206 bo
= radeon_bo_unref(bo
);
211 bo_legacy
->is_pending
= 0;
218 static int legacy_wait_pending(struct radeon_bo
*bo
)
220 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bo
->bom
;
221 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
223 if (!bo_legacy
->is_pending
) {
226 /* FIXME: lockup and userspace busy looping that's all the folks */
227 legacy_get_current_age(boml
);
228 while (legacy_is_pending(bo
)) {
230 legacy_get_current_age(boml
);
235 static void legacy_track_pending(struct bo_manager_legacy
*boml
, int debug
)
237 struct bo_legacy
*bo_legacy
;
238 struct bo_legacy
*next
;
240 legacy_get_current_age(boml
);
241 bo_legacy
= boml
->pending_bos
.pnext
;
244 fprintf(stderr
,"pending %p %d %d %d\n", bo_legacy
, bo_legacy
->base
.size
,
245 boml
->current_age
, bo_legacy
->pending
);
246 next
= bo_legacy
->pnext
;
247 if (legacy_is_pending(&(bo_legacy
->base
))) {
253 static int legacy_wait_any_pending(struct bo_manager_legacy
*boml
)
255 struct bo_legacy
*bo_legacy
;
257 legacy_get_current_age(boml
);
258 bo_legacy
= boml
->pending_bos
.pnext
;
261 legacy_wait_pending(&bo_legacy
->base
);
265 static void legacy_kick_all_buffers(struct bo_manager_legacy
*boml
)
267 struct bo_legacy
*legacy
;
269 legacy
= boml
->bos
.next
;
270 while (legacy
!= &boml
->bos
) {
272 if (legacy
->validated
) {
273 driDestroyTextureObject(&legacy
->tobj
->base
);
275 legacy
->validated
= 0;
278 legacy
= legacy
->next
;
282 static struct bo_legacy
*bo_allocate(struct bo_manager_legacy
*boml
,
288 struct bo_legacy
*bo_legacy
;
292 pgsize
= getpagesize() - 1;
294 size
= (size
+ pgsize
) & ~pgsize
;
296 bo_legacy
= (struct bo_legacy
*)calloc(1, sizeof(struct bo_legacy
));
297 if (bo_legacy
== NULL
) {
300 bo_legacy
->base
.bom
= (struct radeon_bo_manager
*)boml
;
301 bo_legacy
->base
.handle
= 0;
302 bo_legacy
->base
.size
= size
;
303 bo_legacy
->base
.alignment
= alignment
;
304 bo_legacy
->base
.domains
= domains
;
305 bo_legacy
->base
.flags
= flags
;
306 bo_legacy
->base
.ptr
= NULL
;
307 bo_legacy
->map_count
= 0;
308 bo_legacy
->next
= NULL
;
309 bo_legacy
->prev
= NULL
;
310 bo_legacy
->pnext
= NULL
;
311 bo_legacy
->pprev
= NULL
;
312 bo_legacy
->next
= boml
->bos
.next
;
313 bo_legacy
->prev
= &boml
->bos
;
314 boml
->bos
.next
= bo_legacy
;
315 if (bo_legacy
->next
) {
316 bo_legacy
->next
->prev
= bo_legacy
;
321 static int bo_dma_alloc(struct radeon_bo
*bo
)
323 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bo
->bom
;
324 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
325 drm_radeon_mem_alloc_t alloc
;
330 /* align size on 4Kb */
331 size
= (((4 * 1024) - 1) + bo
->size
) & ~((4 * 1024) - 1);
332 alloc
.region
= RADEON_MEM_REGION_GART
;
333 alloc
.alignment
= bo_legacy
->base
.alignment
;
335 alloc
.region_offset
= &base_offset
;
336 r
= drmCommandWriteRead(bo
->bom
->fd
,
341 /* ptr is set to NULL if dma allocation failed */
342 bo_legacy
->ptr
= NULL
;
345 bo_legacy
->ptr
= boml
->screen
->gartTextures
.map
+ base_offset
;
346 bo_legacy
->offset
= boml
->screen
->gart_texture_offset
+ base_offset
;
348 boml
->dma_alloc_size
+= size
;
349 boml
->dma_buf_count
++;
353 static int bo_dma_free(struct radeon_bo
*bo
)
355 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bo
->bom
;
356 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
357 drm_radeon_mem_free_t memfree
;
360 if (bo_legacy
->ptr
== NULL
) {
361 /* ptr is set to NULL if dma allocation failed */
364 legacy_get_current_age(boml
);
365 memfree
.region
= RADEON_MEM_REGION_GART
;
366 memfree
.region_offset
= bo_legacy
->offset
;
367 memfree
.region_offset
-= boml
->screen
->gart_texture_offset
;
368 r
= drmCommandWrite(boml
->base
.fd
,
373 fprintf(stderr
, "Failed to free bo[%p] at %08x\n",
374 &bo_legacy
->base
, memfree
.region_offset
);
375 fprintf(stderr
, "ret = %s\n", strerror(-r
));
378 boml
->dma_alloc_size
-= bo_legacy
->base
.size
;
379 boml
->dma_buf_count
--;
383 static void bo_free(struct bo_legacy
*bo_legacy
)
385 struct bo_manager_legacy
*boml
;
387 if (bo_legacy
== NULL
) {
390 boml
= (struct bo_manager_legacy
*)bo_legacy
->base
.bom
;
391 bo_legacy
->prev
->next
= bo_legacy
->next
;
392 if (bo_legacy
->next
) {
393 bo_legacy
->next
->prev
= bo_legacy
->prev
;
395 if (!bo_legacy
->static_bo
) {
396 legacy_free_handle(boml
, bo_legacy
->base
.handle
);
397 if (bo_legacy
->base
.domains
& RADEON_GEM_DOMAIN_GTT
) {
399 bo_dma_free(&bo_legacy
->base
);
401 driDestroyTextureObject(&bo_legacy
->tobj
->base
);
402 bo_legacy
->tobj
= NULL
;
403 /* free backing store */
404 free(bo_legacy
->ptr
);
407 memset(bo_legacy
, 0 , sizeof(struct bo_legacy
));
411 static struct radeon_bo
*bo_open(struct radeon_bo_manager
*bom
,
418 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bom
;
419 struct bo_legacy
*bo_legacy
;
423 bo_legacy
= boml
->bos
.next
;
425 if (bo_legacy
->base
.handle
== handle
) {
426 radeon_bo_ref(&(bo_legacy
->base
));
427 return (struct radeon_bo
*)bo_legacy
;
429 bo_legacy
= bo_legacy
->next
;
434 bo_legacy
= bo_allocate(boml
, size
, alignment
, domains
, flags
);
435 bo_legacy
->static_bo
= 0;
436 r
= legacy_new_handle(boml
, &bo_legacy
->base
.handle
);
441 if (bo_legacy
->base
.domains
& RADEON_GEM_DOMAIN_GTT
) {
443 legacy_track_pending(boml
, 0);
446 r
= bo_dma_alloc(&(bo_legacy
->base
));
448 if (legacy_wait_any_pending(boml
) == -1) {
456 bo_legacy
->ptr
= malloc(bo_legacy
->base
.size
);
457 if (bo_legacy
->ptr
== NULL
) {
462 radeon_bo_ref(&(bo_legacy
->base
));
463 return (struct radeon_bo
*)bo_legacy
;
466 static void bo_ref(struct radeon_bo
*bo
)
470 static struct radeon_bo
*bo_unref(struct radeon_bo
*bo
)
472 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
475 bo_legacy
->prev
->next
= bo_legacy
->next
;
476 if (bo_legacy
->next
) {
477 bo_legacy
->next
->prev
= bo_legacy
->prev
;
479 if (!bo_legacy
->is_pending
) {
487 static int bo_map(struct radeon_bo
*bo
, int write
)
489 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bo
->bom
;
490 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
492 legacy_wait_pending(bo
);
493 bo_legacy
->validated
= 0;
494 bo_legacy
->dirty
= 1;
495 bo_legacy
->map_count
++;
496 bo
->ptr
= bo_legacy
->ptr
;
497 /* Read the first pixel in the frame buffer. This should
498 * be a noop, right? In fact without this conform fails as reading
499 * from the framebuffer sometimes produces old results -- the
500 * on-card read cache gets mixed up and doesn't notice that the
501 * framebuffer has been updated.
503 * Note that we should probably be reading some otherwise unused
504 * region of VRAM, otherwise we might get incorrect results when
505 * reading pixels from the top left of the screen.
507 * I found this problem on an R420 with glean's texCube test.
508 * Note that the R200 span code also *writes* the first pixel in the
509 * framebuffer, but I've found this to be unnecessary.
510 * -- Nicolai Hähnle, June 2008
512 if (!(bo
->domains
& RADEON_GEM_DOMAIN_GTT
)) {
514 volatile int *buf
= (int*)boml
->screen
->driScreen
->pFB
;
520 static int bo_unmap(struct radeon_bo
*bo
)
522 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
524 if (--bo_legacy
->map_count
> 0) {
531 static struct radeon_bo_funcs bo_legacy_funcs
= {
539 static int bo_vram_validate(struct radeon_bo
*bo
,
543 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bo
->bom
;
544 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
546 int retry_count
= 0, pending_retry
= 0;
548 if (!bo_legacy
->tobj
) {
549 bo_legacy
->tobj
= CALLOC(sizeof(struct bo_legacy_texture_object
));
550 bo_legacy
->tobj
->parent
= bo_legacy
;
551 make_empty_list(&bo_legacy
->tobj
->base
);
552 bo_legacy
->tobj
->base
.totalSize
= bo
->size
;
554 r
= driAllocateTexture(&boml
->texture_heap
, 1,
555 &bo_legacy
->tobj
->base
);
558 while(boml
->cpendings
&& pending_retry
++ < 10000) {
559 legacy_track_pending(boml
, 0);
561 if (retry_count
> 2) {
562 free(bo_legacy
->tobj
);
563 bo_legacy
->tobj
= NULL
;
564 fprintf(stderr
, "Ouch! vram_validate failed %d\n", r
);
570 bo_legacy
->offset
= boml
->texture_offset
+
571 bo_legacy
->tobj
->base
.memBlock
->ofs
;
572 bo_legacy
->dirty
= 1;
575 assert(bo_legacy
->tobj
->base
.memBlock
);
578 driUpdateTextureLRU(&bo_legacy
->tobj
->base
);
580 if (bo_legacy
->dirty
|| bo_legacy
->tobj
->base
.dirty_images
[0]) {
581 /* Copy to VRAM using a blit.
582 * All memory is 4K aligned. We're using 1024 pixels wide blits.
584 drm_radeon_texture_t tex
;
585 drm_radeon_tex_image_t tmp
;
588 tex
.offset
= bo_legacy
->offset
;
590 assert(!(tex
.offset
& 1023));
594 if (bo
->size
< 4096) {
595 tmp
.width
= (bo
->size
+ 3) / 4;
599 tmp
.height
= (bo
->size
+ 4095) / 4096;
601 tmp
.data
= bo_legacy
->ptr
;
602 tex
.format
= RADEON_TXFORMAT_ARGB8888
;
603 tex
.width
= tmp
.width
;
604 tex
.height
= tmp
.height
;
605 tex
.pitch
= MAX2(tmp
.width
/ 16, 1);
607 ret
= drmCommandWriteRead(bo
->bom
->fd
,
610 sizeof(drm_radeon_texture_t
));
612 if (RADEON_DEBUG
& DEBUG_IOCTL
)
613 fprintf(stderr
, "DRM_RADEON_TEXTURE: again!\n");
616 } while (ret
== -EAGAIN
);
617 bo_legacy
->dirty
= 0;
618 bo_legacy
->tobj
->base
.dirty_images
[0] = 0;
624 * radeon_bo_legacy_validate -
627 * -EINVAL - mapped buffer can't be validated
628 * -EAGAIN - restart validation we've kicked all the buffers out
630 int radeon_bo_legacy_validate(struct radeon_bo
*bo
,
634 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bo
->bom
;
635 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
639 if (bo_legacy
->map_count
) {
640 fprintf(stderr
, "bo(%p, %d) is mapped (%d) can't valide it.\n",
641 bo
, bo
->size
, bo_legacy
->map_count
);
644 if (bo_legacy
->static_bo
|| bo_legacy
->validated
) {
645 *soffset
= bo_legacy
->offset
;
646 *eoffset
= bo_legacy
->offset
+ bo
->size
;
649 if (!(bo
->domains
& RADEON_GEM_DOMAIN_GTT
)) {
651 r
= bo_vram_validate(bo
, soffset
, eoffset
);
653 legacy_track_pending(boml
, 0);
654 legacy_kick_all_buffers(boml
);
657 fprintf(stderr
,"legacy bo: failed to get relocations into aperture\n");
664 *soffset
= bo_legacy
->offset
;
665 *eoffset
= bo_legacy
->offset
+ bo
->size
;
666 bo_legacy
->validated
= 1;
670 void radeon_bo_legacy_pending(struct radeon_bo
*bo
, uint32_t pending
)
672 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bo
->bom
;
673 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
675 bo_legacy
->pending
= pending
;
676 bo_legacy
->is_pending
++;
677 /* add to pending list */
679 if (bo_legacy
->is_pending
> 1) {
682 bo_legacy
->pprev
= boml
->pending_bos
.pprev
;
683 bo_legacy
->pnext
= NULL
;
684 bo_legacy
->pprev
->pnext
= bo_legacy
;
685 boml
->pending_bos
.pprev
= bo_legacy
;
689 void radeon_bo_manager_legacy_dtor(struct radeon_bo_manager
*bom
)
691 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bom
;
692 struct bo_legacy
*bo_legacy
;
697 bo_legacy
= boml
->bos
.next
;
699 struct bo_legacy
*next
;
701 next
= bo_legacy
->next
;
705 driDestroyTextureHeap(boml
->texture_heap
);
706 free(boml
->free_handles
);
710 static struct bo_legacy
*radeon_legacy_bo_alloc_static(struct bo_manager_legacy
*bom
,
711 int size
, uint32_t offset
)
713 struct bo_legacy
*bo
;
715 bo
= bo_allocate(bom
, size
, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
719 bo
->offset
= offset
+ bom
->fb_location
;
720 bo
->base
.handle
= bo
->offset
;
721 bo
->ptr
= bom
->screen
->driScreen
->pFB
+ offset
;
722 if (bo
->base
.handle
> bom
->nhandle
) {
723 bom
->nhandle
= bo
->base
.handle
+ 1;
725 radeon_bo_ref(&(bo
->base
));
729 struct radeon_bo_manager
*radeon_bo_manager_legacy_ctor(struct radeon_screen
*scrn
)
731 struct bo_manager_legacy
*bom
;
732 struct bo_legacy
*bo
;
735 bom
= (struct bo_manager_legacy
*)
736 calloc(1, sizeof(struct bo_manager_legacy
));
741 make_empty_list(&bom
->texture_swapped
);
743 bom
->texture_heap
= driCreateTextureHeap(0,
747 RADEON_NR_TEX_REGIONS
,
748 (drmTextureRegionPtr
)scrn
->sarea
->tex_list
[0],
749 &scrn
->sarea
->tex_age
[0],
750 &bom
->texture_swapped
,
751 sizeof(struct bo_legacy_texture_object
),
752 &bo_legacy_tobj_destroy
);
753 bom
->texture_offset
= scrn
->texOffset
[0];
755 bom
->base
.funcs
= &bo_legacy_funcs
;
756 bom
->base
.fd
= scrn
->driScreen
->fd
;
757 bom
->bos
.next
= NULL
;
758 bom
->bos
.prev
= NULL
;
759 bom
->pending_bos
.pprev
= &bom
->pending_bos
;
760 bom
->pending_bos
.pnext
= NULL
;
762 bom
->fb_location
= scrn
->fbLocation
;
764 bom
->cfree_handles
= 0;
765 bom
->nfree_handles
= 0x400;
766 bom
->free_handles
= (uint32_t*)malloc(bom
->nfree_handles
* 4);
767 if (bom
->free_handles
== NULL
) {
768 radeon_bo_manager_legacy_dtor((struct radeon_bo_manager
*)bom
);
772 /* biggest framebuffer size */
776 bo
= radeon_legacy_bo_alloc_static(bom
, size
, bom
->screen
->frontOffset
);
778 radeon_bo_manager_legacy_dtor((struct radeon_bo_manager
*)bom
);
781 if (scrn
->sarea
->tiling_enabled
) {
782 bo
->base
.flags
= RADEON_BO_FLAGS_MACRO_TILE
;
786 bo
= radeon_legacy_bo_alloc_static(bom
, size
, bom
->screen
->backOffset
);
788 radeon_bo_manager_legacy_dtor((struct radeon_bo_manager
*)bom
);
791 if (scrn
->sarea
->tiling_enabled
) {
792 bo
->base
.flags
= RADEON_BO_FLAGS_MACRO_TILE
;
796 bo
= radeon_legacy_bo_alloc_static(bom
, size
, bom
->screen
->depthOffset
);
798 radeon_bo_manager_legacy_dtor((struct radeon_bo_manager
*)bom
);
802 if (scrn
->sarea
->tiling_enabled
) {
803 bo
->base
.flags
|= RADEON_BO_FLAGS_MACRO_TILE
;
804 bo
->base
.flags
|= RADEON_BO_FLAGS_MICRO_TILE
;
806 return (struct radeon_bo_manager
*)bom
;
809 void radeon_bo_legacy_texture_age(struct radeon_bo_manager
*bom
)
811 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bom
;
812 DRI_AGE_TEXTURES(boml
->texture_heap
);
815 unsigned radeon_bo_legacy_relocs_size(struct radeon_bo
*bo
)
817 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
819 if (bo_legacy
->static_bo
|| (bo
->domains
& RADEON_GEM_DOMAIN_GTT
)) {
825 int radeon_legacy_bo_is_static(struct radeon_bo
*bo
)
827 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
828 return bo_legacy
->static_bo
;