2 * Copyright © 2008 Nicolai Haehnle
3 * Copyright © 2008 Dave Airlie
4 * Copyright © 2008 Jérôme Glisse
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
29 * Aapo Tahkola <aet@rasterburn.org>
30 * Nicolai Haehnle <prefect_@gmx.net>
32 * Jérôme Glisse <glisse@freedesktop.org>
42 #include <sys/ioctl.h>
45 #include "main/simple_list.h"
48 #include "radeon_drm.h"
49 #include "radeon_common.h"
50 #include "radeon_bocs_wrapper.h"
51 #include "radeon_macros.h"
53 /* no seriously texmem.c is this screwed up */
54 struct bo_legacy_texture_object
{
55 driTextureObject base
;
56 struct bo_legacy
*parent
;
60 struct radeon_bo base
;
66 struct bo_legacy_texture_object
*tobj
;
70 struct bo_legacy
*next
, *prev
;
71 struct bo_legacy
*pnext
, *pprev
;
74 struct bo_manager_legacy
{
75 struct radeon_bo_manager base
;
77 unsigned nfree_handles
;
78 unsigned cfree_handles
;
81 struct bo_legacy pending_bos
;
83 uint32_t texture_offset
;
84 unsigned dma_alloc_size
;
85 uint32_t dma_buf_count
;
87 driTextureObject texture_swapped
;
88 driTexHeap
*texture_heap
;
89 struct radeon_screen
*screen
;
90 unsigned *free_handles
;
93 static void bo_legacy_tobj_destroy(void *data
, driTextureObject
*t
)
95 struct bo_legacy_texture_object
*tobj
= (struct bo_legacy_texture_object
*)t
;
98 tobj
->parent
->tobj
= NULL
;
99 tobj
->parent
->validated
= 0;
103 static void inline clean_handles(struct bo_manager_legacy
*bom
)
105 while (bom
->cfree_handles
> 0 &&
106 !bom
->free_handles
[bom
->cfree_handles
- 1])
107 bom
->cfree_handles
--;
110 static int legacy_new_handle(struct bo_manager_legacy
*bom
, uint32_t *handle
)
115 if (bom
->nhandle
== 0xFFFFFFFF) {
118 if (bom
->cfree_handles
> 0) {
119 tmp
= bom
->free_handles
[--bom
->cfree_handles
];
122 bom
->cfree_handles
= 0;
123 tmp
= bom
->nhandle
++;
130 static int legacy_free_handle(struct bo_manager_legacy
*bom
, uint32_t handle
)
137 if (handle
== (bom
->nhandle
- 1)) {
141 for (i
= bom
->cfree_handles
- 1; i
>= 0; i
--) {
142 if (bom
->free_handles
[i
] == (bom
->nhandle
- 1)) {
144 bom
->free_handles
[i
] = 0;
150 if (bom
->cfree_handles
< bom
->nfree_handles
) {
151 bom
->free_handles
[bom
->cfree_handles
++] = handle
;
154 bom
->nfree_handles
+= 0x100;
155 handles
= (uint32_t*)realloc(bom
->free_handles
, bom
->nfree_handles
* 4);
156 if (handles
== NULL
) {
157 bom
->nfree_handles
-= 0x100;
160 bom
->free_handles
= handles
;
161 bom
->free_handles
[bom
->cfree_handles
++] = handle
;
165 static void legacy_get_current_age(struct bo_manager_legacy
*boml
)
167 drm_radeon_getparam_t gp
;
168 unsigned char *RADEONMMIO
= NULL
;
171 if ( IS_R300_CLASS(boml
->screen
)
172 || IS_R600_CLASS(boml
->screen
) )
174 gp
.param
= RADEON_PARAM_LAST_CLEAR
;
175 gp
.value
= (int *)&boml
->current_age
;
176 r
= drmCommandWriteRead(boml
->base
.fd
, DRM_RADEON_GETPARAM
,
179 fprintf(stderr
, "%s: drmRadeonGetParam: %d\n", __FUNCTION__
, r
);
184 RADEONMMIO
= boml
->screen
->mmio
.map
;
185 boml
->current_age
= boml
->screen
->scratch
[3];
186 boml
->current_age
= INREG(RADEON_GUI_SCRATCH_REG3
);
190 static int legacy_is_pending(struct radeon_bo
*bo
)
192 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bo
->bom
;
193 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
195 if (bo_legacy
->is_pending
<= 0) {
196 bo_legacy
->is_pending
= 0;
199 if (boml
->current_age
>= bo_legacy
->pending
) {
200 if (boml
->pending_bos
.pprev
== bo_legacy
) {
201 boml
->pending_bos
.pprev
= bo_legacy
->pprev
;
203 bo_legacy
->pprev
->pnext
= bo_legacy
->pnext
;
204 if (bo_legacy
->pnext
) {
205 bo_legacy
->pnext
->pprev
= bo_legacy
->pprev
;
207 assert(bo_legacy
->is_pending
<= bo
->cref
);
208 while (bo_legacy
->is_pending
--) {
209 bo
= radeon_bo_unref(bo
);
214 bo_legacy
->is_pending
= 0;
221 static int legacy_wait_pending(struct radeon_bo
*bo
)
223 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bo
->bom
;
224 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
226 if (!bo_legacy
->is_pending
) {
229 /* FIXME: lockup and userspace busy looping that's all the folks */
230 legacy_get_current_age(boml
);
231 while (legacy_is_pending(bo
)) {
233 legacy_get_current_age(boml
);
238 void legacy_track_pending(struct radeon_bo_manager
*bom
, int debug
)
240 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*) bom
;
241 struct bo_legacy
*bo_legacy
;
242 struct bo_legacy
*next
;
244 legacy_get_current_age(boml
);
245 bo_legacy
= boml
->pending_bos
.pnext
;
248 fprintf(stderr
,"pending %p %d %d %d\n", bo_legacy
, bo_legacy
->base
.size
,
249 boml
->current_age
, bo_legacy
->pending
);
250 next
= bo_legacy
->pnext
;
251 if (legacy_is_pending(&(bo_legacy
->base
))) {
257 static int legacy_wait_any_pending(struct bo_manager_legacy
*boml
)
259 struct bo_legacy
*bo_legacy
;
261 legacy_get_current_age(boml
);
262 bo_legacy
= boml
->pending_bos
.pnext
;
265 legacy_wait_pending(&bo_legacy
->base
);
269 static void legacy_kick_all_buffers(struct bo_manager_legacy
*boml
)
271 struct bo_legacy
*legacy
;
273 legacy
= boml
->bos
.next
;
274 while (legacy
!= &boml
->bos
) {
276 if (legacy
->validated
) {
277 driDestroyTextureObject(&legacy
->tobj
->base
);
279 legacy
->validated
= 0;
282 legacy
= legacy
->next
;
286 static struct bo_legacy
*bo_allocate(struct bo_manager_legacy
*boml
,
292 struct bo_legacy
*bo_legacy
;
296 pgsize
= getpagesize() - 1;
298 size
= (size
+ pgsize
) & ~pgsize
;
300 bo_legacy
= (struct bo_legacy
*)calloc(1, sizeof(struct bo_legacy
));
301 if (bo_legacy
== NULL
) {
304 bo_legacy
->base
.bom
= (struct radeon_bo_manager
*)boml
;
305 bo_legacy
->base
.handle
= 0;
306 bo_legacy
->base
.size
= size
;
307 bo_legacy
->base
.alignment
= alignment
;
308 bo_legacy
->base
.domains
= domains
;
309 bo_legacy
->base
.flags
= flags
;
310 bo_legacy
->base
.ptr
= NULL
;
311 bo_legacy
->map_count
= 0;
312 bo_legacy
->next
= NULL
;
313 bo_legacy
->prev
= NULL
;
314 bo_legacy
->pnext
= NULL
;
315 bo_legacy
->pprev
= NULL
;
316 bo_legacy
->next
= boml
->bos
.next
;
317 bo_legacy
->prev
= &boml
->bos
;
318 boml
->bos
.next
= bo_legacy
;
319 if (bo_legacy
->next
) {
320 bo_legacy
->next
->prev
= bo_legacy
;
326 static int bo_dma_alloc(struct radeon_bo
*bo
)
328 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bo
->bom
;
329 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
330 drm_radeon_mem_alloc_t alloc
;
335 /* align size on 4Kb */
336 size
= (((4 * 1024) - 1) + bo
->size
) & ~((4 * 1024) - 1);
337 alloc
.region
= RADEON_MEM_REGION_GART
;
338 alloc
.alignment
= bo_legacy
->base
.alignment
;
340 alloc
.region_offset
= &base_offset
;
341 r
= drmCommandWriteRead(bo
->bom
->fd
,
346 /* ptr is set to NULL if dma allocation failed */
347 bo_legacy
->ptr
= NULL
;
350 bo_legacy
->ptr
= boml
->screen
->gartTextures
.map
+ base_offset
;
351 bo_legacy
->offset
= boml
->screen
->gart_texture_offset
+ base_offset
;
353 boml
->dma_alloc_size
+= size
;
354 boml
->dma_buf_count
++;
358 static int bo_dma_free(struct radeon_bo
*bo
)
360 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bo
->bom
;
361 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
362 drm_radeon_mem_free_t memfree
;
365 if (bo_legacy
->ptr
== NULL
) {
366 /* ptr is set to NULL if dma allocation failed */
369 legacy_get_current_age(boml
);
370 memfree
.region
= RADEON_MEM_REGION_GART
;
371 memfree
.region_offset
= bo_legacy
->offset
;
372 memfree
.region_offset
-= boml
->screen
->gart_texture_offset
;
373 r
= drmCommandWrite(boml
->base
.fd
,
378 fprintf(stderr
, "Failed to free bo[%p] at %08x\n",
379 &bo_legacy
->base
, memfree
.region_offset
);
380 fprintf(stderr
, "ret = %s\n", strerror(-r
));
383 boml
->dma_alloc_size
-= bo_legacy
->base
.size
;
384 boml
->dma_buf_count
--;
388 static void bo_free(struct bo_legacy
*bo_legacy
)
390 struct bo_manager_legacy
*boml
;
392 if (bo_legacy
== NULL
) {
395 boml
= (struct bo_manager_legacy
*)bo_legacy
->base
.bom
;
396 bo_legacy
->prev
->next
= bo_legacy
->next
;
397 if (bo_legacy
->next
) {
398 bo_legacy
->next
->prev
= bo_legacy
->prev
;
400 if (!bo_legacy
->static_bo
) {
401 legacy_free_handle(boml
, bo_legacy
->base
.handle
);
402 if (bo_legacy
->base
.domains
& RADEON_GEM_DOMAIN_GTT
) {
404 bo_dma_free(&bo_legacy
->base
);
406 driDestroyTextureObject(&bo_legacy
->tobj
->base
);
407 bo_legacy
->tobj
= NULL
;
408 /* free backing store */
409 free(bo_legacy
->ptr
);
412 memset(bo_legacy
, 0 , sizeof(struct bo_legacy
));
416 static struct radeon_bo
*bo_open(struct radeon_bo_manager
*bom
,
423 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bom
;
424 struct bo_legacy
*bo_legacy
;
428 bo_legacy
= boml
->bos
.next
;
430 if (bo_legacy
->base
.handle
== handle
) {
431 radeon_bo_ref(&(bo_legacy
->base
));
432 return (struct radeon_bo
*)bo_legacy
;
434 bo_legacy
= bo_legacy
->next
;
438 bo_legacy
= bo_allocate(boml
, size
, alignment
, domains
, flags
);
439 bo_legacy
->static_bo
= 0;
440 r
= legacy_new_handle(boml
, &bo_legacy
->base
.handle
);
445 if (bo_legacy
->base
.domains
& RADEON_GEM_DOMAIN_GTT
)
448 legacy_track_pending(&boml
->base
, 0);
451 r
= bo_dma_alloc(&(bo_legacy
->base
));
454 if (legacy_wait_any_pending(boml
) == -1)
465 bo_legacy
->ptr
= malloc(bo_legacy
->base
.size
);
466 if (bo_legacy
->ptr
== NULL
) {
471 radeon_bo_ref(&(bo_legacy
->base
));
473 return (struct radeon_bo
*)bo_legacy
;
476 static void bo_ref(struct radeon_bo
*bo
)
480 static struct radeon_bo
*bo_unref(struct radeon_bo
*bo
)
482 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
485 bo_legacy
->prev
->next
= bo_legacy
->next
;
486 if (bo_legacy
->next
) {
487 bo_legacy
->next
->prev
= bo_legacy
->prev
;
489 if (!bo_legacy
->is_pending
) {
497 static int bo_map(struct radeon_bo
*bo
, int write
)
499 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bo
->bom
;
500 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
502 legacy_wait_pending(bo
);
503 bo_legacy
->validated
= 0;
504 bo_legacy
->dirty
= 1;
505 bo_legacy
->map_count
++;
506 bo
->ptr
= bo_legacy
->ptr
;
507 /* Read the first pixel in the frame buffer. This should
508 * be a noop, right? In fact without this conform fails as reading
509 * from the framebuffer sometimes produces old results -- the
510 * on-card read cache gets mixed up and doesn't notice that the
511 * framebuffer has been updated.
513 * Note that we should probably be reading some otherwise unused
514 * region of VRAM, otherwise we might get incorrect results when
515 * reading pixels from the top left of the screen.
517 * I found this problem on an R420 with glean's texCube test.
518 * Note that the R200 span code also *writes* the first pixel in the
519 * framebuffer, but I've found this to be unnecessary.
520 * -- Nicolai Hähnle, June 2008
522 if (!(bo
->domains
& RADEON_GEM_DOMAIN_GTT
)) {
524 volatile int *buf
= (int*)boml
->screen
->driScreen
->pFB
;
531 static int bo_unmap(struct radeon_bo
*bo
)
533 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
535 if (--bo_legacy
->map_count
> 0)
545 static int bo_is_busy(struct radeon_bo
*bo
, uint32_t *domain
)
548 if (bo
->domains
& RADEON_GEM_DOMAIN_GTT
)
549 *domain
= RADEON_GEM_DOMAIN_GTT
;
551 *domain
= RADEON_GEM_DOMAIN_CPU
;
552 if (legacy_is_pending(bo
))
558 static int bo_is_static(struct radeon_bo
*bo
)
560 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
561 return bo_legacy
->static_bo
;
564 static struct radeon_bo_funcs bo_legacy_funcs
= {
577 static int bo_vram_validate(struct radeon_bo
*bo
,
581 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bo
->bom
;
582 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
584 int retry_count
= 0, pending_retry
= 0;
586 if (!bo_legacy
->tobj
) {
587 bo_legacy
->tobj
= CALLOC(sizeof(struct bo_legacy_texture_object
));
588 bo_legacy
->tobj
->parent
= bo_legacy
;
589 make_empty_list(&bo_legacy
->tobj
->base
);
590 bo_legacy
->tobj
->base
.totalSize
= bo
->size
;
592 r
= driAllocateTexture(&boml
->texture_heap
, 1,
593 &bo_legacy
->tobj
->base
);
596 while(boml
->cpendings
&& pending_retry
++ < 10000) {
597 legacy_track_pending(&boml
->base
, 0);
599 if (retry_count
> 2) {
600 free(bo_legacy
->tobj
);
601 bo_legacy
->tobj
= NULL
;
602 fprintf(stderr
, "Ouch! vram_validate failed %d\n", r
);
608 bo_legacy
->offset
= boml
->texture_offset
+
609 bo_legacy
->tobj
->base
.memBlock
->ofs
;
610 bo_legacy
->dirty
= 1;
613 assert(bo_legacy
->tobj
->base
.memBlock
);
616 driUpdateTextureLRU(&bo_legacy
->tobj
->base
);
618 if (bo_legacy
->dirty
|| bo_legacy
->tobj
->base
.dirty_images
[0]) {
619 if (IS_R600_CLASS(boml
->screen
)) {
620 drm_radeon_texture_t tex
;
621 drm_radeon_tex_image_t tmp
;
624 tex
.offset
= bo_legacy
->offset
;
626 assert(!(tex
.offset
& 1023));
630 tmp
.width
= bo
->size
;
632 tmp
.data
= bo_legacy
->ptr
;
633 tex
.format
= RADEON_TXFORMAT_ARGB8888
;
634 tex
.width
= tmp
.width
;
635 tex
.height
= tmp
.height
;
636 tex
.pitch
= bo
->size
;
638 ret
= drmCommandWriteRead(bo
->bom
->fd
,
641 sizeof(drm_radeon_texture_t
));
643 if (RADEON_DEBUG
& RADEON_IOCTL
)
644 fprintf(stderr
, "DRM_RADEON_TEXTURE: again!\n");
647 } while (ret
== -EAGAIN
);
649 /* Copy to VRAM using a blit.
650 * All memory is 4K aligned. We're using 1024 pixels wide blits.
652 drm_radeon_texture_t tex
;
653 drm_radeon_tex_image_t tmp
;
656 tex
.offset
= bo_legacy
->offset
;
658 assert(!(tex
.offset
& 1023));
662 if (bo
->size
< 4096) {
663 tmp
.width
= (bo
->size
+ 3) / 4;
667 tmp
.height
= (bo
->size
+ 4095) / 4096;
669 tmp
.data
= bo_legacy
->ptr
;
670 tex
.format
= RADEON_TXFORMAT_ARGB8888
;
671 tex
.width
= tmp
.width
;
672 tex
.height
= tmp
.height
;
673 tex
.pitch
= MAX2(tmp
.width
/ 16, 1);
675 ret
= drmCommandWriteRead(bo
->bom
->fd
,
678 sizeof(drm_radeon_texture_t
));
680 if (RADEON_DEBUG
& RADEON_IOCTL
)
681 fprintf(stderr
, "DRM_RADEON_TEXTURE: again!\n");
684 } while (ret
== -EAGAIN
);
686 bo_legacy
->dirty
= 0;
687 bo_legacy
->tobj
->base
.dirty_images
[0] = 0;
693 * radeon_bo_legacy_validate -
696 * -EINVAL - mapped buffer can't be validated
697 * -EAGAIN - restart validation we've kicked all the buffers out
699 int radeon_bo_legacy_validate(struct radeon_bo
*bo
,
703 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bo
->bom
;
704 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
708 if (bo_legacy
->map_count
) {
709 fprintf(stderr
, "bo(%p, %d) is mapped (%d) can't valide it.\n",
710 bo
, bo
->size
, bo_legacy
->map_count
);
713 if (bo_legacy
->static_bo
|| bo_legacy
->validated
) {
714 *soffset
= bo_legacy
->offset
;
715 *eoffset
= bo_legacy
->offset
+ bo
->size
;
719 if (!(bo
->domains
& RADEON_GEM_DOMAIN_GTT
)) {
721 r
= bo_vram_validate(bo
, soffset
, eoffset
);
723 legacy_track_pending(&boml
->base
, 0);
724 legacy_kick_all_buffers(boml
);
727 fprintf(stderr
,"legacy bo: failed to get relocations into aperture\n");
734 *soffset
= bo_legacy
->offset
;
735 *eoffset
= bo_legacy
->offset
+ bo
->size
;
736 bo_legacy
->validated
= 1;
741 void radeon_bo_legacy_pending(struct radeon_bo
*bo
, uint32_t pending
)
743 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bo
->bom
;
744 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
746 bo_legacy
->pending
= pending
;
747 bo_legacy
->is_pending
++;
748 /* add to pending list */
750 if (bo_legacy
->is_pending
> 1) {
753 bo_legacy
->pprev
= boml
->pending_bos
.pprev
;
754 bo_legacy
->pnext
= NULL
;
755 bo_legacy
->pprev
->pnext
= bo_legacy
;
756 boml
->pending_bos
.pprev
= bo_legacy
;
760 void radeon_bo_manager_legacy_dtor(struct radeon_bo_manager
*bom
)
762 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bom
;
763 struct bo_legacy
*bo_legacy
;
768 bo_legacy
= boml
->bos
.next
;
770 struct bo_legacy
*next
;
772 next
= bo_legacy
->next
;
776 driDestroyTextureHeap(boml
->texture_heap
);
777 free(boml
->free_handles
);
781 static struct bo_legacy
*radeon_legacy_bo_alloc_static(struct bo_manager_legacy
*bom
,
785 struct bo_legacy
*bo
;
787 bo
= bo_allocate(bom
, size
, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
792 bo
->offset
= offset
+ bom
->fb_location
;
793 bo
->base
.handle
= bo
->offset
;
794 bo
->ptr
= bom
->screen
->driScreen
->pFB
+ offset
;
795 if (bo
->base
.handle
> bom
->nhandle
) {
796 bom
->nhandle
= bo
->base
.handle
+ 1;
798 radeon_bo_ref(&(bo
->base
));
802 struct radeon_bo_manager
*radeon_bo_manager_legacy_ctor(struct radeon_screen
*scrn
)
804 struct bo_manager_legacy
*bom
;
805 struct bo_legacy
*bo
;
808 bom
= (struct bo_manager_legacy
*)
809 calloc(1, sizeof(struct bo_manager_legacy
));
814 make_empty_list(&bom
->texture_swapped
);
816 bom
->texture_heap
= driCreateTextureHeap(0,
820 RADEON_NR_TEX_REGIONS
,
821 (drmTextureRegionPtr
)scrn
->sarea
->tex_list
[0],
822 &scrn
->sarea
->tex_age
[0],
823 &bom
->texture_swapped
,
824 sizeof(struct bo_legacy_texture_object
),
825 &bo_legacy_tobj_destroy
);
826 bom
->texture_offset
= scrn
->texOffset
[0];
828 bom
->base
.funcs
= &bo_legacy_funcs
;
829 bom
->base
.fd
= scrn
->driScreen
->fd
;
830 bom
->bos
.next
= NULL
;
831 bom
->bos
.prev
= NULL
;
832 bom
->pending_bos
.pprev
= &bom
->pending_bos
;
833 bom
->pending_bos
.pnext
= NULL
;
835 bom
->fb_location
= scrn
->fbLocation
;
837 bom
->cfree_handles
= 0;
838 bom
->nfree_handles
= 0x400;
839 bom
->free_handles
= (uint32_t*)malloc(bom
->nfree_handles
* 4);
840 if (bom
->free_handles
== NULL
) {
841 radeon_bo_manager_legacy_dtor((struct radeon_bo_manager
*)bom
);
845 /* biggest framebuffer size */
849 bo
= radeon_legacy_bo_alloc_static(bom
, size
, bom
->screen
->frontOffset
);
852 radeon_bo_manager_legacy_dtor((struct radeon_bo_manager
*)bom
);
855 if (scrn
->sarea
->tiling_enabled
) {
856 bo
->base
.flags
= RADEON_BO_FLAGS_MACRO_TILE
;
860 bo
= radeon_legacy_bo_alloc_static(bom
, size
, bom
->screen
->backOffset
);
863 radeon_bo_manager_legacy_dtor((struct radeon_bo_manager
*)bom
);
866 if (scrn
->sarea
->tiling_enabled
) {
867 bo
->base
.flags
= RADEON_BO_FLAGS_MACRO_TILE
;
871 bo
= radeon_legacy_bo_alloc_static(bom
, size
, bom
->screen
->depthOffset
);
874 radeon_bo_manager_legacy_dtor((struct radeon_bo_manager
*)bom
);
878 if (scrn
->sarea
->tiling_enabled
) {
879 bo
->base
.flags
|= RADEON_BO_FLAGS_MACRO_TILE
;
880 bo
->base
.flags
|= RADEON_BO_FLAGS_MICRO_TILE
;
882 return (struct radeon_bo_manager
*)bom
;
885 void radeon_bo_legacy_texture_age(struct radeon_bo_manager
*bom
)
887 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bom
;
888 DRI_AGE_TEXTURES(boml
->texture_heap
);
891 unsigned radeon_bo_legacy_relocs_size(struct radeon_bo
*bo
)
893 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
895 if (bo_legacy
->static_bo
|| (bo
->domains
& RADEON_GEM_DOMAIN_GTT
)) {
902 * Fake up a bo for things like texture image_override.
903 * bo->offset already includes fb_location
905 struct radeon_bo
*radeon_legacy_bo_alloc_fake(struct radeon_bo_manager
*bom
,
909 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bom
;
910 struct bo_legacy
*bo
;
912 bo
= bo_allocate(boml
, size
, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
918 bo
->base
.handle
= bo
->offset
;
919 bo
->ptr
= boml
->screen
->driScreen
->pFB
+ (offset
- boml
->fb_location
);
920 if (bo
->base
.handle
> boml
->nhandle
) {
921 boml
->nhandle
= bo
->base
.handle
+ 1;
923 radeon_bo_ref(&(bo
->base
));