2 * Copyright © 2008 Nicolai Haehnle
3 * Copyright © 2008 Dave Airlie
4 * Copyright © 2008 Jérôme Glisse
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
29 * Aapo Tahkola <aet@rasterburn.org>
30 * Nicolai Haehnle <prefect_@gmx.net>
32 * Jérôme Glisse <glisse@freedesktop.org>
41 #include <sys/ioctl.h>
44 #include "main/simple_list.h"
47 #include "radeon_drm.h"
48 #include "radeon_bo.h"
49 #include "radeon_bo_legacy.h"
50 #include "common_context.h"
53 struct radeon_bo base
;
54 driTextureObject tobj_base
;
60 int got_dri_texture_obj
;
63 driTextureObject dri_texture_obj
;
65 struct bo_legacy
*next
, *prev
;
66 struct bo_legacy
*pnext
, *pprev
;
69 struct bo_manager_legacy
{
70 struct radeon_bo_manager base
;
72 unsigned nfree_handles
;
73 unsigned cfree_handles
;
76 struct bo_legacy pending_bos
;
78 uint32_t texture_offset
;
79 unsigned dma_alloc_size
;
80 uint32_t dma_buf_count
;
82 driTextureObject texture_swapped
;
83 driTexHeap
*texture_heap
;
84 struct radeon_screen
*screen
;
85 unsigned *free_handles
;
88 static void bo_legacy_tobj_destroy(void *data
, driTextureObject
*t
)
90 struct bo_legacy
*bo_legacy
;
92 bo_legacy
= (struct bo_legacy
*)((char*)t
)-sizeof(struct radeon_bo
);
93 bo_legacy
->got_dri_texture_obj
= 0;
94 bo_legacy
->validated
= 0;
97 static void inline clean_handles(struct bo_manager_legacy
*bom
)
99 while (bom
->cfree_handles
> 0 &&
100 !bom
->free_handles
[bom
->cfree_handles
- 1])
101 bom
->cfree_handles
--;
104 static int legacy_new_handle(struct bo_manager_legacy
*bom
, uint32_t *handle
)
109 if (bom
->nhandle
== 0xFFFFFFFF) {
112 if (bom
->cfree_handles
> 0) {
113 tmp
= bom
->free_handles
[--bom
->cfree_handles
];
116 bom
->cfree_handles
= 0;
117 tmp
= bom
->nhandle
++;
124 static int legacy_free_handle(struct bo_manager_legacy
*bom
, uint32_t handle
)
131 if (handle
== (bom
->nhandle
- 1)) {
135 for (i
= bom
->cfree_handles
- 1; i
>= 0; i
--) {
136 if (bom
->free_handles
[i
] == (bom
->nhandle
- 1)) {
138 bom
->free_handles
[i
] = 0;
144 if (bom
->cfree_handles
< bom
->nfree_handles
) {
145 bom
->free_handles
[bom
->cfree_handles
++] = handle
;
148 bom
->nfree_handles
+= 0x100;
149 handles
= (uint32_t*)realloc(bom
->free_handles
, bom
->nfree_handles
* 4);
150 if (handles
== NULL
) {
151 bom
->nfree_handles
-= 0x100;
154 bom
->free_handles
= handles
;
155 bom
->free_handles
[bom
->cfree_handles
++] = handle
;
159 static void legacy_get_current_age(struct bo_manager_legacy
*boml
)
161 drm_radeon_getparam_t gp
;
164 if (IS_R300_CLASS(boml
->screen
)) {
165 gp
.param
= RADEON_PARAM_LAST_CLEAR
;
166 gp
.value
= (int *)&boml
->current_age
;
167 r
= drmCommandWriteRead(boml
->base
.fd
, DRM_RADEON_GETPARAM
,
170 fprintf(stderr
, "%s: drmRadeonGetParam: %d\n", __FUNCTION__
, r
);
174 boml
->current_age
= boml
->screen
->scratch
[3];
177 static int legacy_is_pending(struct radeon_bo
*bo
)
179 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bo
->bom
;
180 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
182 if (bo_legacy
->is_pending
<= 0) {
183 bo_legacy
->is_pending
= 0;
186 if (boml
->current_age
>= bo_legacy
->pending
) {
187 if (boml
->pending_bos
.pprev
== bo_legacy
) {
188 boml
->pending_bos
.pprev
= bo_legacy
->pprev
;
190 bo_legacy
->pprev
->pnext
= bo_legacy
->pnext
;
191 if (bo_legacy
->pnext
) {
192 bo_legacy
->pnext
->pprev
= bo_legacy
->pprev
;
194 assert(bo_legacy
->is_pending
<= bo
->cref
);
195 while (bo_legacy
->is_pending
--) {
196 bo
= radeon_bo_unref(bo
);
201 bo_legacy
->is_pending
= 0;
208 static int legacy_wait_pending(struct radeon_bo
*bo
)
210 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bo
->bom
;
211 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
213 if (!bo_legacy
->is_pending
) {
216 /* FIXME: lockup and userspace busy looping that's all the folks */
217 legacy_get_current_age(boml
);
218 while (legacy_is_pending(bo
)) {
220 legacy_get_current_age(boml
);
225 static void legacy_track_pending(struct bo_manager_legacy
*boml
, int debug
)
227 struct bo_legacy
*bo_legacy
;
228 struct bo_legacy
*next
;
230 legacy_get_current_age(boml
);
231 bo_legacy
= boml
->pending_bos
.pnext
;
234 fprintf(stderr
,"pending %p %d %d %d\n", bo_legacy
, bo_legacy
->base
.size
,
235 boml
->current_age
, bo_legacy
->pending
);
236 next
= bo_legacy
->pnext
;
237 if (legacy_is_pending(&(bo_legacy
->base
))) {
243 static int legacy_wait_any_pending(struct bo_manager_legacy
*boml
)
245 struct bo_legacy
*bo_legacy
;
246 struct bo_legacy
*next
;
248 legacy_get_current_age(boml
);
249 bo_legacy
= boml
->pending_bos
.pnext
;
252 legacy_wait_pending(&bo_legacy
->base
);
256 static struct bo_legacy
*bo_allocate(struct bo_manager_legacy
*boml
,
262 struct bo_legacy
*bo_legacy
;
263 uint32_t pgsize
= getpagesize() - 1;
265 size
= (size
+ pgsize
) & ~pgsize
;
267 bo_legacy
= (struct bo_legacy
*)calloc(1, sizeof(struct bo_legacy
));
268 if (bo_legacy
== NULL
) {
271 bo_legacy
->base
.bom
= (struct radeon_bo_manager
*)boml
;
272 bo_legacy
->base
.handle
= 0;
273 bo_legacy
->base
.size
= size
;
274 bo_legacy
->base
.alignment
= alignment
;
275 bo_legacy
->base
.domains
= domains
;
276 bo_legacy
->base
.flags
= flags
;
277 bo_legacy
->base
.ptr
= NULL
;
278 bo_legacy
->map_count
= 0;
279 bo_legacy
->next
= NULL
;
280 bo_legacy
->prev
= NULL
;
281 bo_legacy
->got_dri_texture_obj
= 0;
282 bo_legacy
->pnext
= NULL
;
283 bo_legacy
->pprev
= NULL
;
284 bo_legacy
->next
= boml
->bos
.next
;
285 bo_legacy
->prev
= &boml
->bos
;
286 boml
->bos
.next
= bo_legacy
;
287 if (bo_legacy
->next
) {
288 bo_legacy
->next
->prev
= bo_legacy
;
293 static int bo_dma_alloc(struct radeon_bo
*bo
)
295 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bo
->bom
;
296 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
297 drm_radeon_mem_alloc_t alloc
;
302 /* align size on 4Kb */
303 size
= (((4 * 1024) - 1) + bo
->size
) & ~((4 * 1024) - 1);
304 alloc
.region
= RADEON_MEM_REGION_GART
;
305 alloc
.alignment
= bo_legacy
->base
.alignment
;
307 alloc
.region_offset
= &base_offset
;
308 r
= drmCommandWriteRead(bo
->bom
->fd
,
313 /* ptr is set to NULL if dma allocation failed */
314 bo_legacy
->ptr
= NULL
;
317 bo_legacy
->ptr
= boml
->screen
->gartTextures
.map
+ base_offset
;
318 bo_legacy
->offset
= boml
->screen
->gart_texture_offset
+ base_offset
;
320 boml
->dma_alloc_size
+= size
;
321 boml
->dma_buf_count
++;
325 static int bo_dma_free(struct radeon_bo
*bo
)
327 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bo
->bom
;
328 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
329 drm_radeon_mem_free_t memfree
;
332 if (bo_legacy
->ptr
== NULL
) {
333 /* ptr is set to NULL if dma allocation failed */
336 legacy_get_current_age(boml
);
337 memfree
.region
= RADEON_MEM_REGION_GART
;
338 memfree
.region_offset
= bo_legacy
->offset
;
339 memfree
.region_offset
-= boml
->screen
->gart_texture_offset
;
340 r
= drmCommandWrite(boml
->base
.fd
,
345 fprintf(stderr
, "Failed to free bo[%p] at %08x\n",
346 &bo_legacy
->base
, memfree
.region_offset
);
347 fprintf(stderr
, "ret = %s\n", strerror(-r
));
350 boml
->dma_alloc_size
-= bo_legacy
->base
.size
;
351 boml
->dma_buf_count
--;
355 static void bo_free(struct bo_legacy
*bo_legacy
)
357 struct bo_manager_legacy
*boml
;
359 if (bo_legacy
== NULL
) {
362 boml
= (struct bo_manager_legacy
*)bo_legacy
->base
.bom
;
363 bo_legacy
->prev
->next
= bo_legacy
->next
;
364 if (bo_legacy
->next
) {
365 bo_legacy
->next
->prev
= bo_legacy
->prev
;
367 if (!bo_legacy
->static_bo
) {
368 legacy_free_handle(boml
, bo_legacy
->base
.handle
);
369 if (bo_legacy
->base
.domains
& RADEON_GEM_DOMAIN_GTT
) {
371 bo_dma_free(&bo_legacy
->base
);
373 /* free backing store */
374 free(bo_legacy
->ptr
);
377 memset(bo_legacy
, 0 , sizeof(struct bo_legacy
));
381 static struct radeon_bo
*bo_open(struct radeon_bo_manager
*bom
,
388 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bom
;
389 struct bo_legacy
*bo_legacy
;
393 bo_legacy
= boml
->bos
.next
;
395 if (bo_legacy
->base
.handle
== handle
) {
396 radeon_bo_ref(&(bo_legacy
->base
));
397 return (struct radeon_bo
*)bo_legacy
;
399 bo_legacy
= bo_legacy
->next
;
404 bo_legacy
= bo_allocate(boml
, size
, alignment
, domains
, flags
);
405 bo_legacy
->static_bo
= 0;
406 r
= legacy_new_handle(boml
, &bo_legacy
->base
.handle
);
411 if (bo_legacy
->base
.domains
& RADEON_GEM_DOMAIN_GTT
) {
413 legacy_track_pending(boml
, 0);
416 r
= bo_dma_alloc(&(bo_legacy
->base
));
418 if (legacy_wait_any_pending(boml
) == -1) {
426 bo_legacy
->ptr
= malloc(bo_legacy
->base
.size
);
427 if (bo_legacy
->ptr
== NULL
) {
432 radeon_bo_ref(&(bo_legacy
->base
));
433 return (struct radeon_bo
*)bo_legacy
;
436 static void bo_ref(struct radeon_bo
*bo
)
440 static struct radeon_bo
*bo_unref(struct radeon_bo
*bo
)
442 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
445 bo_legacy
->prev
->next
= bo_legacy
->next
;
446 if (bo_legacy
->next
) {
447 bo_legacy
->next
->prev
= bo_legacy
->prev
;
449 if (!bo_legacy
->is_pending
) {
457 static int bo_map(struct radeon_bo
*bo
, int write
)
459 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bo
->bom
;
460 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
462 legacy_wait_pending(bo
);
463 bo_legacy
->validated
= 0;
464 bo_legacy
->dirty
= 1;
465 bo_legacy
->map_count
++;
466 bo
->ptr
= bo_legacy
->ptr
;
467 /* Read the first pixel in the frame buffer. This should
468 * be a noop, right? In fact without this conform fails as reading
469 * from the framebuffer sometimes produces old results -- the
470 * on-card read cache gets mixed up and doesn't notice that the
471 * framebuffer has been updated.
473 * Note that we should probably be reading some otherwise unused
474 * region of VRAM, otherwise we might get incorrect results when
475 * reading pixels from the top left of the screen.
477 * I found this problem on an R420 with glean's texCube test.
478 * Note that the R200 span code also *writes* the first pixel in the
479 * framebuffer, but I've found this to be unnecessary.
480 * -- Nicolai Hähnle, June 2008
482 if (!(bo
->domains
& RADEON_GEM_DOMAIN_GTT
)) {
484 volatile int *buf
= (int*)boml
->screen
->driScreen
->pFB
;
490 static int bo_unmap(struct radeon_bo
*bo
)
492 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
494 if (--bo_legacy
->map_count
> 0) {
501 static struct radeon_bo_funcs bo_legacy_funcs
= {
509 static int bo_vram_validate(struct radeon_bo
*bo
,
513 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bo
->bom
;
514 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
517 if (!bo_legacy
->got_dri_texture_obj
) {
518 make_empty_list(&bo_legacy
->dri_texture_obj
);
519 bo_legacy
->dri_texture_obj
.totalSize
= bo
->size
;
520 r
= driAllocateTexture(&boml
->texture_heap
, 1,
521 &bo_legacy
->dri_texture_obj
);
523 uint8_t *segfault
=NULL
;
524 fprintf(stderr
, "Ouch! vram_validate failed %d\n", r
);
528 bo_legacy
->offset
= boml
->texture_offset
+
529 bo_legacy
->dri_texture_obj
.memBlock
->ofs
;
530 bo_legacy
->got_dri_texture_obj
= 1;
531 bo_legacy
->dirty
= 1;
533 if (bo_legacy
->dirty
) {
534 /* Copy to VRAM using a blit.
535 * All memory is 4K aligned. We're using 1024 pixels wide blits.
537 drm_radeon_texture_t tex
;
538 drm_radeon_tex_image_t tmp
;
541 tex
.offset
= bo_legacy
->offset
;
543 assert(!(tex
.offset
& 1023));
547 if (bo
->size
< 4096) {
548 tmp
.width
= (bo
->size
+ 3) / 4;
552 tmp
.height
= (bo
->size
+ 4095) / 4096;
554 tmp
.data
= bo_legacy
->ptr
;
555 tex
.format
= RADEON_TXFORMAT_ARGB8888
;
556 tex
.width
= tmp
.width
;
557 tex
.height
= tmp
.height
;
558 tex
.pitch
= MAX2(tmp
.width
/ 16, 1);
560 ret
= drmCommandWriteRead(bo
->bom
->fd
,
563 sizeof(drm_radeon_texture_t
));
565 if (RADEON_DEBUG
& DEBUG_IOCTL
)
566 fprintf(stderr
, "DRM_RADEON_TEXTURE: again!\n");
569 } while (ret
== -EAGAIN
);
570 bo_legacy
->dirty
= 0;
575 int radeon_bo_legacy_validate(struct radeon_bo
*bo
,
579 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
582 if (bo_legacy
->map_count
) {
583 fprintf(stderr
, "bo(%p, %d) is mapped (%d) can't valide it.\n",
584 bo
, bo
->size
, bo_legacy
->map_count
);
587 if (bo_legacy
->static_bo
|| bo_legacy
->validated
) {
588 *soffset
= bo_legacy
->offset
;
589 *eoffset
= bo_legacy
->offset
+ bo
->size
;
592 if (!(bo
->domains
& RADEON_GEM_DOMAIN_GTT
)) {
593 r
= bo_vram_validate(bo
, soffset
, eoffset
);
598 *soffset
= bo_legacy
->offset
;
599 *eoffset
= bo_legacy
->offset
+ bo
->size
;
600 bo_legacy
->validated
= 1;
604 void radeon_bo_legacy_pending(struct radeon_bo
*bo
, uint32_t pending
)
606 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bo
->bom
;
607 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
609 bo_legacy
->pending
= pending
;
610 bo_legacy
->is_pending
++;
611 /* add to pending list */
613 if (bo_legacy
->is_pending
> 1) {
616 bo_legacy
->pprev
= boml
->pending_bos
.pprev
;
617 bo_legacy
->pnext
= NULL
;
618 bo_legacy
->pprev
->pnext
= bo_legacy
;
619 boml
->pending_bos
.pprev
= bo_legacy
;
623 void radeon_bo_manager_legacy_dtor(struct radeon_bo_manager
*bom
)
625 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bom
;
626 struct bo_legacy
*bo_legacy
;
631 bo_legacy
= boml
->bos
.next
;
633 struct bo_legacy
*next
;
635 next
= bo_legacy
->next
;
639 free(boml
->free_handles
);
643 static struct bo_legacy
*radeon_legacy_bo_alloc_static(struct bo_manager_legacy
*bom
,
644 int size
, uint32_t offset
)
646 struct bo_legacy
*bo
;
648 bo
= bo_allocate(bom
, size
, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
652 bo
->offset
= offset
+ bom
->fb_location
;
653 bo
->base
.handle
= bo
->offset
;
654 bo
->ptr
= bom
->screen
->driScreen
->pFB
+ offset
;
655 if (bo
->base
.handle
> bom
->nhandle
) {
656 bom
->nhandle
= bo
->base
.handle
+ 1;
658 radeon_bo_ref(&(bo
->base
));
662 struct radeon_bo_manager
*radeon_bo_manager_legacy_ctor(struct radeon_screen
*scrn
)
664 struct bo_manager_legacy
*bom
;
665 struct bo_legacy
*bo
;
668 bom
= (struct bo_manager_legacy
*)
669 calloc(1, sizeof(struct bo_manager_legacy
));
674 bom
->texture_heap
= driCreateTextureHeap(0,
678 RADEON_NR_TEX_REGIONS
,
679 (drmTextureRegionPtr
)scrn
->sarea
->tex_list
[0],
680 &scrn
->sarea
->tex_age
[0],
681 &bom
->texture_swapped
,
682 sizeof(struct bo_legacy
),
683 &bo_legacy_tobj_destroy
);
684 bom
->texture_offset
= scrn
->texOffset
[0];
686 bom
->base
.funcs
= &bo_legacy_funcs
;
687 bom
->base
.fd
= scrn
->driScreen
->fd
;
688 bom
->bos
.next
= NULL
;
689 bom
->bos
.prev
= NULL
;
690 bom
->pending_bos
.pprev
= &bom
->pending_bos
;
691 bom
->pending_bos
.pnext
= NULL
;
693 bom
->fb_location
= scrn
->fbLocation
;
695 bom
->cfree_handles
= 0;
696 bom
->nfree_handles
= 0x400;
697 bom
->free_handles
= (uint32_t*)malloc(bom
->nfree_handles
* 4);
698 if (bom
->free_handles
== NULL
) {
699 radeon_bo_manager_legacy_dtor((struct radeon_bo_manager
*)bom
);
703 /* biggest framebuffer size */
707 bo
= radeon_legacy_bo_alloc_static(bom
, size
, bom
->screen
->frontOffset
);
709 radeon_bo_manager_legacy_dtor((struct radeon_bo_manager
*)bom
);
712 if (scrn
->sarea
->tiling_enabled
) {
713 bo
->base
.flags
= RADEON_BO_FLAGS_MACRO_TILE
;
717 bo
= radeon_legacy_bo_alloc_static(bom
, size
, bom
->screen
->backOffset
);
719 radeon_bo_manager_legacy_dtor((struct radeon_bo_manager
*)bom
);
722 if (scrn
->sarea
->tiling_enabled
) {
723 bo
->base
.flags
= RADEON_BO_FLAGS_MACRO_TILE
;
727 bo
= radeon_legacy_bo_alloc_static(bom
, size
, bom
->screen
->depthOffset
);
729 radeon_bo_manager_legacy_dtor((struct radeon_bo_manager
*)bom
);
733 if (scrn
->sarea
->tiling_enabled
) {
734 bo
->base
.flags
|= RADEON_BO_FLAGS_MACRO_TILE
;
735 bo
->base
.flags
|= RADEON_BO_FLAGS_MICRO_TILE
;
737 return (struct radeon_bo_manager
*)bom
;
740 void radeon_bo_legacy_texture_age(struct radeon_bo_manager
*bom
)
742 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bom
;
743 DRI_AGE_TEXTURES(boml
->texture_heap
);
746 unsigned radeon_bo_legacy_relocs_size(struct radeon_bo
*bo
)
748 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
750 if (bo_legacy
->static_bo
|| (bo
->domains
& RADEON_GEM_DOMAIN_GTT
)) {
756 int radeon_legacy_bo_is_static(struct radeon_bo
*bo
)
758 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
759 return bo_legacy
->static_bo
;