2 * Copyright © 2008 Nicolai Haehnle
3 * Copyright © 2008 Dave Airlie
4 * Copyright © 2008 Jérôme Glisse
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
29 * Aapo Tahkola <aet@rasterburn.org>
30 * Nicolai Haehnle <prefect_@gmx.net>
32 * Jérôme Glisse <glisse@freedesktop.org>
42 #include <sys/ioctl.h>
45 #include "main/simple_list.h"
48 #include "radeon_drm.h"
49 #include "radeon_common.h"
50 #include "radeon_bocs_wrapper.h"
51 #include "radeon_macros.h"
53 /* no seriously texmem.c is this screwed up */
54 struct bo_legacy_texture_object
{
55 driTextureObject base
;
56 struct bo_legacy
*parent
;
60 struct radeon_bo base
;
66 struct bo_legacy_texture_object
*tobj
;
70 struct bo_legacy
*next
, *prev
;
71 struct bo_legacy
*pnext
, *pprev
;
72 #ifdef RADEON_DEBUG_BO
74 #endif /* RADEON_DEBUG_BO */
77 struct bo_manager_legacy
{
78 struct radeon_bo_manager base
;
80 unsigned nfree_handles
;
81 unsigned cfree_handles
;
84 struct bo_legacy pending_bos
;
86 uint32_t texture_offset
;
87 unsigned dma_alloc_size
;
88 uint32_t dma_buf_count
;
90 driTextureObject texture_swapped
;
91 driTexHeap
*texture_heap
;
92 struct radeon_screen
*screen
;
93 unsigned *free_handles
;
96 static void bo_legacy_tobj_destroy(void *data
, driTextureObject
*t
)
98 struct bo_legacy_texture_object
*tobj
= (struct bo_legacy_texture_object
*)t
;
101 tobj
->parent
->tobj
= NULL
;
102 tobj
->parent
->validated
= 0;
106 static void inline clean_handles(struct bo_manager_legacy
*bom
)
108 while (bom
->cfree_handles
> 0 &&
109 !bom
->free_handles
[bom
->cfree_handles
- 1])
110 bom
->cfree_handles
--;
113 static int legacy_new_handle(struct bo_manager_legacy
*bom
, uint32_t *handle
)
118 if (bom
->nhandle
== 0xFFFFFFFF) {
121 if (bom
->cfree_handles
> 0) {
122 tmp
= bom
->free_handles
[--bom
->cfree_handles
];
125 bom
->cfree_handles
= 0;
126 tmp
= bom
->nhandle
++;
133 static int legacy_free_handle(struct bo_manager_legacy
*bom
, uint32_t handle
)
140 if (handle
== (bom
->nhandle
- 1)) {
144 for (i
= bom
->cfree_handles
- 1; i
>= 0; i
--) {
145 if (bom
->free_handles
[i
] == (bom
->nhandle
- 1)) {
147 bom
->free_handles
[i
] = 0;
153 if (bom
->cfree_handles
< bom
->nfree_handles
) {
154 bom
->free_handles
[bom
->cfree_handles
++] = handle
;
157 bom
->nfree_handles
+= 0x100;
158 handles
= (uint32_t*)realloc(bom
->free_handles
, bom
->nfree_handles
* 4);
159 if (handles
== NULL
) {
160 bom
->nfree_handles
-= 0x100;
163 bom
->free_handles
= handles
;
164 bom
->free_handles
[bom
->cfree_handles
++] = handle
;
168 static void legacy_get_current_age(struct bo_manager_legacy
*boml
)
170 drm_radeon_getparam_t gp
;
171 unsigned char *RADEONMMIO
= NULL
;
174 if (IS_R300_CLASS(boml
->screen
)) {
175 gp
.param
= RADEON_PARAM_LAST_CLEAR
;
176 gp
.value
= (int *)&boml
->current_age
;
177 r
= drmCommandWriteRead(boml
->base
.fd
, DRM_RADEON_GETPARAM
,
180 fprintf(stderr
, "%s: drmRadeonGetParam: %d\n", __FUNCTION__
, r
);
184 RADEONMMIO
= boml
->screen
->mmio
.map
;
185 boml
->current_age
= boml
->screen
->scratch
[3];
186 boml
->current_age
= INREG(RADEON_GUI_SCRATCH_REG3
);
190 static int legacy_is_pending(struct radeon_bo
*bo
)
192 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bo
->bom
;
193 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
195 if (bo_legacy
->is_pending
<= 0) {
196 bo_legacy
->is_pending
= 0;
199 if (boml
->current_age
>= bo_legacy
->pending
) {
200 if (boml
->pending_bos
.pprev
== bo_legacy
) {
201 boml
->pending_bos
.pprev
= bo_legacy
->pprev
;
203 bo_legacy
->pprev
->pnext
= bo_legacy
->pnext
;
204 if (bo_legacy
->pnext
) {
205 bo_legacy
->pnext
->pprev
= bo_legacy
->pprev
;
207 assert(bo_legacy
->is_pending
<= bo
->cref
);
208 while (bo_legacy
->is_pending
--) {
209 bo
= radeon_bo_unref(bo
);
214 bo_legacy
->is_pending
= 0;
221 static int legacy_wait_pending(struct radeon_bo
*bo
)
223 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bo
->bom
;
224 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
226 if (!bo_legacy
->is_pending
) {
229 /* FIXME: lockup and userspace busy looping that's all the folks */
230 legacy_get_current_age(boml
);
231 while (legacy_is_pending(bo
)) {
233 legacy_get_current_age(boml
);
238 static void legacy_track_pending(struct bo_manager_legacy
*boml
, int debug
)
240 struct bo_legacy
*bo_legacy
;
241 struct bo_legacy
*next
;
243 legacy_get_current_age(boml
);
244 bo_legacy
= boml
->pending_bos
.pnext
;
247 fprintf(stderr
,"pending %p %d %d %d\n", bo_legacy
, bo_legacy
->base
.size
,
248 boml
->current_age
, bo_legacy
->pending
);
249 next
= bo_legacy
->pnext
;
250 if (legacy_is_pending(&(bo_legacy
->base
))) {
256 static int legacy_wait_any_pending(struct bo_manager_legacy
*boml
)
258 struct bo_legacy
*bo_legacy
;
260 legacy_get_current_age(boml
);
261 bo_legacy
= boml
->pending_bos
.pnext
;
264 legacy_wait_pending(&bo_legacy
->base
);
268 static void legacy_kick_all_buffers(struct bo_manager_legacy
*boml
)
270 struct bo_legacy
*legacy
;
272 legacy
= boml
->bos
.next
;
273 while (legacy
!= &boml
->bos
) {
275 if (legacy
->validated
) {
276 driDestroyTextureObject(&legacy
->tobj
->base
);
278 legacy
->validated
= 0;
281 legacy
= legacy
->next
;
285 static struct bo_legacy
*bo_allocate(struct bo_manager_legacy
*boml
,
289 #ifdef RADEON_DEBUG_BO
294 #endif /* RADEON_DEBUG_BO */
296 struct bo_legacy
*bo_legacy
;
300 pgsize
= getpagesize() - 1;
302 size
= (size
+ pgsize
) & ~pgsize
;
304 bo_legacy
= (struct bo_legacy
*)calloc(1, sizeof(struct bo_legacy
));
305 if (bo_legacy
== NULL
) {
308 bo_legacy
->base
.bom
= (struct radeon_bo_manager
*)boml
;
309 bo_legacy
->base
.handle
= 0;
310 bo_legacy
->base
.size
= size
;
311 bo_legacy
->base
.alignment
= alignment
;
312 bo_legacy
->base
.domains
= domains
;
313 bo_legacy
->base
.flags
= flags
;
314 bo_legacy
->base
.ptr
= NULL
;
315 bo_legacy
->map_count
= 0;
316 bo_legacy
->next
= NULL
;
317 bo_legacy
->prev
= NULL
;
318 bo_legacy
->pnext
= NULL
;
319 bo_legacy
->pprev
= NULL
;
320 bo_legacy
->next
= boml
->bos
.next
;
321 bo_legacy
->prev
= &boml
->bos
;
322 boml
->bos
.next
= bo_legacy
;
323 if (bo_legacy
->next
) {
324 bo_legacy
->next
->prev
= bo_legacy
;
327 #ifdef RADEON_DEBUG_BO
328 sprintf(bo_legacy
->szBufUsage
, "%s", szBufUsage
);
329 #endif /* RADEON_DEBUG_BO */
334 static int bo_dma_alloc(struct radeon_bo
*bo
)
336 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bo
->bom
;
337 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
338 drm_radeon_mem_alloc_t alloc
;
343 /* align size on 4Kb */
344 size
= (((4 * 1024) - 1) + bo
->size
) & ~((4 * 1024) - 1);
345 alloc
.region
= RADEON_MEM_REGION_GART
;
346 alloc
.alignment
= bo_legacy
->base
.alignment
;
348 alloc
.region_offset
= &base_offset
;
349 r
= drmCommandWriteRead(bo
->bom
->fd
,
354 /* ptr is set to NULL if dma allocation failed */
355 bo_legacy
->ptr
= NULL
;
358 bo_legacy
->ptr
= boml
->screen
->gartTextures
.map
+ base_offset
;
359 bo_legacy
->offset
= boml
->screen
->gart_texture_offset
+ base_offset
;
361 boml
->dma_alloc_size
+= size
;
362 boml
->dma_buf_count
++;
366 static int bo_dma_free(struct radeon_bo
*bo
)
368 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bo
->bom
;
369 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
370 drm_radeon_mem_free_t memfree
;
373 if (bo_legacy
->ptr
== NULL
) {
374 /* ptr is set to NULL if dma allocation failed */
377 legacy_get_current_age(boml
);
378 memfree
.region
= RADEON_MEM_REGION_GART
;
379 memfree
.region_offset
= bo_legacy
->offset
;
380 memfree
.region_offset
-= boml
->screen
->gart_texture_offset
;
381 r
= drmCommandWrite(boml
->base
.fd
,
386 fprintf(stderr
, "Failed to free bo[%p] at %08x\n",
387 &bo_legacy
->base
, memfree
.region_offset
);
388 fprintf(stderr
, "ret = %s\n", strerror(-r
));
391 boml
->dma_alloc_size
-= bo_legacy
->base
.size
;
392 boml
->dma_buf_count
--;
396 static void bo_free(struct bo_legacy
*bo_legacy
)
398 struct bo_manager_legacy
*boml
;
400 if (bo_legacy
== NULL
) {
403 boml
= (struct bo_manager_legacy
*)bo_legacy
->base
.bom
;
404 bo_legacy
->prev
->next
= bo_legacy
->next
;
405 if (bo_legacy
->next
) {
406 bo_legacy
->next
->prev
= bo_legacy
->prev
;
408 if (!bo_legacy
->static_bo
) {
409 legacy_free_handle(boml
, bo_legacy
->base
.handle
);
410 if (bo_legacy
->base
.domains
& RADEON_GEM_DOMAIN_GTT
) {
412 bo_dma_free(&bo_legacy
->base
);
414 driDestroyTextureObject(&bo_legacy
->tobj
->base
);
415 bo_legacy
->tobj
= NULL
;
416 /* free backing store */
417 free(bo_legacy
->ptr
);
420 memset(bo_legacy
, 0 , sizeof(struct bo_legacy
));
424 static struct radeon_bo
*bo_open(struct radeon_bo_manager
*bom
,
429 #ifdef RADEON_DEBUG_BO
434 #endif /* RADEON_DEBUG_BO */
436 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bom
;
437 struct bo_legacy
*bo_legacy
;
441 bo_legacy
= boml
->bos
.next
;
443 if (bo_legacy
->base
.handle
== handle
) {
444 radeon_bo_ref(&(bo_legacy
->base
));
445 return (struct radeon_bo
*)bo_legacy
;
447 bo_legacy
= bo_legacy
->next
;
451 #ifdef RADEON_DEBUG_BO
452 bo_legacy
= bo_allocate(boml
, size
, alignment
, domains
, flags
, szBufUsage
);
454 bo_legacy
= bo_allocate(boml
, size
, alignment
, domains
, flags
);
455 #endif /* RADEON_DEBUG_BO */
456 bo_legacy
->static_bo
= 0;
457 r
= legacy_new_handle(boml
, &bo_legacy
->base
.handle
);
462 if (bo_legacy
->base
.domains
& RADEON_GEM_DOMAIN_GTT
)
465 legacy_track_pending(boml
, 0);
468 r
= bo_dma_alloc(&(bo_legacy
->base
));
471 if (legacy_wait_any_pending(boml
) == -1)
482 bo_legacy
->ptr
= malloc(bo_legacy
->base
.size
);
483 if (bo_legacy
->ptr
== NULL
) {
488 radeon_bo_ref(&(bo_legacy
->base
));
490 return (struct radeon_bo
*)bo_legacy
;
493 static void bo_ref(struct radeon_bo
*bo
)
497 static struct radeon_bo
*bo_unref(struct radeon_bo
*bo
)
499 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
502 bo_legacy
->prev
->next
= bo_legacy
->next
;
503 if (bo_legacy
->next
) {
504 bo_legacy
->next
->prev
= bo_legacy
->prev
;
506 if (!bo_legacy
->is_pending
) {
514 static int bo_map(struct radeon_bo
*bo
, int write
)
516 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bo
->bom
;
517 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
519 legacy_wait_pending(bo
);
520 bo_legacy
->validated
= 0;
521 bo_legacy
->dirty
= 1;
522 bo_legacy
->map_count
++;
523 bo
->ptr
= bo_legacy
->ptr
;
524 /* Read the first pixel in the frame buffer. This should
525 * be a noop, right? In fact without this conform fails as reading
526 * from the framebuffer sometimes produces old results -- the
527 * on-card read cache gets mixed up and doesn't notice that the
528 * framebuffer has been updated.
530 * Note that we should probably be reading some otherwise unused
531 * region of VRAM, otherwise we might get incorrect results when
532 * reading pixels from the top left of the screen.
534 * I found this problem on an R420 with glean's texCube test.
535 * Note that the R200 span code also *writes* the first pixel in the
536 * framebuffer, but I've found this to be unnecessary.
537 * -- Nicolai Hähnle, June 2008
539 if (!(bo
->domains
& RADEON_GEM_DOMAIN_GTT
)) {
541 volatile int *buf
= (int*)boml
->screen
->driScreen
->pFB
;
548 static int bo_unmap(struct radeon_bo
*bo
)
550 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
552 if (--bo_legacy
->map_count
> 0)
562 static struct radeon_bo_funcs bo_legacy_funcs
= {
570 static int bo_vram_validate(struct radeon_bo
*bo
,
574 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bo
->bom
;
575 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
577 int retry_count
= 0, pending_retry
= 0;
579 if (!bo_legacy
->tobj
) {
580 bo_legacy
->tobj
= CALLOC(sizeof(struct bo_legacy_texture_object
));
581 bo_legacy
->tobj
->parent
= bo_legacy
;
582 make_empty_list(&bo_legacy
->tobj
->base
);
583 bo_legacy
->tobj
->base
.totalSize
= bo
->size
;
585 r
= driAllocateTexture(&boml
->texture_heap
, 1,
586 &bo_legacy
->tobj
->base
);
589 while(boml
->cpendings
&& pending_retry
++ < 10000) {
590 legacy_track_pending(boml
, 0);
592 if (retry_count
> 2) {
593 free(bo_legacy
->tobj
);
594 bo_legacy
->tobj
= NULL
;
595 fprintf(stderr
, "Ouch! vram_validate failed %d\n", r
);
601 bo_legacy
->offset
= boml
->texture_offset
+
602 bo_legacy
->tobj
->base
.memBlock
->ofs
;
603 bo_legacy
->dirty
= 1;
606 assert(bo_legacy
->tobj
->base
.memBlock
);
609 driUpdateTextureLRU(&bo_legacy
->tobj
->base
);
611 if (bo_legacy
->dirty
|| bo_legacy
->tobj
->base
.dirty_images
[0]) {
612 if (IS_R600_CLASS(boml
->screen
)) {
613 char *src
= bo_legacy
->ptr
;
614 char *dst
= (char *) boml
->screen
->driScreen
->pFB
+
615 (bo_legacy
->offset
- boml
->fb_location
);
617 /* FIXME: alignment, pitch, etc. */
618 r600_sw_blit(src
, 0, dst
, 0, 0, 0, 1, 1, bo
->size
);
620 /* Copy to VRAM using a blit.
621 * All memory is 4K aligned. We're using 1024 pixels wide blits.
623 drm_radeon_texture_t tex
;
624 drm_radeon_tex_image_t tmp
;
627 tex
.offset
= bo_legacy
->offset
;
629 assert(!(tex
.offset
& 1023));
633 if (bo
->size
< 4096) {
634 tmp
.width
= (bo
->size
+ 3) / 4;
638 tmp
.height
= (bo
->size
+ 4095) / 4096;
640 tmp
.data
= bo_legacy
->ptr
;
641 tex
.format
= RADEON_TXFORMAT_ARGB8888
;
642 tex
.width
= tmp
.width
;
643 tex
.height
= tmp
.height
;
644 tex
.pitch
= MAX2(tmp
.width
/ 16, 1);
646 ret
= drmCommandWriteRead(bo
->bom
->fd
,
649 sizeof(drm_radeon_texture_t
));
651 if (RADEON_DEBUG
& DEBUG_IOCTL
)
652 fprintf(stderr
, "DRM_RADEON_TEXTURE: again!\n");
655 } while (ret
== -EAGAIN
);
657 bo_legacy
->dirty
= 0;
658 bo_legacy
->tobj
->base
.dirty_images
[0] = 0;
664 * radeon_bo_legacy_validate -
667 * -EINVAL - mapped buffer can't be validated
668 * -EAGAIN - restart validation we've kicked all the buffers out
670 int radeon_bo_legacy_validate(struct radeon_bo
*bo
,
674 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bo
->bom
;
675 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
679 if (bo_legacy
->map_count
) {
680 #ifdef RADEON_DEBUG_BO
681 fprintf(stderr
, "bo(%p, %d, %s) is mapped (%d) can't valide it.\n",
682 bo
, bo
->size
, bo_legacy
->szBufUsage
, bo_legacy
->map_count
);
684 fprintf(stderr
, "bo(%p, %d) is mapped (%d) can't valide it.\n",
685 bo
, bo
->size
, bo_legacy
->map_count
);
686 #endif /* RADEON_DEBUG_BO */
690 if (bo_legacy
->static_bo
|| bo_legacy
->validated
) {
691 *soffset
= bo_legacy
->offset
;
692 *eoffset
= bo_legacy
->offset
+ bo
->size
;
696 if (!(bo
->domains
& RADEON_GEM_DOMAIN_GTT
)) {
698 r
= bo_vram_validate(bo
, soffset
, eoffset
);
700 legacy_track_pending(boml
, 0);
701 legacy_kick_all_buffers(boml
);
704 fprintf(stderr
,"legacy bo: failed to get relocations into aperture\n");
711 *soffset
= bo_legacy
->offset
;
712 *eoffset
= bo_legacy
->offset
+ bo
->size
;
713 bo_legacy
->validated
= 1;
718 void radeon_bo_legacy_pending(struct radeon_bo
*bo
, uint32_t pending
)
720 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bo
->bom
;
721 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
723 bo_legacy
->pending
= pending
;
724 bo_legacy
->is_pending
++;
725 /* add to pending list */
727 if (bo_legacy
->is_pending
> 1) {
730 bo_legacy
->pprev
= boml
->pending_bos
.pprev
;
731 bo_legacy
->pnext
= NULL
;
732 bo_legacy
->pprev
->pnext
= bo_legacy
;
733 boml
->pending_bos
.pprev
= bo_legacy
;
737 void radeon_bo_manager_legacy_dtor(struct radeon_bo_manager
*bom
)
739 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bom
;
740 struct bo_legacy
*bo_legacy
;
745 bo_legacy
= boml
->bos
.next
;
747 struct bo_legacy
*next
;
749 next
= bo_legacy
->next
;
753 driDestroyTextureHeap(boml
->texture_heap
);
754 free(boml
->free_handles
);
758 static struct bo_legacy
*radeon_legacy_bo_alloc_static(struct bo_manager_legacy
*bom
,
760 #ifdef RADEON_DEBUG_BO
765 #endif /* RADEON_DEBUG_BO */
767 struct bo_legacy
*bo
;
769 #ifdef RADEON_DEBUG_BO
770 bo
= bo_allocate(bom
, size
, 0, RADEON_GEM_DOMAIN_VRAM
, 0, szBufUsage
);
772 bo
= bo_allocate(bom
, size
, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
773 #endif /* RADEON_DEBUG_BO */
777 bo
->offset
= offset
+ bom
->fb_location
;
778 bo
->base
.handle
= bo
->offset
;
779 bo
->ptr
= bom
->screen
->driScreen
->pFB
+ offset
;
780 if (bo
->base
.handle
> bom
->nhandle
) {
781 bom
->nhandle
= bo
->base
.handle
+ 1;
783 radeon_bo_ref(&(bo
->base
));
787 struct radeon_bo_manager
*radeon_bo_manager_legacy_ctor(struct radeon_screen
*scrn
)
789 struct bo_manager_legacy
*bom
;
790 struct bo_legacy
*bo
;
793 bom
= (struct bo_manager_legacy
*)
794 calloc(1, sizeof(struct bo_manager_legacy
));
799 make_empty_list(&bom
->texture_swapped
);
801 bom
->texture_heap
= driCreateTextureHeap(0,
805 RADEON_NR_TEX_REGIONS
,
806 (drmTextureRegionPtr
)scrn
->sarea
->tex_list
[0],
807 &scrn
->sarea
->tex_age
[0],
808 &bom
->texture_swapped
,
809 sizeof(struct bo_legacy_texture_object
),
810 &bo_legacy_tobj_destroy
);
811 bom
->texture_offset
= scrn
->texOffset
[0];
813 bom
->base
.funcs
= &bo_legacy_funcs
;
814 bom
->base
.fd
= scrn
->driScreen
->fd
;
815 bom
->bos
.next
= NULL
;
816 bom
->bos
.prev
= NULL
;
817 bom
->pending_bos
.pprev
= &bom
->pending_bos
;
818 bom
->pending_bos
.pnext
= NULL
;
820 bom
->fb_location
= scrn
->fbLocation
;
822 bom
->cfree_handles
= 0;
823 bom
->nfree_handles
= 0x400;
824 bom
->free_handles
= (uint32_t*)malloc(bom
->nfree_handles
* 4);
825 if (bom
->free_handles
== NULL
) {
826 radeon_bo_manager_legacy_dtor((struct radeon_bo_manager
*)bom
);
830 /* biggest framebuffer size */
834 #ifdef RADEON_DEBUG_BO
835 bo
= radeon_legacy_bo_alloc_static(bom
, size
, bom
->screen
->frontOffset
, "FRONT BUF");
837 bo
= radeon_legacy_bo_alloc_static(bom
, size
, bom
->screen
->frontOffset
);
838 #endif /* RADEON_DEBUG_BO */
840 radeon_bo_manager_legacy_dtor((struct radeon_bo_manager
*)bom
);
843 if (scrn
->sarea
->tiling_enabled
) {
844 bo
->base
.flags
= RADEON_BO_FLAGS_MACRO_TILE
;
848 #ifdef RADEON_DEBUG_BO
849 bo
= radeon_legacy_bo_alloc_static(bom
, size
, bom
->screen
->backOffset
, "BACK BUF");
851 bo
= radeon_legacy_bo_alloc_static(bom
, size
, bom
->screen
->backOffset
);
852 #endif /* RADEON_DEBUG_BO */
854 radeon_bo_manager_legacy_dtor((struct radeon_bo_manager
*)bom
);
857 if (scrn
->sarea
->tiling_enabled
) {
858 bo
->base
.flags
= RADEON_BO_FLAGS_MACRO_TILE
;
862 #ifdef RADEON_DEBUG_BO
863 bo
= radeon_legacy_bo_alloc_static(bom
, size
, bom
->screen
->depthOffset
, "Z BUF");
865 bo
= radeon_legacy_bo_alloc_static(bom
, size
, bom
->screen
->depthOffset
);
866 #endif /* RADEON_DEBUG_BO */
868 radeon_bo_manager_legacy_dtor((struct radeon_bo_manager
*)bom
);
872 if (scrn
->sarea
->tiling_enabled
) {
873 bo
->base
.flags
|= RADEON_BO_FLAGS_MACRO_TILE
;
874 bo
->base
.flags
|= RADEON_BO_FLAGS_MICRO_TILE
;
876 return (struct radeon_bo_manager
*)bom
;
879 void radeon_bo_legacy_texture_age(struct radeon_bo_manager
*bom
)
881 struct bo_manager_legacy
*boml
= (struct bo_manager_legacy
*)bom
;
882 DRI_AGE_TEXTURES(boml
->texture_heap
);
885 unsigned radeon_bo_legacy_relocs_size(struct radeon_bo
*bo
)
887 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
889 if (bo_legacy
->static_bo
|| (bo
->domains
& RADEON_GEM_DOMAIN_GTT
)) {
895 int radeon_legacy_bo_is_static(struct radeon_bo
*bo
)
897 struct bo_legacy
*bo_legacy
= (struct bo_legacy
*)bo
;
898 return bo_legacy
->static_bo
;