1 #ifndef RADEON_CS_WRAPPER_H
2 #define RADEON_CS_WRAPPER_H
4 #ifdef HAVE_LIBDRM_RADEON
7 #include "radeon_bo_gem.h"
9 #include "radeon_cs_gem.h"
14 #define RADEON_GEM_DOMAIN_CPU 0x1 // Cached CPU domain
15 #define RADEON_GEM_DOMAIN_GTT 0x2 // GTT or cache flushed
16 #define RADEON_GEM_DOMAIN_VRAM 0x4 // VRAM domain
18 #define RADEON_TILING_MACRO 0x1
19 #define RADEON_TILING_MICRO 0x2
20 #define RADEON_TILING_SWAP 0x4
22 #ifndef RADEON_TILING_SURFACE
23 #define RADEON_TILING_SURFACE 0x8 /* this object requires a surface
24 * when mapped - i.e. front buffer */
27 /* to be used to build locally in mesa with no libdrm bits */
28 #include "../radeon/radeon_bo_drm.h"
29 #include "../radeon/radeon_cs_drm.h"
31 #ifndef DRM_RADEON_GEM_INFO
32 #define DRM_RADEON_GEM_INFO 0x1c
34 struct drm_radeon_gem_info
{
37 uint64_t vram_visible
;
40 struct drm_radeon_info
{
47 #ifndef RADEON_PARAM_DEVICE_ID
48 #define RADEON_PARAM_DEVICE_ID 16
51 #ifndef RADEON_PARAM_NUM_Z_PIPES
52 #define RADEON_PARAM_NUM_Z_PIPES 17
55 #ifndef RADEON_INFO_DEVICE_ID
56 #define RADEON_INFO_DEVICE_ID 0
58 #ifndef RADEON_INFO_NUM_GB_PIPES
59 #define RADEON_INFO_NUM_GB_PIPES 0
62 #ifndef RADEON_INFO_NUM_Z_PIPES
63 #define RADEON_INFO_NUM_Z_PIPES 0
66 #ifndef DRM_RADEON_INFO
67 #define DRM_RADEON_INFO 0x1
71 static inline uint32_t radeon_gem_name_bo(struct radeon_bo
*dummy
)
76 static inline void *radeon_bo_manager_gem_ctor(int fd
)
81 static inline void radeon_bo_manager_gem_dtor(void *dummy
)
85 static inline void *radeon_cs_manager_gem_ctor(int fd
)
90 static inline void radeon_cs_manager_gem_dtor(void *dummy
)
94 static inline void radeon_tracker_print(void *ptr
, int io
)
99 #include "radeon_bo_legacy.h"
100 #include "radeon_cs_legacy.h"