1 #ifndef COMMON_CMDBUF_H
2 #define COMMON_CMDBUF_H
4 GLboolean
rcommonEnsureCmdBufSpace(radeonContextPtr rmesa
, int dwords
, const char *caller
);
5 int rcommonFlushCmdBuf(radeonContextPtr rmesa
, const char *caller
);
6 int rcommonFlushCmdBufLocked(radeonContextPtr rmesa
, const char *caller
);
7 void rcommonInitCmdBuf(radeonContextPtr rmesa
);
8 void rcommonDestroyCmdBuf(radeonContextPtr rmesa
);
10 void rcommonBeginBatch(radeonContextPtr rmesa
,
16 /* +r6/r7 : code here moved */
18 #define CP_PACKET2 (2 << 30)
19 #define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2))
20 #define CP_PACKET0_ONE(reg, n) (RADEON_CP_PACKET0 | RADEON_CP_PACKET0_ONE_REG_WR | ((n)<<16) | ((reg)>>2))
21 #define CP_PACKET3(pkt, n) (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
24 * Every function writing to the command buffer needs to declare this
25 * to get the necessary local variables.
27 #define BATCH_LOCALS(rmesa) \
28 const radeonContextPtr b_l_rmesa = rmesa
31 * Prepare writing n dwords to the command buffer,
32 * including producing any necessary state emits on buffer wraparound.
34 #define BEGIN_BATCH(n) rcommonBeginBatch(b_l_rmesa, n, __FILE__, __FUNCTION__, __LINE__)
37 * Same as BEGIN_BATCH, but do not cause automatic state emits.
39 #define BEGIN_BATCH_NO_AUTOSTATE(n) rcommonBeginBatch(b_l_rmesa, n, __FILE__, __FUNCTION__, __LINE__)
42 * Write one dword to the command buffer.
44 #define OUT_BATCH(data) \
46 radeon_cs_write_dword(b_l_rmesa->cmdbuf.cs, data);\
50 * Write a relocated dword to the command buffer.
52 #define OUT_BATCH_RELOC(data, bo, offset, rd, wd, flags) \
54 int __offset = (offset); \
55 if (0 && __offset) { \
56 fprintf(stderr, "(%s:%s:%d) offset : %d\n", \
57 __FILE__, __FUNCTION__, __LINE__, __offset); \
59 radeon_cs_write_dword(b_l_rmesa->cmdbuf.cs, __offset); \
60 radeon_cs_write_reloc(b_l_rmesa->cmdbuf.cs, \
66 * Write n dwords from ptr to the command buffer.
68 #define OUT_BATCH_TABLE(ptr,n) \
70 radeon_cs_write_table(b_l_rmesa->cmdbuf.cs, (ptr), (n));\
74 * Finish writing dwords to the command buffer.
75 * The number of (direct or indirect) OUT_BATCH calls between the previous
76 * BEGIN_BATCH and END_BATCH must match the number specified at BEGIN_BATCH time.
80 radeon_cs_end(b_l_rmesa->cmdbuf.cs, __FILE__, __FUNCTION__, __LINE__);\
84 * After the last END_BATCH() of rendering, this indicates that flushing
85 * the command buffer now is okay.
87 #define COMMIT_BATCH() \
92 /** Single register write to command buffer; requires 2 dwords. */
93 #define OUT_BATCH_REGVAL(reg, val) \
94 OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), 1)); \
97 /** Continuous register range write to command buffer; requires 1 dword,
98 * expects count dwords afterwards for register contents. */
99 #define OUT_BATCH_REGSEQ(reg, count) \
100 OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), (count)))
102 /* +r6/r7 : code here moved */
104 /* Fire the buffered vertices no matter what.
106 static INLINE
void radeon_firevertices(radeonContextPtr radeon
)
108 if (radeon
->cmdbuf
.cs
->cdw
|| radeon
->dma
.flush
)
109 radeon
->glCtx
.Driver
.Flush(&radeon
->glCtx
); /* +r6/r7 */