1 #ifndef COMMON_CMDBUF_H
2 #define COMMON_CMDBUF_H
4 #include "radeon_bocs_wrapper.h"
6 GLboolean
rcommonEnsureCmdBufSpace(radeonContextPtr rmesa
, int dwords
, const char *caller
);
7 int rcommonFlushCmdBuf(radeonContextPtr rmesa
, const char *caller
);
8 int rcommonFlushCmdBufLocked(radeonContextPtr rmesa
, const char *caller
);
9 void rcommonInitCmdBuf(radeonContextPtr rmesa
);
10 void rcommonDestroyCmdBuf(radeonContextPtr rmesa
);
12 void rcommonBeginBatch(radeonContextPtr rmesa
,
19 /* +r6/r7 : code here moved */
21 #define CP_PACKET2 (2 << 30)
22 #define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2))
23 #define CP_PACKET0_ONE(reg, n) (RADEON_CP_PACKET0 | RADEON_CP_PACKET0_ONE_REG_WR | ((n)<<16) | ((reg)>>2))
24 #define CP_PACKET3(pkt, n) (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
27 * Every function writing to the command buffer needs to declare this
28 * to get the necessary local variables.
30 #define BATCH_LOCALS(rmesa) \
31 const radeonContextPtr b_l_rmesa = rmesa
34 * Prepare writing n dwords to the command buffer,
35 * including producing any necessary state emits on buffer wraparound.
37 #define BEGIN_BATCH(n) rcommonBeginBatch(b_l_rmesa, n, 1, __FILE__, __FUNCTION__, __LINE__)
40 * Same as BEGIN_BATCH, but do not cause automatic state emits.
42 #define BEGIN_BATCH_NO_AUTOSTATE(n) rcommonBeginBatch(b_l_rmesa, n, 0, __FILE__, __FUNCTION__, __LINE__)
45 * Write one dword to the command buffer.
47 #define OUT_BATCH(data) \
49 radeon_cs_write_dword(b_l_rmesa->cmdbuf.cs, data);\
53 * Write a relocated dword to the command buffer.
55 #define OUT_BATCH_RELOC(data, bo, offset, rd, wd, flags) \
57 int __offset = (offset); \
58 if (0 && __offset) { \
59 fprintf(stderr, "(%s:%s:%d) offset : %d\n", \
60 __FILE__, __FUNCTION__, __LINE__, __offset); \
62 radeon_cs_write_dword(b_l_rmesa->cmdbuf.cs, __offset); \
63 radeon_cs_write_reloc(b_l_rmesa->cmdbuf.cs, \
65 if (!b_l_rmesa->radeonScreen->kernel_mm) \
66 b_l_rmesa->cmdbuf.cs->section_cdw += 2; \
71 * Write n dwords from ptr to the command buffer.
73 #define OUT_BATCH_TABLE(ptr,n) \
75 radeon_cs_write_table(b_l_rmesa->cmdbuf.cs, (ptr), (n));\
79 * Finish writing dwords to the command buffer.
80 * The number of (direct or indirect) OUT_BATCH calls between the previous
81 * BEGIN_BATCH and END_BATCH must match the number specified at BEGIN_BATCH time.
85 radeon_cs_end(b_l_rmesa->cmdbuf.cs, __FILE__, __FUNCTION__, __LINE__);\
89 * After the last END_BATCH() of rendering, this indicates that flushing
90 * the command buffer now is okay.
92 #define COMMIT_BATCH() \
97 /** Single register write to command buffer; requires 2 dwords. */
98 #define OUT_BATCH_REGVAL(reg, val) \
99 OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), 1)); \
102 /** Continuous register range write to command buffer; requires 1 dword,
103 * expects count dwords afterwards for register contents. */
104 #define OUT_BATCH_REGSEQ(reg, count) \
105 OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), (count)))
107 /** Write a 32 bit float to the ring; requires 1 dword. */
108 #define OUT_BATCH_FLOAT32(f) \
109 OUT_BATCH(radeonPackFloat32((f)))
111 /* +r6/r7 : code here moved */
113 /* Fire the buffered vertices no matter what.
115 static INLINE
void radeon_firevertices(radeonContextPtr radeon
)
117 if (radeon
->cmdbuf
.cs
->cdw
|| radeon
->dma
.flush
)
118 radeon
->glCtx
->Driver
.Flush(radeon
->glCtx
); /* +r6/r7 */