1 /**************************************************************************
3 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
5 The Weather Channel (TM) funded Tungsten Graphics to develop the
6 initial release of the Radeon 8500 driver under the XFree86 license.
7 This notice must be preserved.
9 Permission is hereby granted, free of charge, to any person obtaining
10 a copy of this software and associated documentation files (the
11 "Software"), to deal in the Software without restriction, including
12 without limitation the rights to use, copy, modify, merge, publish,
13 distribute, sublicense, and/or sell copies of the Software, and to
14 permit persons to whom the Software is furnished to do so, subject to
15 the following conditions:
17 The above copyright notice and this permission notice (including the
18 next paragraph) shall be included in all copies or substantial
19 portions of the Software.
21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 **************************************************************************/
33 * Keith Whitwell <keith@tungstengraphics.com>
37 - Scissor implementation
38 - buffer swap/copy ioctls
41 - cmdbuffer management
45 #include "main/glheader.h"
46 #include "main/imports.h"
47 #include "main/context.h"
48 #include "main/enums.h"
49 #include "main/framebuffer.h"
50 #include "main/renderbuffer.h"
51 #include "drivers/common/meta.h"
55 #include "radeon_common.h"
56 #include "radeon_bocs_wrapper.h"
57 #include "radeon_lock.h"
58 #include "radeon_drm.h"
59 #include "radeon_queryobj.h"
62 * Enable verbose debug output for emit code.
65 * 2 also print state alues
67 #define RADEON_CMDBUF 0
69 /* =============================================================
73 static GLboolean
intersect_rect(drm_clip_rect_t
* out
,
74 drm_clip_rect_t
* a
, drm_clip_rect_t
* b
)
85 if (out
->x1
>= out
->x2
)
87 if (out
->y1
>= out
->y2
)
92 void radeonRecalcScissorRects(radeonContextPtr radeon
)
97 /* Grow cliprect store?
99 if (radeon
->state
.scissor
.numAllocedClipRects
< radeon
->numClipRects
) {
100 while (radeon
->state
.scissor
.numAllocedClipRects
<
101 radeon
->numClipRects
) {
102 radeon
->state
.scissor
.numAllocedClipRects
+= 1; /* zero case */
103 radeon
->state
.scissor
.numAllocedClipRects
*= 2;
106 if (radeon
->state
.scissor
.pClipRects
)
107 FREE(radeon
->state
.scissor
.pClipRects
);
109 radeon
->state
.scissor
.pClipRects
=
110 MALLOC(radeon
->state
.scissor
.numAllocedClipRects
*
111 sizeof(drm_clip_rect_t
));
113 if (radeon
->state
.scissor
.pClipRects
== NULL
) {
114 radeon
->state
.scissor
.numAllocedClipRects
= 0;
119 out
= radeon
->state
.scissor
.pClipRects
;
120 radeon
->state
.scissor
.numClipRects
= 0;
122 for (i
= 0; i
< radeon
->numClipRects
; i
++) {
123 if (intersect_rect(out
,
124 &radeon
->pClipRects
[i
],
125 &radeon
->state
.scissor
.rect
)) {
126 radeon
->state
.scissor
.numClipRects
++;
131 if (radeon
->vtbl
.update_scissor
)
132 radeon
->vtbl
.update_scissor(radeon
->glCtx
);
135 void radeon_get_cliprects(radeonContextPtr radeon
,
136 struct drm_clip_rect
**cliprects
,
137 unsigned int *num_cliprects
,
138 int *x_off
, int *y_off
)
140 __DRIdrawable
*dPriv
= radeon_get_drawable(radeon
);
141 struct radeon_framebuffer
*rfb
= dPriv
->driverPrivate
;
143 if (radeon
->constant_cliprect
) {
144 radeon
->fboRect
.x1
= 0;
145 radeon
->fboRect
.y1
= 0;
146 radeon
->fboRect
.x2
= radeon
->glCtx
->DrawBuffer
->Width
;
147 radeon
->fboRect
.y2
= radeon
->glCtx
->DrawBuffer
->Height
;
149 *cliprects
= &radeon
->fboRect
;
153 } else if (radeon
->front_cliprects
||
154 rfb
->pf_active
|| dPriv
->numBackClipRects
== 0) {
155 *cliprects
= dPriv
->pClipRects
;
156 *num_cliprects
= dPriv
->numClipRects
;
160 *num_cliprects
= dPriv
->numBackClipRects
;
161 *cliprects
= dPriv
->pBackClipRects
;
162 *x_off
= dPriv
->backX
;
163 *y_off
= dPriv
->backY
;
168 * Update cliprects and scissors.
170 void radeonSetCliprects(radeonContextPtr radeon
)
172 __DRIdrawable
*const drawable
= radeon_get_drawable(radeon
);
173 __DRIdrawable
*const readable
= radeon_get_readable(radeon
);
174 struct radeon_framebuffer
*const draw_rfb
= drawable
->driverPrivate
;
175 struct radeon_framebuffer
*const read_rfb
= readable
->driverPrivate
;
178 radeon_get_cliprects(radeon
, &radeon
->pClipRects
,
179 &radeon
->numClipRects
, &x_off
, &y_off
);
181 if ((draw_rfb
->base
.Width
!= drawable
->w
) ||
182 (draw_rfb
->base
.Height
!= drawable
->h
)) {
183 _mesa_resize_framebuffer(radeon
->glCtx
, &draw_rfb
->base
,
184 drawable
->w
, drawable
->h
);
185 draw_rfb
->base
.Initialized
= GL_TRUE
;
188 if (drawable
!= readable
) {
189 if ((read_rfb
->base
.Width
!= readable
->w
) ||
190 (read_rfb
->base
.Height
!= readable
->h
)) {
191 _mesa_resize_framebuffer(radeon
->glCtx
, &read_rfb
->base
,
192 readable
->w
, readable
->h
);
193 read_rfb
->base
.Initialized
= GL_TRUE
;
197 if (radeon
->state
.scissor
.enabled
)
198 radeonRecalcScissorRects(radeon
);
204 void radeonUpdateScissor( GLcontext
*ctx
)
206 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
207 GLint x
= ctx
->Scissor
.X
, y
= ctx
->Scissor
.Y
;
208 GLsizei w
= ctx
->Scissor
.Width
, h
= ctx
->Scissor
.Height
;
210 int min_x
, min_y
, max_x
, max_y
;
212 if (!ctx
->DrawBuffer
)
215 max_x
= ctx
->DrawBuffer
->Width
- 1;
216 max_y
= ctx
->DrawBuffer
->Height
- 1;
218 if ( !ctx
->DrawBuffer
->Name
) {
220 y1
= ctx
->DrawBuffer
->Height
- (y
+ h
);
230 if (!rmesa
->radeonScreen
->kernel_mm
) {
231 /* Fix scissors for dri 1 */
232 __DRIdrawable
*dPriv
= radeon_get_drawable(rmesa
);
236 max_x
+= dPriv
->x
+ 1;
240 max_y
+= dPriv
->y
+ 1;
243 rmesa
->state
.scissor
.rect
.x1
= CLAMP(x1
, min_x
, max_x
);
244 rmesa
->state
.scissor
.rect
.y1
= CLAMP(y1
, min_y
, max_y
);
245 rmesa
->state
.scissor
.rect
.x2
= CLAMP(x2
, min_x
, max_x
);
246 rmesa
->state
.scissor
.rect
.y2
= CLAMP(y2
, min_y
, max_y
);
248 radeonRecalcScissorRects( rmesa
);
251 /* =============================================================
255 void radeonScissor(GLcontext
* ctx
, GLint x
, GLint y
, GLsizei w
, GLsizei h
)
257 radeonContextPtr radeon
= RADEON_CONTEXT(ctx
);
258 if (ctx
->Scissor
.Enabled
) {
259 /* We don't pipeline cliprect changes */
260 radeon_firevertices(radeon
);
261 radeonUpdateScissor(ctx
);
265 /* ================================================================
266 * SwapBuffers with client-side throttling
269 static uint32_t radeonGetLastFrame(radeonContextPtr radeon
)
271 drm_radeon_getparam_t gp
;
275 gp
.param
= RADEON_PARAM_LAST_FRAME
;
276 gp
.value
= (int *)&frame
;
277 ret
= drmCommandWriteRead(radeon
->dri
.fd
, DRM_RADEON_GETPARAM
,
280 fprintf(stderr
, "%s: drmRadeonGetParam: %d\n", __FUNCTION__
,
288 uint32_t radeonGetAge(radeonContextPtr radeon
)
290 drm_radeon_getparam_t gp
;
294 gp
.param
= RADEON_PARAM_LAST_CLEAR
;
295 gp
.value
= (int *)&age
;
296 ret
= drmCommandWriteRead(radeon
->dri
.fd
, DRM_RADEON_GETPARAM
,
299 fprintf(stderr
, "%s: drmRadeonGetParam: %d\n", __FUNCTION__
,
307 static void radeonEmitIrqLocked(radeonContextPtr radeon
)
309 drm_radeon_irq_emit_t ie
;
312 ie
.irq_seq
= &radeon
->iw
.irq_seq
;
313 ret
= drmCommandWriteRead(radeon
->dri
.fd
, DRM_RADEON_IRQ_EMIT
,
316 fprintf(stderr
, "%s: drmRadeonIrqEmit: %d\n", __FUNCTION__
,
322 static void radeonWaitIrq(radeonContextPtr radeon
)
327 ret
= drmCommandWrite(radeon
->dri
.fd
, DRM_RADEON_IRQ_WAIT
,
328 &radeon
->iw
, sizeof(radeon
->iw
));
329 } while (ret
&& (errno
== EINTR
|| errno
== EBUSY
));
332 fprintf(stderr
, "%s: drmRadeonIrqWait: %d\n", __FUNCTION__
,
338 static void radeonWaitForFrameCompletion(radeonContextPtr radeon
)
340 drm_radeon_sarea_t
*sarea
= radeon
->sarea
;
342 if (radeon
->do_irqs
) {
343 if (radeonGetLastFrame(radeon
) < sarea
->last_frame
) {
344 if (!radeon
->irqsEmitted
) {
345 while (radeonGetLastFrame(radeon
) <
348 UNLOCK_HARDWARE(radeon
);
349 radeonWaitIrq(radeon
);
350 LOCK_HARDWARE(radeon
);
352 radeon
->irqsEmitted
= 10;
355 if (radeon
->irqsEmitted
) {
356 radeonEmitIrqLocked(radeon
);
357 radeon
->irqsEmitted
--;
360 while (radeonGetLastFrame(radeon
) < sarea
->last_frame
) {
361 UNLOCK_HARDWARE(radeon
);
362 if (radeon
->do_usleeps
)
364 LOCK_HARDWARE(radeon
);
370 void radeonWaitForIdleLocked(radeonContextPtr radeon
)
376 ret
= drmCommandNone(radeon
->dri
.fd
, DRM_RADEON_CP_IDLE
);
379 } while (ret
&& ++i
< 100);
382 UNLOCK_HARDWARE(radeon
);
383 fprintf(stderr
, "Error: R300 timed out... exiting\n");
388 static void radeonWaitForIdle(radeonContextPtr radeon
)
390 if (!radeon
->radeonScreen
->driScreen
->dri2
.enabled
) {
391 LOCK_HARDWARE(radeon
);
392 radeonWaitForIdleLocked(radeon
);
393 UNLOCK_HARDWARE(radeon
);
397 static void radeon_flip_renderbuffers(struct radeon_framebuffer
*rfb
)
399 int current_page
= rfb
->pf_current_page
;
400 int next_page
= (current_page
+ 1) % rfb
->pf_num_pages
;
401 struct gl_renderbuffer
*tmp_rb
;
403 /* Exchange renderbuffers if necessary but make sure their
404 * reference counts are preserved.
406 if (rfb
->color_rb
[current_page
] &&
407 rfb
->base
.Attachment
[BUFFER_FRONT_LEFT
].Renderbuffer
!=
408 &rfb
->color_rb
[current_page
]->base
) {
410 _mesa_reference_renderbuffer(&tmp_rb
,
411 rfb
->base
.Attachment
[BUFFER_FRONT_LEFT
].Renderbuffer
);
412 tmp_rb
= &rfb
->color_rb
[current_page
]->base
;
413 _mesa_reference_renderbuffer(&rfb
->base
.Attachment
[BUFFER_FRONT_LEFT
].Renderbuffer
, tmp_rb
);
414 _mesa_reference_renderbuffer(&tmp_rb
, NULL
);
417 if (rfb
->color_rb
[next_page
] &&
418 rfb
->base
.Attachment
[BUFFER_BACK_LEFT
].Renderbuffer
!=
419 &rfb
->color_rb
[next_page
]->base
) {
421 _mesa_reference_renderbuffer(&tmp_rb
,
422 rfb
->base
.Attachment
[BUFFER_BACK_LEFT
].Renderbuffer
);
423 tmp_rb
= &rfb
->color_rb
[next_page
]->base
;
424 _mesa_reference_renderbuffer(&rfb
->base
.Attachment
[BUFFER_BACK_LEFT
].Renderbuffer
, tmp_rb
);
425 _mesa_reference_renderbuffer(&tmp_rb
, NULL
);
429 /* Copy the back color buffer to the front color buffer.
431 void radeonCopyBuffer( __DRIdrawable
*dPriv
,
432 const drm_clip_rect_t
*rect
)
434 radeonContextPtr rmesa
;
435 struct radeon_framebuffer
*rfb
;
439 assert(dPriv
->driContextPriv
);
440 assert(dPriv
->driContextPriv
->driverPrivate
);
442 rmesa
= (radeonContextPtr
) dPriv
->driContextPriv
->driverPrivate
;
444 LOCK_HARDWARE(rmesa
);
446 rfb
= dPriv
->driverPrivate
;
448 if ( RADEON_DEBUG
& RADEON_IOCTL
) {
449 fprintf( stderr
, "\n%s( %p )\n\n", __FUNCTION__
, (void *) rmesa
->glCtx
);
452 nbox
= dPriv
->numClipRects
; /* must be in locked region */
454 for ( i
= 0 ; i
< nbox
; ) {
455 GLint nr
= MIN2( i
+ RADEON_NR_SAREA_CLIPRECTS
, nbox
);
456 drm_clip_rect_t
*box
= dPriv
->pClipRects
;
457 drm_clip_rect_t
*b
= rmesa
->sarea
->boxes
;
460 for ( ; i
< nr
; i
++ ) {
466 if (rect
->x1
> b
->x1
)
468 if (rect
->y1
> b
->y1
)
470 if (rect
->x2
< b
->x2
)
472 if (rect
->y2
< b
->y2
)
475 if (b
->x1
>= b
->x2
|| b
->y1
>= b
->y2
)
482 rmesa
->sarea
->nbox
= n
;
487 ret
= drmCommandNone( rmesa
->dri
.fd
, DRM_RADEON_SWAP
);
490 fprintf( stderr
, "DRM_RADEON_SWAP_BUFFERS: return = %d\n", ret
);
491 UNLOCK_HARDWARE( rmesa
);
496 UNLOCK_HARDWARE( rmesa
);
499 static int radeonScheduleSwap(__DRIdrawable
*dPriv
, GLboolean
*missed_target
)
501 radeonContextPtr rmesa
;
503 rmesa
= (radeonContextPtr
) dPriv
->driContextPriv
->driverPrivate
;
504 radeon_firevertices(rmesa
);
506 LOCK_HARDWARE( rmesa
);
508 if (!dPriv
->numClipRects
) {
509 UNLOCK_HARDWARE(rmesa
);
510 usleep(10000); /* throttle invisible client 10ms */
514 radeonWaitForFrameCompletion(rmesa
);
516 UNLOCK_HARDWARE(rmesa
);
517 driWaitForVBlank(dPriv
, missed_target
);
522 static GLboolean
radeonPageFlip( __DRIdrawable
*dPriv
)
524 radeonContextPtr radeon
;
527 struct radeon_renderbuffer
*rrb
;
528 struct radeon_framebuffer
*rfb
;
531 assert(dPriv
->driContextPriv
);
532 assert(dPriv
->driContextPriv
->driverPrivate
);
534 radeon
= (radeonContextPtr
) dPriv
->driContextPriv
->driverPrivate
;
535 rfb
= dPriv
->driverPrivate
;
536 rrb
= (void *)rfb
->base
.Attachment
[BUFFER_FRONT_LEFT
].Renderbuffer
;
538 psp
= dPriv
->driScreenPriv
;
540 LOCK_HARDWARE(radeon
);
542 if ( RADEON_DEBUG
& RADEON_IOCTL
) {
543 fprintf(stderr
, "%s: pfCurrentPage: %d %d\n", __FUNCTION__
,
544 radeon
->sarea
->pfCurrentPage
, radeon
->sarea
->pfState
);
546 drm_clip_rect_t
*box
= dPriv
->pClipRects
;
547 drm_clip_rect_t
*b
= radeon
->sarea
->boxes
;
549 radeon
->sarea
->nbox
= 1;
551 ret
= drmCommandNone( radeon
->dri
.fd
, DRM_RADEON_FLIP
);
553 UNLOCK_HARDWARE(radeon
);
556 fprintf( stderr
, "DRM_RADEON_FLIP: return = %d\n", ret
);
563 rfb
->pf_current_page
= radeon
->sarea
->pfCurrentPage
;
564 radeon_flip_renderbuffers(rfb
);
565 radeon_draw_buffer(radeon
->glCtx
, &rfb
->base
);
572 * Swap front and back buffer.
574 void radeonSwapBuffers(__DRIdrawable
* dPriv
)
579 if (dPriv
->driContextPriv
&& dPriv
->driContextPriv
->driverPrivate
) {
580 radeonContextPtr radeon
;
583 radeon
= (radeonContextPtr
) dPriv
->driContextPriv
->driverPrivate
;
586 if (ctx
->Visual
.doubleBufferMode
) {
587 GLboolean missed_target
;
588 struct radeon_framebuffer
*rfb
= dPriv
->driverPrivate
;
589 _mesa_notifySwapBuffers(ctx
);/* flush pending rendering comands */
591 radeonScheduleSwap(dPriv
, &missed_target
);
593 if (rfb
->pf_active
) {
594 radeonPageFlip(dPriv
);
596 radeonCopyBuffer(dPriv
, NULL
);
599 psp
= dPriv
->driScreenPriv
;
602 (*psp
->systemTime
->getUST
)( & ust
);
603 if ( missed_target
) {
604 rfb
->swap_missed_count
++;
605 rfb
->swap_missed_ust
= ust
- rfb
->swap_ust
;
609 radeon
->hw
.all_dirty
= GL_TRUE
;
612 /* XXX this shouldn't be an error but we can't handle it for now */
613 _mesa_problem(NULL
, "%s: drawable has no context!",
618 void radeonCopySubBuffer(__DRIdrawable
* dPriv
,
619 int x
, int y
, int w
, int h
)
621 if (dPriv
->driContextPriv
&& dPriv
->driContextPriv
->driverPrivate
) {
622 radeonContextPtr radeon
;
625 radeon
= (radeonContextPtr
) dPriv
->driContextPriv
->driverPrivate
;
628 if (ctx
->Visual
.doubleBufferMode
) {
629 drm_clip_rect_t rect
;
630 rect
.x1
= x
+ dPriv
->x
;
631 rect
.y1
= (dPriv
->h
- y
- h
) + dPriv
->y
;
632 rect
.x2
= rect
.x1
+ w
;
633 rect
.y2
= rect
.y1
+ h
;
634 _mesa_notifySwapBuffers(ctx
); /* flush pending rendering comands */
635 radeonCopyBuffer(dPriv
, &rect
);
638 /* XXX this shouldn't be an error but we can't handle it for now */
639 _mesa_problem(NULL
, "%s: drawable has no context!",
645 * Check if we're about to draw into the front color buffer.
646 * If so, set the intel->front_buffer_dirty field to true.
649 radeon_check_front_buffer_rendering(GLcontext
*ctx
)
651 radeonContextPtr radeon
= RADEON_CONTEXT(ctx
);
652 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
655 /* drawing to window system buffer */
656 if (fb
->_NumColorDrawBuffers
> 0) {
657 if (fb
->_ColorDrawBufferIndexes
[0] == BUFFER_FRONT_LEFT
) {
658 radeon
->front_buffer_dirty
= GL_TRUE
;
665 void radeon_draw_buffer(GLcontext
*ctx
, struct gl_framebuffer
*fb
)
667 radeonContextPtr radeon
= RADEON_CONTEXT(ctx
);
668 struct radeon_renderbuffer
*rrbDepth
= NULL
, *rrbStencil
= NULL
,
674 /* this can happen during the initial context initialization */
678 /* radeons only handle 1 color draw so far */
679 if (fb
->_NumColorDrawBuffers
!= 1) {
680 radeon
->vtbl
.fallback(ctx
, RADEON_FALLBACK_DRAW_BUFFER
, GL_TRUE
);
684 /* Do this here, note core Mesa, since this function is called from
685 * many places within the driver.
687 if (ctx
->NewState
& (_NEW_BUFFERS
| _NEW_COLOR
| _NEW_PIXEL
)) {
688 /* this updates the DrawBuffer->_NumColorDrawBuffers fields, etc */
689 _mesa_update_framebuffer(ctx
);
690 /* this updates the DrawBuffer's Width/Height if it's a FBO */
691 _mesa_update_draw_buffer_bounds(ctx
);
694 if (fb
->_Status
!= GL_FRAMEBUFFER_COMPLETE_EXT
) {
695 /* this may occur when we're called by glBindFrameBuffer() during
696 * the process of someone setting up renderbuffers, etc.
698 /*_mesa_debug(ctx, "DrawBuffer: incomplete user FBO\n");*/
703 ;/* do something depthy/stencily TODO */
708 if (fb
->_ColorDrawBufferIndexes
[0] == BUFFER_FRONT_LEFT
) {
709 rrbColor
= radeon_renderbuffer(fb
->Attachment
[BUFFER_FRONT_LEFT
].Renderbuffer
);
710 radeon
->front_cliprects
= GL_TRUE
;
711 radeon
->front_buffer_dirty
= GL_TRUE
;
713 rrbColor
= radeon_renderbuffer(fb
->Attachment
[BUFFER_BACK_LEFT
].Renderbuffer
);
714 radeon
->front_cliprects
= GL_FALSE
;
717 /* user FBO in theory */
718 struct radeon_renderbuffer
*rrb
;
719 rrb
= radeon_renderbuffer(fb
->_ColorDrawBuffers
[0]);
721 offset
= rrb
->draw_offset
;
724 radeon
->constant_cliprect
= GL_TRUE
;
727 if (rrbColor
== NULL
)
728 radeon
->vtbl
.fallback(ctx
, RADEON_FALLBACK_DRAW_BUFFER
, GL_TRUE
);
730 radeon
->vtbl
.fallback(ctx
, RADEON_FALLBACK_DRAW_BUFFER
, GL_FALSE
);
733 if (fb
->_DepthBuffer
&& fb
->_DepthBuffer
->Wrapped
) {
734 rrbDepth
= radeon_renderbuffer(fb
->_DepthBuffer
->Wrapped
);
735 if (rrbDepth
&& rrbDepth
->bo
) {
736 radeon
->vtbl
.fallback(ctx
, RADEON_FALLBACK_DEPTH_BUFFER
, GL_FALSE
);
738 radeon
->vtbl
.fallback(ctx
, RADEON_FALLBACK_DEPTH_BUFFER
, GL_TRUE
);
741 radeon
->vtbl
.fallback(ctx
, RADEON_FALLBACK_DEPTH_BUFFER
, GL_FALSE
);
745 if (fb
->_StencilBuffer
&& fb
->_StencilBuffer
->Wrapped
) {
746 rrbStencil
= radeon_renderbuffer(fb
->_StencilBuffer
->Wrapped
);
747 if (rrbStencil
&& rrbStencil
->bo
) {
748 radeon
->vtbl
.fallback(ctx
, RADEON_FALLBACK_STENCIL_BUFFER
, GL_FALSE
);
749 /* need to re-compute stencil hw state */
751 rrbDepth
= rrbStencil
;
753 radeon
->vtbl
.fallback(ctx
, RADEON_FALLBACK_STENCIL_BUFFER
, GL_TRUE
);
756 radeon
->vtbl
.fallback(ctx
, RADEON_FALLBACK_STENCIL_BUFFER
, GL_FALSE
);
757 if (ctx
->Driver
.Enable
!= NULL
)
758 ctx
->Driver
.Enable(ctx
, GL_STENCIL_TEST
, ctx
->Stencil
.Enabled
);
760 ctx
->NewState
|= _NEW_STENCIL
;
763 /* Update culling direction which changes depending on the
764 * orientation of the buffer:
766 if (ctx
->Driver
.FrontFace
)
767 ctx
->Driver
.FrontFace(ctx
, ctx
->Polygon
.FrontFace
);
769 ctx
->NewState
|= _NEW_POLYGON
;
772 * Update depth test state
774 if (ctx
->Driver
.Enable
) {
775 ctx
->Driver
.Enable(ctx
, GL_DEPTH_TEST
,
776 (ctx
->Depth
.Test
&& fb
->Visual
.depthBits
> 0));
777 /* Need to update the derived ctx->Stencil._Enabled first */
778 ctx
->Driver
.Enable(ctx
, GL_STENCIL_TEST
,
779 (ctx
->Stencil
.Enabled
&& fb
->Visual
.stencilBits
> 0));
781 ctx
->NewState
|= (_NEW_DEPTH
| _NEW_STENCIL
);
784 _mesa_reference_renderbuffer(&radeon
->state
.depth
.rb
, &rrbDepth
->base
);
785 _mesa_reference_renderbuffer(&radeon
->state
.color
.rb
, &rrbColor
->base
);
786 radeon
->state
.color
.draw_offset
= offset
;
789 /* update viewport since it depends on window size */
790 if (ctx
->Driver
.Viewport
) {
791 ctx
->Driver
.Viewport(ctx
, ctx
->Viewport
.X
, ctx
->Viewport
.Y
,
792 ctx
->Viewport
.Width
, ctx
->Viewport
.Height
);
797 ctx
->NewState
|= _NEW_VIEWPORT
;
799 /* Set state we know depends on drawable parameters:
801 radeonUpdateScissor(ctx
);
802 radeon
->NewGLState
|= _NEW_SCISSOR
;
804 if (ctx
->Driver
.DepthRange
)
805 ctx
->Driver
.DepthRange(ctx
,
809 /* Update culling direction which changes depending on the
810 * orientation of the buffer:
812 if (ctx
->Driver
.FrontFace
)
813 ctx
->Driver
.FrontFace(ctx
, ctx
->Polygon
.FrontFace
);
815 ctx
->NewState
|= _NEW_POLYGON
;
819 * Called via glDrawBuffer.
821 void radeonDrawBuffer( GLcontext
*ctx
, GLenum mode
)
823 if (RADEON_DEBUG
& RADEON_DRI
)
824 fprintf(stderr
, "%s %s\n", __FUNCTION__
,
825 _mesa_lookup_enum_by_nr( mode
));
827 if (ctx
->DrawBuffer
->Name
== 0) {
828 radeonContextPtr radeon
= RADEON_CONTEXT(ctx
);
830 const GLboolean was_front_buffer_rendering
=
831 radeon
->is_front_buffer_rendering
;
833 radeon
->is_front_buffer_rendering
= (mode
== GL_FRONT_LEFT
) ||
836 /* If we weren't front-buffer rendering before but we are now, make sure
837 * that the front-buffer has actually been allocated.
839 if (!was_front_buffer_rendering
&& radeon
->is_front_buffer_rendering
) {
840 radeon_update_renderbuffers(radeon
->dri
.context
,
841 radeon
->dri
.context
->driDrawablePriv
, GL_FALSE
);
845 radeon_draw_buffer(ctx
, ctx
->DrawBuffer
);
848 void radeonReadBuffer( GLcontext
*ctx
, GLenum mode
)
850 if ((ctx
->DrawBuffer
!= NULL
) && (ctx
->DrawBuffer
->Name
== 0)) {
851 struct radeon_context
*const rmesa
= RADEON_CONTEXT(ctx
);
852 const GLboolean was_front_buffer_reading
= rmesa
->is_front_buffer_reading
;
853 rmesa
->is_front_buffer_reading
= (mode
== GL_FRONT_LEFT
)
854 || (mode
== GL_FRONT
);
856 if (!was_front_buffer_reading
&& rmesa
->is_front_buffer_reading
) {
857 radeon_update_renderbuffers(rmesa
->dri
.context
,
858 rmesa
->dri
.context
->driReadablePriv
, GL_FALSE
);
861 /* nothing, until we implement h/w glRead/CopyPixels or CopyTexImage */
862 if (ctx
->ReadBuffer
== ctx
->DrawBuffer
) {
863 /* This will update FBO completeness status.
864 * A framebuffer will be incomplete if the GL_READ_BUFFER setting
865 * refers to a missing renderbuffer. Calling glReadBuffer can set
866 * that straight and can make the drawing buffer complete.
868 radeon_draw_buffer(ctx
, ctx
->DrawBuffer
);
873 /* Turn on/off page flipping according to the flags in the sarea:
875 void radeonUpdatePageFlipping(radeonContextPtr radeon
)
877 struct radeon_framebuffer
*rfb
= radeon_get_drawable(radeon
)->driverPrivate
;
879 rfb
->pf_active
= radeon
->sarea
->pfState
;
880 rfb
->pf_current_page
= radeon
->sarea
->pfCurrentPage
;
881 rfb
->pf_num_pages
= 2;
882 radeon_flip_renderbuffers(rfb
);
883 radeon_draw_buffer(radeon
->glCtx
, radeon
->glCtx
->DrawBuffer
);
886 void radeon_window_moved(radeonContextPtr radeon
)
888 /* Cliprects has to be updated before doing anything else */
889 radeonSetCliprects(radeon
);
890 if (!radeon
->radeonScreen
->driScreen
->dri2
.enabled
) {
891 radeonUpdatePageFlipping(radeon
);
895 void radeon_viewport(GLcontext
*ctx
, GLint x
, GLint y
, GLsizei width
, GLsizei height
)
897 radeonContextPtr radeon
= RADEON_CONTEXT(ctx
);
898 __DRIcontext
*driContext
= radeon
->dri
.context
;
899 void (*old_viewport
)(GLcontext
*ctx
, GLint x
, GLint y
,
900 GLsizei w
, GLsizei h
);
902 if (!driContext
->driScreenPriv
->dri2
.enabled
)
905 if (!radeon
->meta
.internal_viewport_call
&& ctx
->DrawBuffer
->Name
== 0) {
906 if (radeon
->is_front_buffer_rendering
) {
907 ctx
->Driver
.Flush(ctx
);
909 radeon_update_renderbuffers(driContext
, driContext
->driDrawablePriv
, GL_FALSE
);
910 if (driContext
->driDrawablePriv
!= driContext
->driReadablePriv
)
911 radeon_update_renderbuffers(driContext
, driContext
->driReadablePriv
, GL_FALSE
);
914 old_viewport
= ctx
->Driver
.Viewport
;
915 ctx
->Driver
.Viewport
= NULL
;
916 radeon_window_moved(radeon
);
917 radeon_draw_buffer(ctx
, radeon
->glCtx
->DrawBuffer
);
918 ctx
->Driver
.Viewport
= old_viewport
;
921 static void radeon_print_state_atom_prekmm(radeonContextPtr radeon
, struct radeon_state_atom
*state
)
924 int dwords
= (*state
->check
) (radeon
->glCtx
, state
);
925 drm_r300_cmd_header_t cmd
;
927 fprintf(stderr
, " emit %s %d/%d\n", state
->name
, dwords
, state
->cmd_size
);
929 if (radeon_is_debug_enabled(RADEON_STATE
, RADEON_TRACE
)) {
930 if (dwords
> state
->cmd_size
)
931 dwords
= state
->cmd_size
;
933 for (i
= 0; i
< dwords
;) {
934 cmd
= *((drm_r300_cmd_header_t
*) &state
->cmd
[i
]);
935 reg
= (cmd
.packet0
.reghi
<< 8) | cmd
.packet0
.reglo
;
936 fprintf(stderr
, " %s[%d]: cmdpacket0 (first reg=0x%04x, count=%d)\n",
937 state
->name
, i
, reg
, cmd
.packet0
.count
);
939 for (j
= 0; j
< cmd
.packet0
.count
&& i
< dwords
; j
++) {
940 fprintf(stderr
, " %s[%d]: 0x%04x = %08x\n",
941 state
->name
, i
, reg
, state
->cmd
[i
]);
949 static void radeon_print_state_atom(radeonContextPtr radeon
, struct radeon_state_atom
*state
)
951 int i
, j
, reg
, count
;
954 if (!radeon_is_debug_enabled(RADEON_STATE
, RADEON_VERBOSE
) )
957 if (!radeon
->radeonScreen
->kernel_mm
) {
958 radeon_print_state_atom_prekmm(radeon
, state
);
962 dwords
= (*state
->check
) (radeon
->glCtx
, state
);
964 fprintf(stderr
, " emit %s %d/%d\n", state
->name
, dwords
, state
->cmd_size
);
966 if (radeon_is_debug_enabled(RADEON_STATE
, RADEON_TRACE
)) {
967 if (dwords
> state
->cmd_size
)
968 dwords
= state
->cmd_size
;
969 for (i
= 0; i
< dwords
;) {
970 packet0
= state
->cmd
[i
];
971 reg
= (packet0
& 0x1FFF) << 2;
972 count
= ((packet0
& 0x3FFF0000) >> 16) + 1;
973 fprintf(stderr
, " %s[%d]: cmdpacket0 (first reg=0x%04x, count=%d)\n",
974 state
->name
, i
, reg
, count
);
976 for (j
= 0; j
< count
&& i
< dwords
; j
++) {
977 fprintf(stderr
, " %s[%d]: 0x%04x = %08x\n",
978 state
->name
, i
, reg
, state
->cmd
[i
]);
987 * Count total size for next state emit.
989 GLuint
radeonCountStateEmitSize(radeonContextPtr radeon
)
991 struct radeon_state_atom
*atom
;
993 /* check if we are going to emit full state */
995 if (radeon
->cmdbuf
.cs
->cdw
&& !radeon
->hw
.all_dirty
) {
996 if (!radeon
->hw
.is_dirty
)
998 foreach(atom
, &radeon
->hw
.atomlist
) {
1000 const GLuint atom_size
= atom
->check(radeon
->glCtx
, atom
);
1001 dwords
+= atom_size
;
1002 if (RADEON_CMDBUF
&& atom_size
) {
1003 radeon_print_state_atom(radeon
, atom
);
1008 foreach(atom
, &radeon
->hw
.atomlist
) {
1009 const GLuint atom_size
= atom
->check(radeon
->glCtx
, atom
);
1010 dwords
+= atom_size
;
1011 if (RADEON_CMDBUF
&& atom_size
) {
1012 radeon_print_state_atom(radeon
, atom
);
1018 radeon_print(RADEON_STATE
, RADEON_NORMAL
, "%s %u\n", __func__
, dwords
);
1022 static INLINE
void radeon_emit_atom(radeonContextPtr radeon
, struct radeon_state_atom
*atom
)
1024 BATCH_LOCALS(radeon
);
1027 dwords
= (*atom
->check
) (radeon
->glCtx
, atom
);
1030 radeon_print_state_atom(radeon
, atom
);
1033 (*atom
->emit
)(radeon
->glCtx
, atom
);
1035 BEGIN_BATCH_NO_AUTOSTATE(dwords
);
1036 OUT_BATCH_TABLE(atom
->cmd
, dwords
);
1039 atom
->dirty
= GL_FALSE
;
1042 radeon_print(RADEON_STATE
, RADEON_VERBOSE
, " skip state %s\n", atom
->name
);
1047 static INLINE
void radeonEmitAtoms(radeonContextPtr radeon
, GLboolean emitAll
)
1049 struct radeon_state_atom
*atom
;
1051 if (radeon
->vtbl
.pre_emit_atoms
)
1052 radeon
->vtbl
.pre_emit_atoms(radeon
);
1054 /* Emit actual atoms */
1055 if (radeon
->hw
.all_dirty
|| emitAll
) {
1056 foreach(atom
, &radeon
->hw
.atomlist
)
1057 radeon_emit_atom( radeon
, atom
);
1059 foreach(atom
, &radeon
->hw
.atomlist
) {
1061 radeon_emit_atom( radeon
, atom
);
1068 static GLboolean
radeon_revalidate_bos(GLcontext
*ctx
)
1070 radeonContextPtr radeon
= RADEON_CONTEXT(ctx
);
1073 ret
= radeon_cs_space_check(radeon
->cmdbuf
.cs
);
1074 if (ret
== RADEON_CS_SPACE_FLUSH
)
1079 void radeonEmitState(radeonContextPtr radeon
)
1081 radeon_print(RADEON_STATE
, RADEON_NORMAL
, "%s\n", __FUNCTION__
);
1083 if (radeon
->vtbl
.pre_emit_state
)
1084 radeon
->vtbl
.pre_emit_state(radeon
);
1086 /* this code used to return here but now it emits zbs */
1087 if (radeon
->cmdbuf
.cs
->cdw
&& !radeon
->hw
.is_dirty
&& !radeon
->hw
.all_dirty
)
1090 if (!radeon
->cmdbuf
.cs
->cdw
) {
1091 if (RADEON_DEBUG
& RADEON_STATE
)
1092 fprintf(stderr
, "Begin reemit state\n");
1094 radeonEmitAtoms(radeon
, GL_TRUE
);
1097 if (RADEON_DEBUG
& RADEON_STATE
)
1098 fprintf(stderr
, "Begin dirty state\n");
1100 radeonEmitAtoms(radeon
, GL_FALSE
);
1103 radeon
->hw
.is_dirty
= GL_FALSE
;
1104 radeon
->hw
.all_dirty
= GL_FALSE
;
1108 void radeonFlush(GLcontext
*ctx
)
1110 radeonContextPtr radeon
= RADEON_CONTEXT(ctx
);
1111 if (RADEON_DEBUG
& RADEON_IOCTL
)
1112 fprintf(stderr
, "%s %d\n", __FUNCTION__
, radeon
->cmdbuf
.cs
->cdw
);
1114 /* okay if we have no cmds in the buffer &&
1115 we have no DMA flush &&
1116 we have no DMA buffer allocated.
1117 then no point flushing anything at all.
1119 if (!radeon
->dma
.flush
&& !radeon
->cmdbuf
.cs
->cdw
&& is_empty_list(&radeon
->dma
.reserved
))
1122 if (radeon
->dma
.flush
)
1123 radeon
->dma
.flush( ctx
);
1125 if (radeon
->cmdbuf
.cs
->cdw
)
1126 rcommonFlushCmdBuf(radeon
, __FUNCTION__
);
1129 if ((ctx
->DrawBuffer
->Name
== 0) && radeon
->front_buffer_dirty
) {
1130 __DRIscreen
*const screen
= radeon
->radeonScreen
->driScreen
;
1132 if (screen
->dri2
.loader
&& (screen
->dri2
.loader
->base
.version
>= 2)
1133 && (screen
->dri2
.loader
->flushFrontBuffer
!= NULL
)) {
1134 __DRIdrawable
* drawable
= radeon_get_drawable(radeon
);
1135 (*screen
->dri2
.loader
->flushFrontBuffer
)(drawable
, drawable
->loaderPrivate
);
1137 /* Only clear the dirty bit if front-buffer rendering is no longer
1138 * enabled. This is done so that the dirty bit can only be set in
1139 * glDrawBuffer. Otherwise the dirty bit would have to be set at
1140 * each of N places that do rendering. This has worse performances,
1141 * but it is much easier to get correct.
1143 if (!radeon
->is_front_buffer_rendering
) {
1144 radeon
->front_buffer_dirty
= GL_FALSE
;
1150 /* Make sure all commands have been sent to the hardware and have
1151 * completed processing.
1153 void radeonFinish(GLcontext
* ctx
)
1155 radeonContextPtr radeon
= RADEON_CONTEXT(ctx
);
1156 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
1159 if (ctx
->Driver
.Flush
)
1160 ctx
->Driver
.Flush(ctx
); /* +r6/r7 */
1162 if (radeon
->radeonScreen
->kernel_mm
) {
1163 for (i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
1164 struct radeon_renderbuffer
*rrb
;
1165 rrb
= radeon_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
1167 radeon_bo_wait(rrb
->bo
);
1170 struct radeon_renderbuffer
*rrb
;
1171 rrb
= radeon_get_depthbuffer(radeon
);
1173 radeon_bo_wait(rrb
->bo
);
1175 } else if (radeon
->do_irqs
) {
1176 LOCK_HARDWARE(radeon
);
1177 radeonEmitIrqLocked(radeon
);
1178 UNLOCK_HARDWARE(radeon
);
1179 radeonWaitIrq(radeon
);
1181 radeonWaitForIdle(radeon
);
1187 * Send the current command buffer via ioctl to the hardware.
1189 int rcommonFlushCmdBufLocked(radeonContextPtr rmesa
, const char *caller
)
1193 if (rmesa
->cmdbuf
.flushing
) {
1194 fprintf(stderr
, "Recursive call into r300FlushCmdBufLocked!\n");
1197 rmesa
->cmdbuf
.flushing
= 1;
1199 if (RADEON_DEBUG
& RADEON_IOCTL
) {
1200 fprintf(stderr
, "%s from %s - %i cliprects\n",
1201 __FUNCTION__
, caller
, rmesa
->numClipRects
);
1204 radeonEmitQueryEnd(rmesa
->glCtx
);
1206 if (rmesa
->cmdbuf
.cs
->cdw
) {
1207 ret
= radeon_cs_emit(rmesa
->cmdbuf
.cs
);
1208 rmesa
->hw
.all_dirty
= GL_TRUE
;
1210 radeon_cs_erase(rmesa
->cmdbuf
.cs
);
1211 rmesa
->cmdbuf
.flushing
= 0;
1213 if (radeon_revalidate_bos(rmesa
->glCtx
) == GL_FALSE
) {
1214 fprintf(stderr
,"failed to revalidate buffers\n");
1220 int rcommonFlushCmdBuf(radeonContextPtr rmesa
, const char *caller
)
1224 radeonReleaseDmaRegions(rmesa
);
1226 LOCK_HARDWARE(rmesa
);
1227 ret
= rcommonFlushCmdBufLocked(rmesa
, caller
);
1228 UNLOCK_HARDWARE(rmesa
);
1231 fprintf(stderr
, "drmRadeonCmdBuffer: %d. Kernel failed to "
1232 "parse or rejected command stream. See dmesg "
1233 "for more info.\n", ret
);
1241 * Make sure that enough space is available in the command buffer
1242 * by flushing if necessary.
1244 * \param dwords The number of dwords we need to be free on the command buffer
1246 GLboolean
rcommonEnsureCmdBufSpace(radeonContextPtr rmesa
, int dwords
, const char *caller
)
1248 if ((rmesa
->cmdbuf
.cs
->cdw
+ dwords
+ 128) > rmesa
->cmdbuf
.size
1249 || radeon_cs_need_flush(rmesa
->cmdbuf
.cs
)) {
1250 /* If we try to flush empty buffer there is too big rendering operation. */
1251 assert(rmesa
->cmdbuf
.cs
->cdw
);
1252 rcommonFlushCmdBuf(rmesa
, caller
);
1258 void rcommonInitCmdBuf(radeonContextPtr rmesa
)
1261 /* Initialize command buffer */
1262 size
= 256 * driQueryOptioni(&rmesa
->optionCache
,
1263 "command_buffer_size");
1264 if (size
< 2 * rmesa
->hw
.max_state_size
) {
1265 size
= 2 * rmesa
->hw
.max_state_size
+ 65535;
1267 if (size
> 64 * 256)
1270 radeon_print(RADEON_CS
, RADEON_VERBOSE
,
1271 "sizeof(drm_r300_cmd_header_t)=%zd\n", sizeof(drm_r300_cmd_header_t
));
1272 radeon_print(RADEON_CS
, RADEON_VERBOSE
,
1273 "sizeof(drm_radeon_cmd_buffer_t)=%zd\n", sizeof(drm_radeon_cmd_buffer_t
));
1274 radeon_print(RADEON_CS
, RADEON_VERBOSE
,
1275 "Allocating %d bytes command buffer (max state is %d bytes)\n",
1276 size
* 4, rmesa
->hw
.max_state_size
* 4);
1278 if (rmesa
->radeonScreen
->kernel_mm
) {
1279 int fd
= rmesa
->radeonScreen
->driScreen
->fd
;
1280 rmesa
->cmdbuf
.csm
= radeon_cs_manager_gem_ctor(fd
);
1282 rmesa
->cmdbuf
.csm
= radeon_cs_manager_legacy_ctor(rmesa
);
1284 if (rmesa
->cmdbuf
.csm
== NULL
) {
1285 /* FIXME: fatal error */
1288 rmesa
->cmdbuf
.cs
= radeon_cs_create(rmesa
->cmdbuf
.csm
, size
);
1289 assert(rmesa
->cmdbuf
.cs
!= NULL
);
1290 rmesa
->cmdbuf
.size
= size
;
1292 radeon_cs_space_set_flush(rmesa
->cmdbuf
.cs
,
1293 (void (*)(void *))rmesa
->glCtx
->Driver
.Flush
, rmesa
->glCtx
);
1295 if (!rmesa
->radeonScreen
->kernel_mm
) {
1296 radeon_cs_set_limit(rmesa
->cmdbuf
.cs
, RADEON_GEM_DOMAIN_VRAM
, rmesa
->radeonScreen
->texSize
[0]);
1297 radeon_cs_set_limit(rmesa
->cmdbuf
.cs
, RADEON_GEM_DOMAIN_GTT
, rmesa
->radeonScreen
->gartTextures
.size
);
1299 struct drm_radeon_gem_info mminfo
= { 0 };
1301 if (!drmCommandWriteRead(rmesa
->dri
.fd
, DRM_RADEON_GEM_INFO
, &mminfo
, sizeof(mminfo
)))
1303 radeon_cs_set_limit(rmesa
->cmdbuf
.cs
, RADEON_GEM_DOMAIN_VRAM
, mminfo
.vram_visible
);
1304 radeon_cs_set_limit(rmesa
->cmdbuf
.cs
, RADEON_GEM_DOMAIN_GTT
, mminfo
.gart_size
);
1310 * Destroy the command buffer
1312 void rcommonDestroyCmdBuf(radeonContextPtr rmesa
)
1314 radeon_cs_destroy(rmesa
->cmdbuf
.cs
);
1315 if (rmesa
->radeonScreen
->driScreen
->dri2
.enabled
|| rmesa
->radeonScreen
->kernel_mm
) {
1316 radeon_cs_manager_gem_dtor(rmesa
->cmdbuf
.csm
);
1318 radeon_cs_manager_legacy_dtor(rmesa
->cmdbuf
.csm
);
1322 void rcommonBeginBatch(radeonContextPtr rmesa
, int n
,
1325 const char *function
,
1328 if (!rmesa
->cmdbuf
.cs
->cdw
&& dostate
) {
1329 radeon_print(RADEON_STATE
, RADEON_NORMAL
,
1330 "Reemit state after flush (from %s)\n", function
);
1331 radeonEmitState(rmesa
);
1333 radeon_cs_begin(rmesa
->cmdbuf
.cs
, n
, file
, function
, line
);
1335 radeon_print(RADEON_CS
, RADEON_VERBOSE
, "BEGIN_BATCH(%d) at %d, from %s:%i\n",
1336 n
, rmesa
->cmdbuf
.cs
->cdw
, function
, line
);
1340 void radeonUserClear(GLcontext
*ctx
, GLuint mask
)
1342 _mesa_meta_Clear(ctx
, mask
);