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dri: Remove driver date from renderer string
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_common_context.c
1 /**************************************************************************
2
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
5 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
6
7 The Weather Channel (TM) funded Tungsten Graphics to develop the
8 initial release of the Radeon 8500 driver under the XFree86 license.
9 This notice must be preserved.
10
11 All Rights Reserved.
12
13 Permission is hereby granted, free of charge, to any person obtaining
14 a copy of this software and associated documentation files (the
15 "Software"), to deal in the Software without restriction, including
16 without limitation the rights to use, copy, modify, merge, publish,
17 distribute, sublicense, and/or sell copies of the Software, and to
18 permit persons to whom the Software is furnished to do so, subject to
19 the following conditions:
20
21 The above copyright notice and this permission notice (including the
22 next paragraph) shall be included in all copies or substantial
23 portions of the Software.
24
25 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
28 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
29 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
30 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
31 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
32
33 **************************************************************************/
34
35 #include "radeon_common.h"
36 #include "xmlpool.h" /* for symbolic values of enum-type options */
37 #include "utils.h"
38 #include "vblank.h"
39 #include "drirenderbuffer.h"
40 #include "drivers/common/meta.h"
41 #include "main/context.h"
42 #include "main/framebuffer.h"
43 #include "main/renderbuffer.h"
44 #include "main/state.h"
45 #include "main/simple_list.h"
46 #include "swrast/swrast.h"
47 #include "swrast_setup/swrast_setup.h"
48 #include "tnl/tnl.h"
49
50 #ifndef RADEON_DEBUG
51 int RADEON_DEBUG = (0);
52 #endif
53
54
55 static const char* get_chip_family_name(int chip_family)
56 {
57 switch(chip_family) {
58 case CHIP_FAMILY_R100: return "R100";
59 case CHIP_FAMILY_RV100: return "RV100";
60 case CHIP_FAMILY_RS100: return "RS100";
61 case CHIP_FAMILY_RV200: return "RV200";
62 case CHIP_FAMILY_RS200: return "RS200";
63 case CHIP_FAMILY_R200: return "R200";
64 case CHIP_FAMILY_RV250: return "RV250";
65 case CHIP_FAMILY_RS300: return "RS300";
66 case CHIP_FAMILY_RV280: return "RV280";
67 case CHIP_FAMILY_R300: return "R300";
68 case CHIP_FAMILY_R350: return "R350";
69 case CHIP_FAMILY_RV350: return "RV350";
70 case CHIP_FAMILY_RV380: return "RV380";
71 case CHIP_FAMILY_R420: return "R420";
72 case CHIP_FAMILY_RV410: return "RV410";
73 case CHIP_FAMILY_RS400: return "RS400";
74 case CHIP_FAMILY_RS600: return "RS600";
75 case CHIP_FAMILY_RS690: return "RS690";
76 case CHIP_FAMILY_RS740: return "RS740";
77 case CHIP_FAMILY_RV515: return "RV515";
78 case CHIP_FAMILY_R520: return "R520";
79 case CHIP_FAMILY_RV530: return "RV530";
80 case CHIP_FAMILY_R580: return "R580";
81 case CHIP_FAMILY_RV560: return "RV560";
82 case CHIP_FAMILY_RV570: return "RV570";
83 case CHIP_FAMILY_R600: return "R600";
84 case CHIP_FAMILY_RV610: return "RV610";
85 case CHIP_FAMILY_RV630: return "RV630";
86 case CHIP_FAMILY_RV670: return "RV670";
87 case CHIP_FAMILY_RV620: return "RV620";
88 case CHIP_FAMILY_RV635: return "RV635";
89 case CHIP_FAMILY_RS780: return "RS780";
90 case CHIP_FAMILY_RS880: return "RS880";
91 case CHIP_FAMILY_RV770: return "RV770";
92 case CHIP_FAMILY_RV730: return "RV730";
93 case CHIP_FAMILY_RV710: return "RV710";
94 case CHIP_FAMILY_RV740: return "RV740";
95 case CHIP_FAMILY_CEDAR: return "CEDAR";
96 case CHIP_FAMILY_REDWOOD: return "REDWOOD";
97 case CHIP_FAMILY_JUNIPER: return "JUNIPER";
98 case CHIP_FAMILY_CYPRESS: return "CYPRESS";
99 case CHIP_FAMILY_HEMLOCK: return "HEMLOCK";
100 case CHIP_FAMILY_PALM: return "PALM";
101 case CHIP_FAMILY_BARTS: return "BARTS";
102 case CHIP_FAMILY_TURKS: return "TURKS";
103 case CHIP_FAMILY_CAICOS: return "CAICOS";
104 default: return "unknown";
105 }
106 }
107
108
109 /* Return various strings for glGetString().
110 */
111 static const GLubyte *radeonGetString(struct gl_context * ctx, GLenum name)
112 {
113 radeonContextPtr radeon = RADEON_CONTEXT(ctx);
114 static char buffer[128];
115
116 switch (name) {
117 case GL_VENDOR:
118 if (IS_R600_CLASS(radeon->radeonScreen))
119 return (GLubyte *) "Advanced Micro Devices, Inc.";
120 else if (IS_R300_CLASS(radeon->radeonScreen))
121 return (GLubyte *) "DRI R300 Project";
122 else
123 return (GLubyte *) "Tungsten Graphics, Inc.";
124
125 case GL_RENDERER:
126 {
127 unsigned offset;
128 GLuint agp_mode = (radeon->radeonScreen->card_type==RADEON_CARD_PCI) ? 0 :
129 radeon->radeonScreen->AGPMode;
130 const char* chipclass;
131 char hardwarename[32];
132
133 if (IS_R600_CLASS(radeon->radeonScreen))
134 chipclass = "R600";
135 else if (IS_R300_CLASS(radeon->radeonScreen))
136 chipclass = "R300";
137 else if (IS_R200_CLASS(radeon->radeonScreen))
138 chipclass = "R200";
139 else
140 chipclass = "R100";
141
142 sprintf(hardwarename, "%s (%s %04X)",
143 chipclass,
144 get_chip_family_name(radeon->radeonScreen->chip_family),
145 radeon->radeonScreen->device_id);
146
147 offset = driGetRendererString(buffer, hardwarename, agp_mode);
148
149 if (IS_R600_CLASS(radeon->radeonScreen)) {
150 sprintf(&buffer[offset], " TCL");
151 } else if (IS_R300_CLASS(radeon->radeonScreen)) {
152 sprintf(&buffer[offset], " %sTCL",
153 (radeon->radeonScreen->chip_flags & RADEON_CHIPSET_TCL)
154 ? "" : "NO-");
155 } else {
156 sprintf(&buffer[offset], " %sTCL",
157 !(radeon->TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE)
158 ? "" : "NO-");
159 }
160
161 if (radeon->radeonScreen->driScreen->dri2.enabled)
162 strcat(buffer, " DRI2");
163
164 return (GLubyte *) buffer;
165 }
166
167 default:
168 return NULL;
169 }
170 }
171
172 /* Initialize the driver's misc functions.
173 */
174 static void radeonInitDriverFuncs(struct dd_function_table *functions)
175 {
176 functions->GetString = radeonGetString;
177 }
178
179 /**
180 * Create and initialize all common fields of the context,
181 * including the Mesa context itself.
182 */
183 GLboolean radeonInitContext(radeonContextPtr radeon,
184 struct dd_function_table* functions,
185 const struct gl_config * glVisual,
186 __DRIcontext * driContextPriv,
187 void *sharedContextPrivate)
188 {
189 __DRIscreen *sPriv = driContextPriv->driScreenPriv;
190 radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
191 struct gl_context* ctx;
192 struct gl_context* shareCtx;
193 int fthrottle_mode;
194
195 /* Fill in additional standard functions. */
196 radeonInitDriverFuncs(functions);
197
198 radeon->radeonScreen = screen;
199 /* Allocate and initialize the Mesa context */
200 if (sharedContextPrivate)
201 shareCtx = ((radeonContextPtr)sharedContextPrivate)->glCtx;
202 else
203 shareCtx = NULL;
204 radeon->glCtx = _mesa_create_context(API_OPENGL, glVisual, shareCtx,
205 functions, (void *)radeon);
206 if (!radeon->glCtx)
207 return GL_FALSE;
208
209 ctx = radeon->glCtx;
210 driContextPriv->driverPrivate = radeon;
211
212 _mesa_meta_init(ctx);
213
214 /* DRI fields */
215 radeon->dri.context = driContextPriv;
216 radeon->dri.screen = sPriv;
217 radeon->dri.hwContext = driContextPriv->hHWContext;
218 radeon->dri.hwLock = &sPriv->pSAREA->lock;
219 radeon->dri.hwLockCount = 0;
220 radeon->dri.fd = sPriv->fd;
221 radeon->dri.drmMinor = sPriv->drm_version.minor;
222
223 radeon->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA +
224 screen->sarea_priv_offset);
225
226 /* Setup IRQs */
227 fthrottle_mode = driQueryOptioni(&radeon->optionCache, "fthrottle_mode");
228 radeon->iw.irq_seq = -1;
229 radeon->irqsEmitted = 0;
230 radeon->do_irqs = (fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS &&
231 radeon->radeonScreen->irq);
232
233 radeon->do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
234
235 if (!radeon->do_irqs)
236 fprintf(stderr,
237 "IRQ's not enabled, falling back to %s: %d %d\n",
238 radeon->do_usleeps ? "usleeps" : "busy waits",
239 fthrottle_mode, radeon->radeonScreen->irq);
240
241 radeon->texture_depth = driQueryOptioni (&radeon->optionCache,
242 "texture_depth");
243 if (radeon->texture_depth == DRI_CONF_TEXTURE_DEPTH_FB)
244 radeon->texture_depth = ( glVisual->rgbBits > 16 ) ?
245 DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16;
246
247 if (IS_R600_CLASS(radeon->radeonScreen)) {
248 radeon->texture_row_align = radeon->radeonScreen->group_bytes;
249 radeon->texture_rect_row_align = radeon->radeonScreen->group_bytes;
250 radeon->texture_compressed_row_align = radeon->radeonScreen->group_bytes;
251 } else if (IS_R200_CLASS(radeon->radeonScreen) ||
252 IS_R100_CLASS(radeon->radeonScreen)) {
253 radeon->texture_row_align = 32;
254 radeon->texture_rect_row_align = 64;
255 radeon->texture_compressed_row_align = 32;
256 } else { /* R300 - not sure this is all correct */
257 int chip_family = radeon->radeonScreen->chip_family;
258 if (chip_family == CHIP_FAMILY_RS600 ||
259 chip_family == CHIP_FAMILY_RS690 ||
260 chip_family == CHIP_FAMILY_RS740)
261 radeon->texture_row_align = 64;
262 else
263 radeon->texture_row_align = 32;
264 radeon->texture_rect_row_align = 64;
265 radeon->texture_compressed_row_align = 32;
266 }
267
268 radeon_init_dma(radeon);
269
270 return GL_TRUE;
271 }
272
273
274
275 /**
276 * Destroy the command buffer and state atoms.
277 */
278 static void radeon_destroy_atom_list(radeonContextPtr radeon)
279 {
280 struct radeon_state_atom *atom;
281
282 foreach(atom, &radeon->hw.atomlist) {
283 FREE(atom->cmd);
284 if (atom->lastcmd)
285 FREE(atom->lastcmd);
286 }
287
288 }
289
290 /**
291 * Cleanup common context fields.
292 * Called by r200DestroyContext/r300DestroyContext
293 */
294 void radeonDestroyContext(__DRIcontext *driContextPriv )
295 {
296 #ifdef RADEON_BO_TRACK
297 FILE *track;
298 #endif
299 GET_CURRENT_CONTEXT(ctx);
300 radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
301 radeonContextPtr current = ctx ? RADEON_CONTEXT(ctx) : NULL;
302
303 assert(radeon);
304
305 _mesa_meta_free(radeon->glCtx);
306
307 if (radeon == current) {
308 _mesa_make_current(NULL, NULL, NULL);
309 }
310
311 radeon_firevertices(radeon);
312 if (!is_empty_list(&radeon->dma.reserved)) {
313 rcommonFlushCmdBuf( radeon, __FUNCTION__ );
314 }
315
316 radeonFreeDmaRegions(radeon);
317 radeonReleaseArrays(radeon->glCtx, ~0);
318 if (radeon->vtbl.free_context)
319 radeon->vtbl.free_context(radeon->glCtx);
320 _swsetup_DestroyContext( radeon->glCtx );
321 _tnl_DestroyContext( radeon->glCtx );
322 _vbo_DestroyContext( radeon->glCtx );
323 _swrast_DestroyContext( radeon->glCtx );
324
325 /* free atom list */
326 /* free the Mesa context */
327 _mesa_destroy_context(radeon->glCtx);
328
329 /* _mesa_destroy_context() might result in calls to functions that
330 * depend on the DriverCtx, so don't set it to NULL before.
331 *
332 * radeon->glCtx->DriverCtx = NULL;
333 */
334 /* free the option cache */
335 driDestroyOptionCache(&radeon->optionCache);
336
337 rcommonDestroyCmdBuf(radeon);
338
339 radeon_destroy_atom_list(radeon);
340
341 if (radeon->state.scissor.pClipRects) {
342 FREE(radeon->state.scissor.pClipRects);
343 radeon->state.scissor.pClipRects = 0;
344 }
345 #ifdef RADEON_BO_TRACK
346 track = fopen("/tmp/tracklog", "w");
347 if (track) {
348 radeon_tracker_print(&radeon->radeonScreen->bom->tracker, track);
349 fclose(track);
350 }
351 #endif
352 FREE(radeon);
353 }
354
355 /* Force the context `c' to be unbound from its buffer.
356 */
357 GLboolean radeonUnbindContext(__DRIcontext * driContextPriv)
358 {
359 radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
360
361 if (RADEON_DEBUG & RADEON_DRI)
362 fprintf(stderr, "%s ctx %p\n", __FUNCTION__,
363 radeon->glCtx);
364
365 /* Unset current context and dispath table */
366 _mesa_make_current(NULL, NULL, NULL);
367
368 return GL_TRUE;
369 }
370
371
372 static void
373 radeon_make_kernel_renderbuffer_current(radeonContextPtr radeon,
374 struct gl_framebuffer *draw)
375 {
376 /* if radeon->fake */
377 struct radeon_renderbuffer *rb;
378
379 if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) {
380 if (!rb->bo) {
381 rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
382 radeon->radeonScreen->frontOffset,
383 0,
384 0,
385 RADEON_GEM_DOMAIN_VRAM,
386 0);
387 }
388 rb->cpp = radeon->radeonScreen->cpp;
389 rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp;
390 }
391 if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) {
392 if (!rb->bo) {
393 rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
394 radeon->radeonScreen->backOffset,
395 0,
396 0,
397 RADEON_GEM_DOMAIN_VRAM,
398 0);
399 }
400 rb->cpp = radeon->radeonScreen->cpp;
401 rb->pitch = radeon->radeonScreen->backPitch * rb->cpp;
402 }
403 if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) {
404 if (!rb->bo) {
405 rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
406 radeon->radeonScreen->depthOffset,
407 0,
408 0,
409 RADEON_GEM_DOMAIN_VRAM,
410 0);
411 }
412 rb->cpp = radeon->radeonScreen->cpp;
413 rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp;
414 }
415 if ((rb = (void *)draw->Attachment[BUFFER_STENCIL].Renderbuffer)) {
416 if (!rb->bo) {
417 rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
418 radeon->radeonScreen->depthOffset,
419 0,
420 0,
421 RADEON_GEM_DOMAIN_VRAM,
422 0);
423 }
424 rb->cpp = radeon->radeonScreen->cpp;
425 rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp;
426 }
427 }
428
429 static void
430 radeon_make_renderbuffer_current(radeonContextPtr radeon,
431 struct gl_framebuffer *draw)
432 {
433 int size = 4096*4096*4;
434 /* if radeon->fake */
435 struct radeon_renderbuffer *rb;
436
437 if (radeon->radeonScreen->kernel_mm) {
438 radeon_make_kernel_renderbuffer_current(radeon, draw);
439 return;
440 }
441
442
443 if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) {
444 if (!rb->bo) {
445 rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
446 radeon->radeonScreen->frontOffset +
447 radeon->radeonScreen->fbLocation,
448 size,
449 4096,
450 RADEON_GEM_DOMAIN_VRAM,
451 0);
452 }
453 rb->cpp = radeon->radeonScreen->cpp;
454 rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp;
455 }
456 if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) {
457 if (!rb->bo) {
458 rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
459 radeon->radeonScreen->backOffset +
460 radeon->radeonScreen->fbLocation,
461 size,
462 4096,
463 RADEON_GEM_DOMAIN_VRAM,
464 0);
465 }
466 rb->cpp = radeon->radeonScreen->cpp;
467 rb->pitch = radeon->radeonScreen->backPitch * rb->cpp;
468 }
469 if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) {
470 if (!rb->bo) {
471 rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
472 radeon->radeonScreen->depthOffset +
473 radeon->radeonScreen->fbLocation,
474 size,
475 4096,
476 RADEON_GEM_DOMAIN_VRAM,
477 0);
478 }
479 rb->cpp = radeon->radeonScreen->cpp;
480 rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp;
481 }
482 if ((rb = (void *)draw->Attachment[BUFFER_STENCIL].Renderbuffer)) {
483 if (!rb->bo) {
484 rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
485 radeon->radeonScreen->depthOffset +
486 radeon->radeonScreen->fbLocation,
487 size,
488 4096,
489 RADEON_GEM_DOMAIN_VRAM,
490 0);
491 }
492 rb->cpp = radeon->radeonScreen->cpp;
493 rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp;
494 }
495 }
496
497 static unsigned
498 radeon_bits_per_pixel(const struct radeon_renderbuffer *rb)
499 {
500 return _mesa_get_format_bytes(rb->base.Format) * 8;
501 }
502
503 /*
504 * Check if drawable has been invalidated by dri2InvalidateDrawable().
505 * Update renderbuffers if so. This prevents a client from accessing
506 * a backbuffer that has a swap pending but not yet completed.
507 *
508 * See intel_prepare_render for equivalent code in intel driver.
509 *
510 */
511 void radeon_prepare_render(radeonContextPtr radeon)
512 {
513 __DRIcontext *driContext = radeon->dri.context;
514 __DRIdrawable *drawable;
515 __DRIscreen *screen;
516 struct radeon_framebuffer *draw;
517
518 screen = driContext->driScreenPriv;
519 if (!screen->dri2.loader)
520 return;
521
522 drawable = driContext->driDrawablePriv;
523 if (drawable->dri2.stamp != driContext->dri2.draw_stamp) {
524 if (drawable->lastStamp != drawable->dri2.stamp)
525 radeon_update_renderbuffers(driContext, drawable, GL_FALSE);
526
527 /* Intel driver does the equivalent of this, no clue if it is needed:*/
528 draw = drawable->driverPrivate;
529 radeon_draw_buffer(radeon->glCtx, radeon->glCtx->DrawBuffer);
530
531 driContext->dri2.draw_stamp = drawable->dri2.stamp;
532 }
533
534 drawable = driContext->driReadablePriv;
535 if (drawable->dri2.stamp != driContext->dri2.read_stamp) {
536 if (drawable->lastStamp != drawable->dri2.stamp)
537 radeon_update_renderbuffers(driContext, drawable, GL_FALSE);
538 driContext->dri2.read_stamp = drawable->dri2.stamp;
539 }
540
541 /* If we're currently rendering to the front buffer, the rendering
542 * that will happen next will probably dirty the front buffer. So
543 * mark it as dirty here.
544 */
545 if (radeon->is_front_buffer_rendering)
546 radeon->front_buffer_dirty = GL_TRUE;
547 }
548
549 void
550 radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable,
551 GLboolean front_only)
552 {
553 unsigned int attachments[10];
554 __DRIbuffer *buffers = NULL;
555 __DRIscreen *screen;
556 struct radeon_renderbuffer *rb;
557 int i, count;
558 struct radeon_framebuffer *draw;
559 radeonContextPtr radeon;
560 char *regname;
561 struct radeon_bo *depth_bo = NULL, *bo;
562
563 if (RADEON_DEBUG & RADEON_DRI)
564 fprintf(stderr, "enter %s, drawable %p\n", __func__, drawable);
565
566 draw = drawable->driverPrivate;
567 screen = context->driScreenPriv;
568 radeon = (radeonContextPtr) context->driverPrivate;
569
570 /* Set this up front, so that in case our buffers get invalidated
571 * while we're getting new buffers, we don't clobber the stamp and
572 * thus ignore the invalidate. */
573 drawable->lastStamp = drawable->dri2.stamp;
574
575 if (screen->dri2.loader
576 && (screen->dri2.loader->base.version > 2)
577 && (screen->dri2.loader->getBuffersWithFormat != NULL)) {
578 struct radeon_renderbuffer *depth_rb;
579 struct radeon_renderbuffer *stencil_rb;
580
581 i = 0;
582 if ((front_only || radeon->is_front_buffer_rendering ||
583 radeon->is_front_buffer_reading ||
584 !draw->color_rb[1])
585 && draw->color_rb[0]) {
586 attachments[i++] = __DRI_BUFFER_FRONT_LEFT;
587 attachments[i++] = radeon_bits_per_pixel(draw->color_rb[0]);
588 }
589
590 if (!front_only) {
591 if (draw->color_rb[1]) {
592 attachments[i++] = __DRI_BUFFER_BACK_LEFT;
593 attachments[i++] = radeon_bits_per_pixel(draw->color_rb[1]);
594 }
595
596 depth_rb = radeon_get_renderbuffer(&draw->base, BUFFER_DEPTH);
597 stencil_rb = radeon_get_renderbuffer(&draw->base, BUFFER_STENCIL);
598
599 if ((depth_rb != NULL) && (stencil_rb != NULL)) {
600 attachments[i++] = __DRI_BUFFER_DEPTH_STENCIL;
601 attachments[i++] = radeon_bits_per_pixel(depth_rb);
602 } else if (depth_rb != NULL) {
603 attachments[i++] = __DRI_BUFFER_DEPTH;
604 attachments[i++] = radeon_bits_per_pixel(depth_rb);
605 } else if (stencil_rb != NULL) {
606 attachments[i++] = __DRI_BUFFER_STENCIL;
607 attachments[i++] = radeon_bits_per_pixel(stencil_rb);
608 }
609 }
610
611 buffers = (*screen->dri2.loader->getBuffersWithFormat)(drawable,
612 &drawable->w,
613 &drawable->h,
614 attachments, i / 2,
615 &count,
616 drawable->loaderPrivate);
617 } else if (screen->dri2.loader) {
618 i = 0;
619 if (draw->color_rb[0])
620 attachments[i++] = __DRI_BUFFER_FRONT_LEFT;
621 if (!front_only) {
622 if (draw->color_rb[1])
623 attachments[i++] = __DRI_BUFFER_BACK_LEFT;
624 if (radeon_get_renderbuffer(&draw->base, BUFFER_DEPTH))
625 attachments[i++] = __DRI_BUFFER_DEPTH;
626 if (radeon_get_renderbuffer(&draw->base, BUFFER_STENCIL))
627 attachments[i++] = __DRI_BUFFER_STENCIL;
628 }
629
630 buffers = (*screen->dri2.loader->getBuffers)(drawable,
631 &drawable->w,
632 &drawable->h,
633 attachments, i,
634 &count,
635 drawable->loaderPrivate);
636 }
637
638 if (buffers == NULL)
639 return;
640
641 /* set one cliprect to cover the whole drawable */
642 drawable->x = 0;
643 drawable->y = 0;
644 drawable->backX = 0;
645 drawable->backY = 0;
646 drawable->numClipRects = 1;
647 drawable->pClipRects[0].x1 = 0;
648 drawable->pClipRects[0].y1 = 0;
649 drawable->pClipRects[0].x2 = drawable->w;
650 drawable->pClipRects[0].y2 = drawable->h;
651 drawable->numBackClipRects = 1;
652 drawable->pBackClipRects[0].x1 = 0;
653 drawable->pBackClipRects[0].y1 = 0;
654 drawable->pBackClipRects[0].x2 = drawable->w;
655 drawable->pBackClipRects[0].y2 = drawable->h;
656 for (i = 0; i < count; i++) {
657 switch (buffers[i].attachment) {
658 case __DRI_BUFFER_FRONT_LEFT:
659 rb = draw->color_rb[0];
660 regname = "dri2 front buffer";
661 break;
662 case __DRI_BUFFER_FAKE_FRONT_LEFT:
663 rb = draw->color_rb[0];
664 regname = "dri2 fake front buffer";
665 break;
666 case __DRI_BUFFER_BACK_LEFT:
667 rb = draw->color_rb[1];
668 regname = "dri2 back buffer";
669 break;
670 case __DRI_BUFFER_DEPTH:
671 rb = radeon_get_renderbuffer(&draw->base, BUFFER_DEPTH);
672 regname = "dri2 depth buffer";
673 break;
674 case __DRI_BUFFER_DEPTH_STENCIL:
675 rb = radeon_get_renderbuffer(&draw->base, BUFFER_DEPTH);
676 regname = "dri2 depth / stencil buffer";
677 break;
678 case __DRI_BUFFER_STENCIL:
679 rb = radeon_get_renderbuffer(&draw->base, BUFFER_STENCIL);
680 regname = "dri2 stencil buffer";
681 break;
682 case __DRI_BUFFER_ACCUM:
683 default:
684 fprintf(stderr,
685 "unhandled buffer attach event, attacment type %d\n",
686 buffers[i].attachment);
687 return;
688 }
689
690 if (rb == NULL)
691 continue;
692
693 if (rb->bo) {
694 uint32_t name = radeon_gem_name_bo(rb->bo);
695 if (name == buffers[i].name)
696 continue;
697 }
698
699 if (RADEON_DEBUG & RADEON_DRI)
700 fprintf(stderr,
701 "attaching buffer %s, %d, at %d, cpp %d, pitch %d\n",
702 regname, buffers[i].name, buffers[i].attachment,
703 buffers[i].cpp, buffers[i].pitch);
704
705 rb->cpp = buffers[i].cpp;
706 rb->pitch = buffers[i].pitch;
707 rb->base.Width = drawable->w;
708 rb->base.Height = drawable->h;
709 rb->has_surface = 0;
710
711 /* r6xx+ tiling */
712 rb->tile_config = radeon->radeonScreen->tile_config;
713 rb->group_bytes = radeon->radeonScreen->group_bytes;
714 rb->num_channels = radeon->radeonScreen->num_channels;
715 rb->num_banks = radeon->radeonScreen->num_banks;
716 rb->r7xx_bank_op = radeon->radeonScreen->r7xx_bank_op;
717
718 if (buffers[i].attachment == __DRI_BUFFER_STENCIL && depth_bo) {
719 if (RADEON_DEBUG & RADEON_DRI)
720 fprintf(stderr, "(reusing depth buffer as stencil)\n");
721 bo = depth_bo;
722 radeon_bo_ref(bo);
723 } else {
724 uint32_t tiling_flags = 0, pitch = 0;
725 int ret;
726
727 bo = radeon_bo_open(radeon->radeonScreen->bom,
728 buffers[i].name,
729 0,
730 0,
731 RADEON_GEM_DOMAIN_VRAM,
732 buffers[i].flags);
733
734 if (bo == NULL) {
735 fprintf(stderr, "failed to attach %s %d\n",
736 regname, buffers[i].name);
737 continue;
738 }
739
740 ret = radeon_bo_get_tiling(bo, &tiling_flags, &pitch);
741 if (tiling_flags & RADEON_TILING_MACRO)
742 bo->flags |= RADEON_BO_FLAGS_MACRO_TILE;
743 if (tiling_flags & RADEON_TILING_MICRO)
744 bo->flags |= RADEON_BO_FLAGS_MICRO_TILE;
745
746 }
747
748 if (buffers[i].attachment == __DRI_BUFFER_DEPTH) {
749 if (draw->base.Visual.depthBits == 16)
750 rb->cpp = 2;
751 depth_bo = bo;
752 }
753
754 radeon_renderbuffer_set_bo(rb, bo);
755 radeon_bo_unref(bo);
756
757 if (buffers[i].attachment == __DRI_BUFFER_DEPTH_STENCIL) {
758 rb = radeon_get_renderbuffer(&draw->base, BUFFER_STENCIL);
759 if (rb != NULL) {
760 struct radeon_bo *stencil_bo = NULL;
761
762 if (rb->bo) {
763 uint32_t name = radeon_gem_name_bo(rb->bo);
764 if (name == buffers[i].name)
765 continue;
766 }
767
768 stencil_bo = bo;
769 radeon_bo_ref(stencil_bo);
770 radeon_renderbuffer_set_bo(rb, stencil_bo);
771 radeon_bo_unref(stencil_bo);
772 }
773 }
774 }
775
776 driUpdateFramebufferSize(radeon->glCtx, drawable);
777 }
778
779 /* Force the context `c' to be the current context and associate with it
780 * buffer `b'.
781 */
782 GLboolean radeonMakeCurrent(__DRIcontext * driContextPriv,
783 __DRIdrawable * driDrawPriv,
784 __DRIdrawable * driReadPriv)
785 {
786 radeonContextPtr radeon;
787 struct radeon_framebuffer *rdrfb;
788 struct gl_framebuffer *drfb, *readfb;
789
790 if (!driContextPriv) {
791 if (RADEON_DEBUG & RADEON_DRI)
792 fprintf(stderr, "%s ctx is null\n", __FUNCTION__);
793 _mesa_make_current(NULL, NULL, NULL);
794 return GL_TRUE;
795 }
796
797 radeon = (radeonContextPtr) driContextPriv->driverPrivate;
798
799 if(driDrawPriv == NULL && driReadPriv == NULL) {
800 drfb = _mesa_create_framebuffer(&radeon->glCtx->Visual);
801 readfb = drfb;
802 }
803 else {
804 drfb = driDrawPriv->driverPrivate;
805 readfb = driReadPriv->driverPrivate;
806 }
807
808 if (driContextPriv->driScreenPriv->dri2.enabled) {
809 if(driDrawPriv)
810 radeon_update_renderbuffers(driContextPriv, driDrawPriv, GL_FALSE);
811 if (driDrawPriv != driReadPriv)
812 radeon_update_renderbuffers(driContextPriv, driReadPriv, GL_FALSE);
813 _mesa_reference_renderbuffer(&radeon->state.color.rb,
814 &(radeon_get_renderbuffer(drfb, BUFFER_BACK_LEFT)->base));
815 _mesa_reference_renderbuffer(&radeon->state.depth.rb,
816 &(radeon_get_renderbuffer(drfb, BUFFER_DEPTH)->base));
817 } else {
818 radeon_make_renderbuffer_current(radeon, drfb);
819 }
820
821 if (RADEON_DEBUG & RADEON_DRI)
822 fprintf(stderr, "%s ctx %p dfb %p rfb %p\n", __FUNCTION__, radeon->glCtx, drfb, readfb);
823
824 if(driDrawPriv)
825 driUpdateFramebufferSize(radeon->glCtx, driDrawPriv);
826 if (driReadPriv != driDrawPriv)
827 driUpdateFramebufferSize(radeon->glCtx, driReadPriv);
828
829 _mesa_make_current(radeon->glCtx, drfb, readfb);
830 if (driDrawPriv == NULL && driReadPriv == NULL)
831 _mesa_reference_framebuffer(&drfb, NULL);
832
833 _mesa_update_state(radeon->glCtx);
834
835 if (radeon->glCtx->DrawBuffer == drfb) {
836 if(driDrawPriv != NULL) {
837 rdrfb = (struct radeon_framebuffer *)drfb;
838 if (driDrawPriv->swap_interval == (unsigned)-1) {
839 int i;
840 driDrawPriv->vblFlags =
841 (radeon->radeonScreen->irq != 0)
842 ? driGetDefaultVBlankFlags(&radeon->
843 optionCache)
844 : VBLANK_FLAG_NO_IRQ;
845
846 driDrawableInitVBlank(driDrawPriv);
847 rdrfb->vbl_waited = driDrawPriv->vblSeq;
848
849 for (i = 0; i < 2; i++) {
850 if (rdrfb->color_rb[i])
851 rdrfb->color_rb[i]->vbl_pending = driDrawPriv->vblSeq;
852 }
853 }
854 radeon_window_moved(radeon);
855 }
856
857 radeon_draw_buffer(radeon->glCtx, drfb);
858 }
859
860
861 if (RADEON_DEBUG & RADEON_DRI)
862 fprintf(stderr, "End %s\n", __FUNCTION__);
863
864 return GL_TRUE;
865 }
866