src/mesa/drivers/dri/radeon/radeon_common_context.c

   1 /**************************************************************************
   2
   3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   4                      VA Linux Systems Inc., Fremont, California.
   5 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   6
   7 The Weather Channel (TM) funded Tungsten Graphics to develop the
   8 initial release of the Radeon 8500 driver under the XFree86 license.
   9 This notice must be preserved.
  10
  11 All Rights Reserved.
  12
  13 Permission is hereby granted, free of charge, to any person obtaining
  14 a copy of this software and associated documentation files (the
  15 "Software"), to deal in the Software without restriction, including
  16 without limitation the rights to use, copy, modify, merge, publish,
  17 distribute, sublicense, and/or sell copies of the Software, and to
  18 permit persons to whom the Software is furnished to do so, subject to
  19 the following conditions:
  20
  21 The above copyright notice and this permission notice (including the
  22 next paragraph) shall be included in all copies or substantial
  23 portions of the Software.
  24
  25 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  28 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  29 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  30 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  31 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  32
  33 **************************************************************************/
  34
  35 #include "radeon_common.h"
  36 #include "xmlpool.h"            /* for symbolic values of enum-type options */
  37 #include "utils.h"
  38 #include "vblank.h"
  39 #include "drirenderbuffer.h"
  40 #include "main/context.h"
  41 #include "main/framebuffer.h"
  42 #include "main/renderbuffer.h"
  43 #include "main/state.h"
  44 #include "main/simple_list.h"
  45 #include "swrast/swrast.h"
  46 #include "swrast_setup/swrast_setup.h"
  47 #include "tnl/tnl.h"
  48
  49 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) /* +r6/r7 */
  50 #include "r600_context.h"
  51 #endif
  52
  53 #define DRIVER_DATE "20090101"
  54
  55 #ifndef RADEON_DEBUG
  56 int RADEON_DEBUG = (0);
  57 #endif
  58
  59
  60 static const char* get_chip_family_name(int chip_family)
  61 {
  62         switch(chip_family) {
  63         case CHIP_FAMILY_R100: return "R100";
  64         case CHIP_FAMILY_RV100: return "RV100";
  65         case CHIP_FAMILY_RS100: return "RS100";
  66         case CHIP_FAMILY_RV200: return "RV200";
  67         case CHIP_FAMILY_RS200: return "RS200";
  68         case CHIP_FAMILY_R200: return "R200";
  69         case CHIP_FAMILY_RV250: return "RV250";
  70         case CHIP_FAMILY_RS300: return "RS300";
  71         case CHIP_FAMILY_RV280: return "RV280";
  72         case CHIP_FAMILY_R300: return "R300";
  73         case CHIP_FAMILY_R350: return "R350";
  74         case CHIP_FAMILY_RV350: return "RV350";
  75         case CHIP_FAMILY_RV380: return "RV380";
  76         case CHIP_FAMILY_R420: return "R420";
  77         case CHIP_FAMILY_RV410: return "RV410";
  78         case CHIP_FAMILY_RS400: return "RS400";
  79         case CHIP_FAMILY_RS600: return "RS600";
  80         case CHIP_FAMILY_RS690: return "RS690";
  81         case CHIP_FAMILY_RS740: return "RS740";
  82         case CHIP_FAMILY_RV515: return "RV515";
  83         case CHIP_FAMILY_R520: return "R520";
  84         case CHIP_FAMILY_RV530: return "RV530";
  85         case CHIP_FAMILY_R580: return "R580";
  86         case CHIP_FAMILY_RV560: return "RV560";
  87         case CHIP_FAMILY_RV570: return "RV570";
  88         case CHIP_FAMILY_R600: return "R600";
  89         case CHIP_FAMILY_RV610: return "RV610";
  90         case CHIP_FAMILY_RV630: return "RV630";
  91         case CHIP_FAMILY_RV670: return "RV670";
  92         case CHIP_FAMILY_RV620: return "RV620";
  93         case CHIP_FAMILY_RV635: return "RV635";
  94         case CHIP_FAMILY_RS780: return "RS780";
  95         case CHIP_FAMILY_RV770: return "RV770";
  96         case CHIP_FAMILY_RV730: return "RV730";
  97         case CHIP_FAMILY_RV710: return "RV710";
  98         case CHIP_FAMILY_RV740: return "RV740";
  99         default: return "unknown";
 100         }
 101 }
 102
 103
 104 /* Return various strings for glGetString().
 105  */
 106 static const GLubyte *radeonGetString(GLcontext * ctx, GLenum name)
 107 {
 108         radeonContextPtr radeon = RADEON_CONTEXT(ctx);
 109         static char buffer[128];
 110
 111         switch (name) {
 112         case GL_VENDOR:
 113                 if (IS_R600_CLASS(radeon->radeonScreen))
 114                         return (GLubyte *) "Advanced Micro Devices, Inc.";
 115                 else if (IS_R300_CLASS(radeon->radeonScreen))
 116                         return (GLubyte *) "DRI R300 Project";
 117                 else
 118                         return (GLubyte *) "Tungsten Graphics, Inc.";
 119
 120         case GL_RENDERER:
 121         {
 122                 unsigned offset;
 123                 GLuint agp_mode = (radeon->radeonScreen->card_type==RADEON_CARD_PCI) ? 0 :
 124                         radeon->radeonScreen->AGPMode;
 125                 const char* chipclass;
 126                 char hardwarename[32];
 127
 128                 if (IS_R600_CLASS(radeon->radeonScreen))
 129                         chipclass = "R600";
 130                 else if (IS_R300_CLASS(radeon->radeonScreen))
 131                         chipclass = "R300";
 132                 else if (IS_R200_CLASS(radeon->radeonScreen))
 133                         chipclass = "R200";
 134                 else
 135                         chipclass = "R100";
 136
 137                 sprintf(hardwarename, "%s (%s %04X)",
 138                         chipclass,
 139                         get_chip_family_name(radeon->radeonScreen->chip_family),
 140                         radeon->radeonScreen->device_id);
 141
 142                 offset = driGetRendererString(buffer, hardwarename, DRIVER_DATE,
 143                                               agp_mode);
 144
 145                 if (IS_R600_CLASS(radeon->radeonScreen)) {
 146                         sprintf(&buffer[offset], " TCL");
 147                 } else if (IS_R300_CLASS(radeon->radeonScreen)) {
 148                         sprintf(&buffer[offset], " %sTCL",
 149                                 (radeon->radeonScreen->chip_flags & RADEON_CHIPSET_TCL)
 150                                 ? "" : "NO-");
 151                 } else {
 152                         sprintf(&buffer[offset], " %sTCL",
 153                                 !(radeon->TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE)
 154                                 ? "" : "NO-");
 155                 }
 156
 157                 if (radeon->radeonScreen->driScreen->dri2.enabled)
 158                         strcat(buffer, " DRI2");
 159
 160                 return (GLubyte *) buffer;
 161         }
 162
 163         default:
 164                 return NULL;
 165         }
 166 }
 167
 168 /* Initialize the driver's misc functions.
 169  */
 170 static void radeonInitDriverFuncs(struct dd_function_table *functions)
 171 {
 172         functions->GetString = radeonGetString;
 173 }
 174
 175 /**
 176  * Create and initialize all common fields of the context,
 177  * including the Mesa context itself.
 178  */
 179 GLboolean radeonInitContext(radeonContextPtr radeon,
 180                             struct dd_function_table* functions,
 181                             const __GLcontextModes * glVisual,
 182                             __DRIcontextPrivate * driContextPriv,
 183                             void *sharedContextPrivate)
 184 {
 185         __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
 186         radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
 187         GLcontext* ctx;
 188         GLcontext* shareCtx;
 189         int fthrottle_mode;
 190
 191         /* Fill in additional standard functions. */
 192         radeonInitDriverFuncs(functions);
 193
 194         radeon->radeonScreen = screen;
 195         /* Allocate and initialize the Mesa context */
 196         if (sharedContextPrivate)
 197                 shareCtx = ((radeonContextPtr)sharedContextPrivate)->glCtx;
 198         else
 199                 shareCtx = NULL;
 200         radeon->glCtx = _mesa_create_context(glVisual, shareCtx,
 201                                             functions, (void *)radeon);
 202         if (!radeon->glCtx)
 203                 return GL_FALSE;
 204
 205         ctx = radeon->glCtx;
 206         driContextPriv->driverPrivate = radeon;
 207
 208         meta_init_metaops(ctx, &radeon->meta);
 209         /* DRI fields */
 210         radeon->dri.context = driContextPriv;
 211         radeon->dri.screen = sPriv;
 212         radeon->dri.hwContext = driContextPriv->hHWContext;
 213         radeon->dri.hwLock = &sPriv->pSAREA->lock;
 214         radeon->dri.hwLockCount = 0;
 215         radeon->dri.fd = sPriv->fd;
 216         radeon->dri.drmMinor = sPriv->drm_version.minor;
 217
 218         radeon->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA +
 219                                                screen->sarea_priv_offset);
 220
 221         /* Setup IRQs */
 222         fthrottle_mode = driQueryOptioni(&radeon->optionCache, "fthrottle_mode");
 223         radeon->iw.irq_seq = -1;
 224         radeon->irqsEmitted = 0;
 225         if (IS_R600_CLASS(radeon->radeonScreen))
 226                 radeon->do_irqs = 0;
 227         else
 228                 radeon->do_irqs = (fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS &&
 229                                    radeon->radeonScreen->irq);
 230
 231         radeon->do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
 232
 233         if (!radeon->do_irqs)
 234                 fprintf(stderr,
 235                         "IRQ's not enabled, falling back to %s: %d %d\n",
 236                         radeon->do_usleeps ? "usleeps" : "busy waits",
 237                         fthrottle_mode, radeon->radeonScreen->irq);
 238
 239         radeon->texture_depth = driQueryOptioni (&radeon->optionCache,
 240                                                 "texture_depth");
 241         if (radeon->texture_depth == DRI_CONF_TEXTURE_DEPTH_FB)
 242                 radeon->texture_depth = ( glVisual->rgbBits > 16 ) ?
 243                 DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16;
 244
 245         if (IS_R600_CLASS(radeon->radeonScreen)) {
 246                 radeon->texture_row_align = 256;
 247                 radeon->texture_rect_row_align = 256;
 248                 radeon->texture_compressed_row_align = 256;
 249         } else if (IS_R200_CLASS(radeon->radeonScreen) ||
 250                    IS_R100_CLASS(radeon->radeonScreen)) {
 251                 radeon->texture_row_align = 32;
 252                 radeon->texture_rect_row_align = 64;
 253                 radeon->texture_compressed_row_align = 32;
 254         } else { /* R300 - not sure this is all correct */
 255                 int chip_family = radeon->radeonScreen->chip_family;
 256                 if (chip_family == CHIP_FAMILY_RS600 ||
 257                     chip_family == CHIP_FAMILY_RS690 ||
 258                     chip_family == CHIP_FAMILY_RS740)
 259                         radeon->texture_row_align = 64;
 260                 else
 261                         radeon->texture_row_align = 32;
 262                 radeon->texture_rect_row_align = 64;
 263                 radeon->texture_compressed_row_align = 64;
 264         }
 265
 266         make_empty_list(&radeon->query.not_flushed_head);
 267         radeon_init_dma(radeon);
 268
 269         return GL_TRUE;
 270 }
 271
 272
 273
 274 /**
 275  * Destroy the command buffer and state atoms.
 276  */
 277 static void radeon_destroy_atom_list(radeonContextPtr radeon)
 278 {
 279         struct radeon_state_atom *atom;
 280
 281         foreach(atom, &radeon->hw.atomlist) {
 282                 FREE(atom->cmd);
 283                 if (atom->lastcmd)
 284                         FREE(atom->lastcmd);
 285         }
 286
 287 }
 288
 289 /**
 290  * Cleanup common context fields.
 291  * Called by r200DestroyContext/r300DestroyContext
 292  */
 293 void radeonDestroyContext(__DRIcontextPrivate *driContextPriv )
 294 {
 295 #ifdef RADEON_BO_TRACK
 296         FILE *track;
 297 #endif
 298         GET_CURRENT_CONTEXT(ctx);
 299         radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
 300         radeonContextPtr current = ctx ? RADEON_CONTEXT(ctx) : NULL;
 301
 302         if (radeon == current) {
 303                 radeon_firevertices(radeon);
 304                 _mesa_make_current(NULL, NULL, NULL);
 305         }
 306
 307         assert(radeon);
 308         if (radeon) {
 309                 if (!is_empty_list(&radeon->dma.reserved)) {
 310                         rcommonFlushCmdBuf( radeon, __FUNCTION__ );
 311                 }
 312
 313                 radeonFreeDmaRegions(radeon);
 314                 radeonReleaseArrays(radeon->glCtx, ~0);
 315                 meta_destroy_metaops(&radeon->meta);
 316                 if (radeon->vtbl.free_context)
 317                         radeon->vtbl.free_context(radeon->glCtx);
 318                 _swsetup_DestroyContext( radeon->glCtx );
 319                 _tnl_DestroyContext( radeon->glCtx );
 320                 _vbo_DestroyContext( radeon->glCtx );
 321                 _swrast_DestroyContext( radeon->glCtx );
 322
 323                 /* free atom list */
 324                 /* free the Mesa context */
 325                 _mesa_destroy_context(radeon->glCtx);
 326
 327                 /* _mesa_destroy_context() might result in calls to functions that
 328                  * depend on the DriverCtx, so don't set it to NULL before.
 329                  *
 330                  * radeon->glCtx->DriverCtx = NULL;
 331                  */
 332                 /* free the option cache */
 333                 driDestroyOptionCache(&radeon->optionCache);
 334
 335                 rcommonDestroyCmdBuf(radeon);
 336
 337                 radeon_destroy_atom_list(radeon);
 338
 339                 if (radeon->state.scissor.pClipRects) {
 340                         FREE(radeon->state.scissor.pClipRects);
 341                         radeon->state.scissor.pClipRects = 0;
 342                 }
 343         }
 344 #ifdef RADEON_BO_TRACK
 345         track = fopen("/tmp/tracklog", "w");
 346         if (track) {
 347                 radeon_tracker_print(&radeon->radeonScreen->bom->tracker, track);
 348                 fclose(track);
 349         }
 350 #endif
 351         FREE(radeon);
 352 }
 353
 354 /* Force the context `c' to be unbound from its buffer.
 355  */
 356 GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv)
 357 {
 358         radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
 359
 360         if (RADEON_DEBUG & DEBUG_DRI)
 361                 fprintf(stderr, "%s ctx %p\n", __FUNCTION__,
 362                         radeon->glCtx);
 363
 364         return GL_TRUE;
 365 }
 366
 367
 368 static void
 369 radeon_make_kernel_renderbuffer_current(radeonContextPtr radeon,
 370                                         struct radeon_framebuffer *draw)
 371 {
 372         /* if radeon->fake */
 373         struct radeon_renderbuffer *rb;
 374
 375         if ((rb = (void *)draw->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) {
 376                 if (!rb->bo) {
 377                         rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
 378                                                 radeon->radeonScreen->frontOffset,
 379                                                 0,
 380                                                 0,
 381                                                 RADEON_GEM_DOMAIN_VRAM,
 382                                                 0);
 383                 }
 384                 rb->cpp = radeon->radeonScreen->cpp;
 385                 rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp;
 386         }
 387         if ((rb = (void *)draw->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer)) {
 388                 if (!rb->bo) {
 389                         rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
 390                                                 radeon->radeonScreen->backOffset,
 391                                                 0,
 392                                                 0,
 393                                                 RADEON_GEM_DOMAIN_VRAM,
 394                                                 0);
 395                 }
 396                 rb->cpp = radeon->radeonScreen->cpp;
 397                 rb->pitch = radeon->radeonScreen->backPitch * rb->cpp;
 398         }
 399         if ((rb = (void *)draw->base.Attachment[BUFFER_DEPTH].Renderbuffer)) {
 400                 if (!rb->bo) {
 401                         rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
 402                                                 radeon->radeonScreen->depthOffset,
 403                                                 0,
 404                                                 0,
 405                                                 RADEON_GEM_DOMAIN_VRAM,
 406                                                 0);
 407                 }
 408                 rb->cpp = radeon->radeonScreen->cpp;
 409                 rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp;
 410         }
 411         if ((rb = (void *)draw->base.Attachment[BUFFER_STENCIL].Renderbuffer)) {
 412                 if (!rb->bo) {
 413                         rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
 414                                                 radeon->radeonScreen->depthOffset,
 415                                                 0,
 416                                                 0,
 417                                                 RADEON_GEM_DOMAIN_VRAM,
 418                                                 0);
 419                 }
 420                 rb->cpp = radeon->radeonScreen->cpp;
 421                 rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp;
 422         }
 423 }
 424
 425 static void
 426 radeon_make_renderbuffer_current(radeonContextPtr radeon,
 427                                  struct radeon_framebuffer *draw)
 428 {
 429         int size = 4096*4096*4;
 430         /* if radeon->fake */
 431         struct radeon_renderbuffer *rb;
 432
 433         if (radeon->radeonScreen->kernel_mm) {
 434                 radeon_make_kernel_renderbuffer_current(radeon, draw);
 435                 return;
 436         }
 437
 438
 439         if ((rb = (void *)draw->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) {
 440                 if (!rb->bo) {
 441                         rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
 442                                                 radeon->radeonScreen->frontOffset +
 443                                                 radeon->radeonScreen->fbLocation,
 444                                                 size,
 445                                                 4096,
 446                                                 RADEON_GEM_DOMAIN_VRAM,
 447                                                 0);
 448                 }
 449                 rb->cpp = radeon->radeonScreen->cpp;
 450                 rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp;
 451         }
 452         if ((rb = (void *)draw->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer)) {
 453                 if (!rb->bo) {
 454                         rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
 455                                                 radeon->radeonScreen->backOffset +
 456                                                 radeon->radeonScreen->fbLocation,
 457                                                 size,
 458                                                 4096,
 459                                                 RADEON_GEM_DOMAIN_VRAM,
 460                                                 0);
 461                 }
 462                 rb->cpp = radeon->radeonScreen->cpp;
 463                 rb->pitch = radeon->radeonScreen->backPitch * rb->cpp;
 464         }
 465         if ((rb = (void *)draw->base.Attachment[BUFFER_DEPTH].Renderbuffer)) {
 466                 if (!rb->bo) {
 467                         rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
 468                                                 radeon->radeonScreen->depthOffset +
 469                                                 radeon->radeonScreen->fbLocation,
 470                                                 size,
 471                                                 4096,
 472                                                 RADEON_GEM_DOMAIN_VRAM,
 473                                                 0);
 474                 }
 475                 rb->cpp = radeon->radeonScreen->cpp;
 476                 rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp;
 477         }
 478         if ((rb = (void *)draw->base.Attachment[BUFFER_STENCIL].Renderbuffer)) {
 479                 if (!rb->bo) {
 480                         rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
 481                                                 radeon->radeonScreen->depthOffset +
 482                                                 radeon->radeonScreen->fbLocation,
 483                                                 size,
 484                                                 4096,
 485                                                 RADEON_GEM_DOMAIN_VRAM,
 486                                                 0);
 487                 }
 488                 rb->cpp = radeon->radeonScreen->cpp;
 489                 rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp;
 490         }
 491 }
 492
 493 static unsigned
 494 radeon_bits_per_pixel(const struct radeon_renderbuffer *rb)
 495 {
 496    switch (rb->base._ActualFormat) {
 497    case GL_RGB5:
 498    case GL_DEPTH_COMPONENT16:
 499       return 16;
 500    case GL_RGB8:
 501    case GL_RGBA8:
 502    case GL_DEPTH_COMPONENT24:
 503    case GL_DEPTH24_STENCIL8_EXT:
 504    case GL_STENCIL_INDEX8_EXT:
 505       return 32;
 506    default:
 507       return 0;
 508    }
 509 }
 510
 511 void
 512 radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
 513 {
 514         unsigned int attachments[10];
 515         __DRIbuffer *buffers = NULL;
 516         __DRIscreen *screen;
 517         struct radeon_renderbuffer *rb;
 518         int i, count;
 519         struct radeon_framebuffer *draw;
 520         radeonContextPtr radeon;
 521         char *regname;
 522         struct radeon_bo *depth_bo = NULL, *bo;
 523
 524         if (RADEON_DEBUG & DEBUG_DRI)
 525             fprintf(stderr, "enter %s, drawable %p\n", __func__, drawable);
 526
 527         draw = drawable->driverPrivate;
 528         screen = context->driScreenPriv;
 529         radeon = (radeonContextPtr) context->driverPrivate;
 530
 531         if (screen->dri2.loader
 532            && (screen->dri2.loader->base.version > 2)
 533            && (screen->dri2.loader->getBuffersWithFormat != NULL)) {
 534                 struct radeon_renderbuffer *depth_rb;
 535                 struct radeon_renderbuffer *stencil_rb;
 536
 537                 i = 0;
 538                 if ((radeon->is_front_buffer_rendering ||
 539                      radeon->is_front_buffer_reading ||
 540                      !draw->color_rb[1])
 541                     && draw->color_rb[0]) {
 542                         attachments[i++] = __DRI_BUFFER_FRONT_LEFT;
 543                         attachments[i++] = radeon_bits_per_pixel(draw->color_rb[0]);
 544                 }
 545
 546                 if (draw->color_rb[1]) {
 547                         attachments[i++] = __DRI_BUFFER_BACK_LEFT;
 548                         attachments[i++] = radeon_bits_per_pixel(draw->color_rb[1]);
 549                 }
 550
 551                 depth_rb = radeon_get_renderbuffer(&draw->base, BUFFER_DEPTH);
 552                 stencil_rb = radeon_get_renderbuffer(&draw->base, BUFFER_STENCIL);
 553
 554                 if ((depth_rb != NULL) && (stencil_rb != NULL)) {
 555                         attachments[i++] = __DRI_BUFFER_DEPTH_STENCIL;
 556                         attachments[i++] = radeon_bits_per_pixel(depth_rb);
 557                 } else if (depth_rb != NULL) {
 558                         attachments[i++] = __DRI_BUFFER_DEPTH;
 559                         attachments[i++] = radeon_bits_per_pixel(depth_rb);
 560                 } else if (stencil_rb != NULL) {
 561                         attachments[i++] = __DRI_BUFFER_STENCIL;
 562                         attachments[i++] = radeon_bits_per_pixel(stencil_rb);
 563                 }
 564
 565                 buffers = (*screen->dri2.loader->getBuffersWithFormat)(drawable,
 566                                                                 &drawable->w,
 567                                                                 &drawable->h,
 568                                                                 attachments, i / 2,
 569                                                                 &count,
 570                                                                 drawable->loaderPrivate);
 571         } else if (screen->dri2.loader) {
 572                 i = 0;
 573                 if (draw->color_rb[0])
 574                         attachments[i++] = __DRI_BUFFER_FRONT_LEFT;
 575                 if (draw->color_rb[1])
 576                         attachments[i++] = __DRI_BUFFER_BACK_LEFT;
 577                 if (radeon_get_renderbuffer(&draw->base, BUFFER_DEPTH))
 578                         attachments[i++] = __DRI_BUFFER_DEPTH;
 579                 if (radeon_get_renderbuffer(&draw->base, BUFFER_STENCIL))
 580                         attachments[i++] = __DRI_BUFFER_STENCIL;
 581
 582                 buffers = (*screen->dri2.loader->getBuffers)(drawable,
 583                                                                  &drawable->w,
 584                                                                  &drawable->h,
 585                                                                  attachments, i,
 586                                                                  &count,
 587                                                                  drawable->loaderPrivate);
 588         }
 589
 590         if (buffers == NULL)
 591                 return;
 592
 593         /* set one cliprect to cover the whole drawable */
 594         drawable->x = 0;
 595         drawable->y = 0;
 596         drawable->backX = 0;
 597         drawable->backY = 0;
 598         drawable->numClipRects = 1;
 599         drawable->pClipRects[0].x1 = 0;
 600         drawable->pClipRects[0].y1 = 0;
 601         drawable->pClipRects[0].x2 = drawable->w;
 602         drawable->pClipRects[0].y2 = drawable->h;
 603         drawable->numBackClipRects = 1;
 604         drawable->pBackClipRects[0].x1 = 0;
 605         drawable->pBackClipRects[0].y1 = 0;
 606         drawable->pBackClipRects[0].x2 = drawable->w;
 607         drawable->pBackClipRects[0].y2 = drawable->h;
 608         for (i = 0; i < count; i++) {
 609                 switch (buffers[i].attachment) {
 610                 case __DRI_BUFFER_FRONT_LEFT:
 611                         rb = draw->color_rb[0];
 612                         regname = "dri2 front buffer";
 613                         break;
 614                 case __DRI_BUFFER_FAKE_FRONT_LEFT:
 615                         rb = draw->color_rb[0];
 616                         regname = "dri2 fake front buffer";
 617                         break;
 618                 case __DRI_BUFFER_BACK_LEFT:
 619                         rb = draw->color_rb[1];
 620                         regname = "dri2 back buffer";
 621                         break;
 622                 case __DRI_BUFFER_DEPTH:
 623                         rb = radeon_get_renderbuffer(&draw->base, BUFFER_DEPTH);
 624                         regname = "dri2 depth buffer";
 625                         break;
 626                 case __DRI_BUFFER_DEPTH_STENCIL:
 627                         rb = radeon_get_renderbuffer(&draw->base, BUFFER_DEPTH);
 628                         regname = "dri2 depth / stencil buffer";
 629                         break;
 630                 case __DRI_BUFFER_STENCIL:
 631                         rb = radeon_get_renderbuffer(&draw->base, BUFFER_STENCIL);
 632                         regname = "dri2 stencil buffer";
 633                         break;
 634                 case __DRI_BUFFER_ACCUM:
 635                 default:
 636                         fprintf(stderr,
 637                                 "unhandled buffer attach event, attacment type %d\n",
 638                                 buffers[i].attachment);
 639                         return;
 640                 }
 641
 642                 if (rb == NULL)
 643                         continue;
 644
 645                 if (rb->bo) {
 646                         uint32_t name = radeon_gem_name_bo(rb->bo);
 647                         if (name == buffers[i].name)
 648                                 continue;
 649                 }
 650
 651                 if (RADEON_DEBUG & DEBUG_DRI)
 652                         fprintf(stderr,
 653                                 "attaching buffer %s, %d, at %d, cpp %d, pitch %d\n",
 654                                 regname, buffers[i].name, buffers[i].attachment,
 655                                 buffers[i].cpp, buffers[i].pitch);
 656
 657                 rb->cpp = buffers[i].cpp;
 658                 rb->pitch = buffers[i].pitch;
 659                 rb->base.Width = drawable->w;
 660                 rb->base.Height = drawable->h;
 661                 rb->has_surface = 0;
 662
 663                 if (buffers[i].attachment == __DRI_BUFFER_STENCIL && depth_bo) {
 664                         if (RADEON_DEBUG & DEBUG_DRI)
 665                                 fprintf(stderr, "(reusing depth buffer as stencil)\n");
 666                         bo = depth_bo;
 667                         radeon_bo_ref(bo);
 668                 } else {
 669                         uint32_t tiling_flags = 0, pitch = 0;
 670                         int ret;
 671
 672                         bo = radeon_bo_open(radeon->radeonScreen->bom,
 673                                                 buffers[i].name,
 674                                                 0,
 675                                                 0,
 676                                                 RADEON_GEM_DOMAIN_VRAM,
 677                                                 buffers[i].flags);
 678
 679                         if (bo == NULL) {
 680
 681                                 fprintf(stderr, "failed to attach %s %d\n",
 682                                         regname, buffers[i].name);
 683
 684                         }
 685
 686                         ret = radeon_bo_get_tiling(bo, &tiling_flags, &pitch);
 687                         if (tiling_flags & RADEON_TILING_MACRO)
 688                                 bo->flags |= RADEON_BO_FLAGS_MACRO_TILE;
 689                         if (tiling_flags & RADEON_TILING_MICRO)
 690                                 bo->flags |= RADEON_BO_FLAGS_MICRO_TILE;
 691
 692                 }
 693
 694                 if (buffers[i].attachment == __DRI_BUFFER_DEPTH) {
 695                         if (draw->base.Visual.depthBits == 16)
 696                                 rb->cpp = 2;
 697                         depth_bo = bo;
 698                 }
 699
 700                 radeon_renderbuffer_set_bo(rb, bo);
 701                 radeon_bo_unref(bo);
 702
 703                 if (buffers[i].attachment == __DRI_BUFFER_DEPTH_STENCIL) {
 704                         rb = radeon_get_renderbuffer(&draw->base, BUFFER_STENCIL);
 705                         if (rb != NULL) {
 706                                 struct radeon_bo *stencil_bo = NULL;
 707
 708                                 if (rb->bo) {
 709                                         uint32_t name = radeon_gem_name_bo(rb->bo);
 710                                         if (name == buffers[i].name)
 711                                                 continue;
 712                                 }
 713
 714                                 stencil_bo = bo;
 715                                 radeon_bo_ref(stencil_bo);
 716                                 radeon_renderbuffer_set_bo(rb, stencil_bo);
 717                                 radeon_bo_unref(stencil_bo);
 718                         }
 719                 }
 720         }
 721
 722         driUpdateFramebufferSize(radeon->glCtx, drawable);
 723 }
 724
 725 /* Force the context `c' to be the current context and associate with it
 726  * buffer `b'.
 727  */
 728 GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv,
 729                             __DRIdrawablePrivate * driDrawPriv,
 730                             __DRIdrawablePrivate * driReadPriv)
 731 {
 732         radeonContextPtr radeon;
 733         struct radeon_framebuffer *drfb;
 734         struct gl_framebuffer *readfb;
 735
 736         if (!driContextPriv) {
 737                 if (RADEON_DEBUG & DEBUG_DRI)
 738                         fprintf(stderr, "%s ctx is null\n", __FUNCTION__);
 739                 _mesa_make_current(NULL, NULL, NULL);
 740                 return GL_TRUE;
 741         }
 742
 743         radeon = (radeonContextPtr) driContextPriv->driverPrivate;
 744         drfb = driDrawPriv->driverPrivate;
 745         readfb = driReadPriv->driverPrivate;
 746
 747         if (driContextPriv->driScreenPriv->dri2.enabled) {
 748                 radeon_update_renderbuffers(driContextPriv, driDrawPriv);
 749                 if (driDrawPriv != driReadPriv)
 750                         radeon_update_renderbuffers(driContextPriv, driReadPriv);
 751                 _mesa_reference_renderbuffer(&radeon->state.color.rb,
 752                         &(radeon_get_renderbuffer(&drfb->base, BUFFER_BACK_LEFT)->base));
 753                 _mesa_reference_renderbuffer(&radeon->state.depth.rb,
 754                         &(radeon_get_renderbuffer(&drfb->base, BUFFER_DEPTH)->base));
 755         } else {
 756                 radeon_make_renderbuffer_current(radeon, drfb);
 757         }
 758
 759         if (RADEON_DEBUG & DEBUG_DRI)
 760              fprintf(stderr, "%s ctx %p dfb %p rfb %p\n", __FUNCTION__, radeon->glCtx, drfb, readfb);
 761
 762         driUpdateFramebufferSize(radeon->glCtx, driDrawPriv);
 763         if (driReadPriv != driDrawPriv)
 764                 driUpdateFramebufferSize(radeon->glCtx, driReadPriv);
 765
 766         _mesa_make_current(radeon->glCtx, &drfb->base, readfb);
 767
 768         _mesa_update_state(radeon->glCtx);
 769
 770         if (radeon->glCtx->DrawBuffer == &drfb->base) {
 771                 if (driDrawPriv->swap_interval == (unsigned)-1) {
 772                         int i;
 773                         driDrawPriv->vblFlags =
 774                                 (radeon->radeonScreen->irq != 0)
 775                                 ? driGetDefaultVBlankFlags(&radeon->
 776                                                            optionCache)
 777                                 : VBLANK_FLAG_NO_IRQ;
 778
 779                         driDrawableInitVBlank(driDrawPriv);
 780                         drfb->vbl_waited = driDrawPriv->vblSeq;
 781
 782                         for (i = 0; i < 2; i++) {
 783                                 if (drfb->color_rb[i])
 784                                         drfb->color_rb[i]->vbl_pending = driDrawPriv->vblSeq;
 785                         }
 786
 787                 }
 788
 789                 radeon_window_moved(radeon);
 790                 radeon_draw_buffer(radeon->glCtx, &drfb->base);
 791         }
 792
 793
 794         if (RADEON_DEBUG & DEBUG_DRI)
 795                 fprintf(stderr, "End %s\n", __FUNCTION__);
 796
 797         return GL_TRUE;
 798 }
 799