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r300: OQ rework
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_common_context.c
1 /**************************************************************************
2
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
5 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
6
7 The Weather Channel (TM) funded Tungsten Graphics to develop the
8 initial release of the Radeon 8500 driver under the XFree86 license.
9 This notice must be preserved.
10
11 All Rights Reserved.
12
13 Permission is hereby granted, free of charge, to any person obtaining
14 a copy of this software and associated documentation files (the
15 "Software"), to deal in the Software without restriction, including
16 without limitation the rights to use, copy, modify, merge, publish,
17 distribute, sublicense, and/or sell copies of the Software, and to
18 permit persons to whom the Software is furnished to do so, subject to
19 the following conditions:
20
21 The above copyright notice and this permission notice (including the
22 next paragraph) shall be included in all copies or substantial
23 portions of the Software.
24
25 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
28 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
29 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
30 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
31 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
32
33 **************************************************************************/
34
35 #include "radeon_common.h"
36 #include "xmlpool.h" /* for symbolic values of enum-type options */
37 #include "utils.h"
38 #include "vblank.h"
39 #include "drirenderbuffer.h"
40 #include "main/context.h"
41 #include "main/framebuffer.h"
42 #include "main/renderbuffer.h"
43 #include "main/state.h"
44 #include "main/simple_list.h"
45 #include "swrast/swrast.h"
46 #include "swrast_setup/swrast_setup.h"
47 #include "tnl/tnl.h"
48
49 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) /* +r6/r7 */
50 #include "r600_context.h"
51 #endif
52
53 #define DRIVER_DATE "20090101"
54
55 #ifndef RADEON_DEBUG
56 int RADEON_DEBUG = (0);
57 #endif
58
59
60 static const char* get_chip_family_name(int chip_family)
61 {
62 switch(chip_family) {
63 case CHIP_FAMILY_R100: return "R100";
64 case CHIP_FAMILY_RV100: return "RV100";
65 case CHIP_FAMILY_RS100: return "RS100";
66 case CHIP_FAMILY_RV200: return "RV200";
67 case CHIP_FAMILY_RS200: return "RS200";
68 case CHIP_FAMILY_R200: return "R200";
69 case CHIP_FAMILY_RV250: return "RV250";
70 case CHIP_FAMILY_RS300: return "RS300";
71 case CHIP_FAMILY_RV280: return "RV280";
72 case CHIP_FAMILY_R300: return "R300";
73 case CHIP_FAMILY_R350: return "R350";
74 case CHIP_FAMILY_RV350: return "RV350";
75 case CHIP_FAMILY_RV380: return "RV380";
76 case CHIP_FAMILY_R420: return "R420";
77 case CHIP_FAMILY_RV410: return "RV410";
78 case CHIP_FAMILY_RS400: return "RS400";
79 case CHIP_FAMILY_RS600: return "RS600";
80 case CHIP_FAMILY_RS690: return "RS690";
81 case CHIP_FAMILY_RS740: return "RS740";
82 case CHIP_FAMILY_RV515: return "RV515";
83 case CHIP_FAMILY_R520: return "R520";
84 case CHIP_FAMILY_RV530: return "RV530";
85 case CHIP_FAMILY_R580: return "R580";
86 case CHIP_FAMILY_RV560: return "RV560";
87 case CHIP_FAMILY_RV570: return "RV570";
88 case CHIP_FAMILY_R600: return "R600";
89 case CHIP_FAMILY_RV610: return "RV610";
90 case CHIP_FAMILY_RV630: return "RV630";
91 case CHIP_FAMILY_RV670: return "RV670";
92 case CHIP_FAMILY_RV620: return "RV620";
93 case CHIP_FAMILY_RV635: return "RV635";
94 case CHIP_FAMILY_RS780: return "RS780";
95 case CHIP_FAMILY_RV770: return "RV770";
96 case CHIP_FAMILY_RV730: return "RV730";
97 case CHIP_FAMILY_RV710: return "RV710";
98 case CHIP_FAMILY_RV740: return "RV740";
99 default: return "unknown";
100 }
101 }
102
103
104 /* Return various strings for glGetString().
105 */
106 static const GLubyte *radeonGetString(GLcontext * ctx, GLenum name)
107 {
108 radeonContextPtr radeon = RADEON_CONTEXT(ctx);
109 static char buffer[128];
110
111 switch (name) {
112 case GL_VENDOR:
113 if (IS_R600_CLASS(radeon->radeonScreen))
114 return (GLubyte *) "Advanced Micro Devices, Inc.";
115 else if (IS_R300_CLASS(radeon->radeonScreen))
116 return (GLubyte *) "DRI R300 Project";
117 else
118 return (GLubyte *) "Tungsten Graphics, Inc.";
119
120 case GL_RENDERER:
121 {
122 unsigned offset;
123 GLuint agp_mode = (radeon->radeonScreen->card_type==RADEON_CARD_PCI) ? 0 :
124 radeon->radeonScreen->AGPMode;
125 const char* chipclass;
126 char hardwarename[32];
127
128 if (IS_R600_CLASS(radeon->radeonScreen))
129 chipclass = "R600";
130 else if (IS_R300_CLASS(radeon->radeonScreen))
131 chipclass = "R300";
132 else if (IS_R200_CLASS(radeon->radeonScreen))
133 chipclass = "R200";
134 else
135 chipclass = "R100";
136
137 sprintf(hardwarename, "%s (%s %04X)",
138 chipclass,
139 get_chip_family_name(radeon->radeonScreen->chip_family),
140 radeon->radeonScreen->device_id);
141
142 offset = driGetRendererString(buffer, hardwarename, DRIVER_DATE,
143 agp_mode);
144
145 if (IS_R600_CLASS(radeon->radeonScreen)) {
146 sprintf(&buffer[offset], " TCL");
147 } else if (IS_R300_CLASS(radeon->radeonScreen)) {
148 sprintf(&buffer[offset], " %sTCL",
149 (radeon->radeonScreen->chip_flags & RADEON_CHIPSET_TCL)
150 ? "" : "NO-");
151 } else {
152 sprintf(&buffer[offset], " %sTCL",
153 !(radeon->TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE)
154 ? "" : "NO-");
155 }
156
157 if (radeon->radeonScreen->driScreen->dri2.enabled)
158 strcat(buffer, " DRI2");
159
160 return (GLubyte *) buffer;
161 }
162
163 default:
164 return NULL;
165 }
166 }
167
168 /* Initialize the driver's misc functions.
169 */
170 static void radeonInitDriverFuncs(struct dd_function_table *functions)
171 {
172 functions->GetString = radeonGetString;
173 }
174
175 /**
176 * Create and initialize all common fields of the context,
177 * including the Mesa context itself.
178 */
179 GLboolean radeonInitContext(radeonContextPtr radeon,
180 struct dd_function_table* functions,
181 const __GLcontextModes * glVisual,
182 __DRIcontextPrivate * driContextPriv,
183 void *sharedContextPrivate)
184 {
185 __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
186 radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
187 GLcontext* ctx;
188 GLcontext* shareCtx;
189 int fthrottle_mode;
190
191 /* Fill in additional standard functions. */
192 radeonInitDriverFuncs(functions);
193
194 radeon->radeonScreen = screen;
195 /* Allocate and initialize the Mesa context */
196 if (sharedContextPrivate)
197 shareCtx = ((radeonContextPtr)sharedContextPrivate)->glCtx;
198 else
199 shareCtx = NULL;
200 radeon->glCtx = _mesa_create_context(glVisual, shareCtx,
201 functions, (void *)radeon);
202 if (!radeon->glCtx)
203 return GL_FALSE;
204
205 ctx = radeon->glCtx;
206 driContextPriv->driverPrivate = radeon;
207
208 meta_init_metaops(ctx, &radeon->meta);
209 /* DRI fields */
210 radeon->dri.context = driContextPriv;
211 radeon->dri.screen = sPriv;
212 radeon->dri.hwContext = driContextPriv->hHWContext;
213 radeon->dri.hwLock = &sPriv->pSAREA->lock;
214 radeon->dri.hwLockCount = 0;
215 radeon->dri.fd = sPriv->fd;
216 radeon->dri.drmMinor = sPriv->drm_version.minor;
217
218 radeon->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA +
219 screen->sarea_priv_offset);
220
221 /* Setup IRQs */
222 fthrottle_mode = driQueryOptioni(&radeon->optionCache, "fthrottle_mode");
223 radeon->iw.irq_seq = -1;
224 radeon->irqsEmitted = 0;
225 if (IS_R600_CLASS(radeon->radeonScreen))
226 radeon->do_irqs = 0;
227 else
228 radeon->do_irqs = (fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS &&
229 radeon->radeonScreen->irq);
230
231 radeon->do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
232
233 if (!radeon->do_irqs)
234 fprintf(stderr,
235 "IRQ's not enabled, falling back to %s: %d %d\n",
236 radeon->do_usleeps ? "usleeps" : "busy waits",
237 fthrottle_mode, radeon->radeonScreen->irq);
238
239 radeon->texture_depth = driQueryOptioni (&radeon->optionCache,
240 "texture_depth");
241 if (radeon->texture_depth == DRI_CONF_TEXTURE_DEPTH_FB)
242 radeon->texture_depth = ( glVisual->rgbBits > 16 ) ?
243 DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16;
244
245 if (IS_R600_CLASS(radeon->radeonScreen)) {
246 radeon->texture_row_align = 256;
247 radeon->texture_rect_row_align = 256;
248 radeon->texture_compressed_row_align = 256;
249 } else if (IS_R200_CLASS(radeon->radeonScreen) ||
250 IS_R100_CLASS(radeon->radeonScreen)) {
251 radeon->texture_row_align = 32;
252 radeon->texture_rect_row_align = 64;
253 radeon->texture_compressed_row_align = 32;
254 } else { /* R300 - not sure this is all correct */
255 int chip_family = radeon->radeonScreen->chip_family;
256 if (chip_family == CHIP_FAMILY_RS600 ||
257 chip_family == CHIP_FAMILY_RS690 ||
258 chip_family == CHIP_FAMILY_RS740)
259 radeon->texture_row_align = 64;
260 else
261 radeon->texture_row_align = 32;
262 radeon->texture_rect_row_align = 64;
263 radeon->texture_compressed_row_align = 64;
264 }
265
266 make_empty_list(&radeon->query.not_flushed_head);
267
268 return GL_TRUE;
269 }
270
271
272
273 /**
274 * Destroy the command buffer and state atoms.
275 */
276 static void radeon_destroy_atom_list(radeonContextPtr radeon)
277 {
278 struct radeon_state_atom *atom;
279
280 foreach(atom, &radeon->hw.atomlist) {
281 FREE(atom->cmd);
282 if (atom->lastcmd)
283 FREE(atom->lastcmd);
284 }
285
286 }
287
288 /**
289 * Cleanup common context fields.
290 * Called by r200DestroyContext/r300DestroyContext
291 */
292 void radeonDestroyContext(__DRIcontextPrivate *driContextPriv )
293 {
294 #ifdef RADEON_BO_TRACK
295 FILE *track;
296 #endif
297 GET_CURRENT_CONTEXT(ctx);
298 radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
299 radeonContextPtr current = ctx ? RADEON_CONTEXT(ctx) : NULL;
300 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) /* +r6/r7 */
301 __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
302 radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
303 #endif
304
305 if (radeon == current) {
306 radeon_firevertices(radeon);
307 _mesa_make_current(NULL, NULL, NULL);
308 }
309
310 assert(radeon);
311 if (radeon) {
312 if (radeon->dma.current) {
313 rcommonFlushCmdBuf( radeon, __FUNCTION__ );
314 }
315
316 radeonReleaseArrays(radeon->glCtx, ~0);
317 meta_destroy_metaops(&radeon->meta);
318 if (radeon->vtbl.free_context)
319 radeon->vtbl.free_context(radeon->glCtx);
320 _swsetup_DestroyContext( radeon->glCtx );
321 _tnl_DestroyContext( radeon->glCtx );
322 _vbo_DestroyContext( radeon->glCtx );
323 _swrast_DestroyContext( radeon->glCtx );
324
325 /* free atom list */
326 /* free the Mesa context */
327 _mesa_destroy_context(radeon->glCtx);
328
329 /* _mesa_destroy_context() might result in calls to functions that
330 * depend on the DriverCtx, so don't set it to NULL before.
331 *
332 * radeon->glCtx->DriverCtx = NULL;
333 */
334 /* free the option cache */
335 driDestroyOptionCache(&radeon->optionCache);
336
337 rcommonDestroyCmdBuf(radeon);
338
339 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) /* +r6/r7 */
340 if (!IS_R600_CLASS(screen))
341 #endif
342 radeon_destroy_atom_list(radeon);
343
344 if (radeon->state.scissor.pClipRects) {
345 FREE(radeon->state.scissor.pClipRects);
346 radeon->state.scissor.pClipRects = 0;
347 }
348 }
349 #ifdef RADEON_BO_TRACK
350 track = fopen("/tmp/tracklog", "w");
351 if (track) {
352 radeon_tracker_print(&radeon->radeonScreen->bom->tracker, track);
353 fclose(track);
354 }
355 #endif
356 FREE(radeon);
357 }
358
359 /* Force the context `c' to be unbound from its buffer.
360 */
361 GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv)
362 {
363 radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
364
365 if (RADEON_DEBUG & DEBUG_DRI)
366 fprintf(stderr, "%s ctx %p\n", __FUNCTION__,
367 radeon->glCtx);
368
369 return GL_TRUE;
370 }
371
372
373 static void
374 radeon_make_kernel_renderbuffer_current(radeonContextPtr radeon,
375 struct radeon_framebuffer *draw)
376 {
377 /* if radeon->fake */
378 struct radeon_renderbuffer *rb;
379
380 if ((rb = (void *)draw->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) {
381 if (!rb->bo) {
382 rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
383 radeon->radeonScreen->frontOffset,
384 0,
385 0,
386 RADEON_GEM_DOMAIN_VRAM,
387 0);
388 }
389 rb->cpp = radeon->radeonScreen->cpp;
390 rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp;
391 }
392 if ((rb = (void *)draw->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer)) {
393 if (!rb->bo) {
394 rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
395 radeon->radeonScreen->backOffset,
396 0,
397 0,
398 RADEON_GEM_DOMAIN_VRAM,
399 0);
400 }
401 rb->cpp = radeon->radeonScreen->cpp;
402 rb->pitch = radeon->radeonScreen->backPitch * rb->cpp;
403 }
404 if ((rb = (void *)draw->base.Attachment[BUFFER_DEPTH].Renderbuffer)) {
405 if (!rb->bo) {
406 rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
407 radeon->radeonScreen->depthOffset,
408 0,
409 0,
410 RADEON_GEM_DOMAIN_VRAM,
411 0);
412 }
413 rb->cpp = radeon->radeonScreen->cpp;
414 rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp;
415 }
416 if ((rb = (void *)draw->base.Attachment[BUFFER_STENCIL].Renderbuffer)) {
417 if (!rb->bo) {
418 rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
419 radeon->radeonScreen->depthOffset,
420 0,
421 0,
422 RADEON_GEM_DOMAIN_VRAM,
423 0);
424 }
425 rb->cpp = radeon->radeonScreen->cpp;
426 rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp;
427 }
428 }
429
430 static void
431 radeon_make_renderbuffer_current(radeonContextPtr radeon,
432 struct radeon_framebuffer *draw)
433 {
434 int size = 4096*4096*4;
435 /* if radeon->fake */
436 struct radeon_renderbuffer *rb;
437
438 if (radeon->radeonScreen->kernel_mm) {
439 radeon_make_kernel_renderbuffer_current(radeon, draw);
440 return;
441 }
442
443
444 if ((rb = (void *)draw->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) {
445 if (!rb->bo) {
446 rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
447 radeon->radeonScreen->frontOffset +
448 radeon->radeonScreen->fbLocation,
449 size,
450 4096,
451 RADEON_GEM_DOMAIN_VRAM,
452 0);
453 }
454 rb->cpp = radeon->radeonScreen->cpp;
455 rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp;
456 }
457 if ((rb = (void *)draw->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer)) {
458 if (!rb->bo) {
459 rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
460 radeon->radeonScreen->backOffset +
461 radeon->radeonScreen->fbLocation,
462 size,
463 4096,
464 RADEON_GEM_DOMAIN_VRAM,
465 0);
466 }
467 rb->cpp = radeon->radeonScreen->cpp;
468 rb->pitch = radeon->radeonScreen->backPitch * rb->cpp;
469 }
470 if ((rb = (void *)draw->base.Attachment[BUFFER_DEPTH].Renderbuffer)) {
471 if (!rb->bo) {
472 rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
473 radeon->radeonScreen->depthOffset +
474 radeon->radeonScreen->fbLocation,
475 size,
476 4096,
477 RADEON_GEM_DOMAIN_VRAM,
478 0);
479 }
480 rb->cpp = radeon->radeonScreen->cpp;
481 rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp;
482 }
483 if ((rb = (void *)draw->base.Attachment[BUFFER_STENCIL].Renderbuffer)) {
484 if (!rb->bo) {
485 rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
486 radeon->radeonScreen->depthOffset +
487 radeon->radeonScreen->fbLocation,
488 size,
489 4096,
490 RADEON_GEM_DOMAIN_VRAM,
491 0);
492 }
493 rb->cpp = radeon->radeonScreen->cpp;
494 rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp;
495 }
496 }
497
498 static unsigned
499 radeon_bits_per_pixel(const struct radeon_renderbuffer *rb)
500 {
501 switch (rb->base._ActualFormat) {
502 case GL_RGB5:
503 case GL_DEPTH_COMPONENT16:
504 return 16;
505 case GL_RGB8:
506 case GL_RGBA8:
507 case GL_DEPTH_COMPONENT24:
508 case GL_DEPTH24_STENCIL8_EXT:
509 case GL_STENCIL_INDEX8_EXT:
510 return 32;
511 default:
512 return 0;
513 }
514 }
515
516 void
517 radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
518 {
519 unsigned int attachments[10];
520 __DRIbuffer *buffers = NULL;
521 __DRIscreen *screen;
522 struct radeon_renderbuffer *rb;
523 int i, count;
524 struct radeon_framebuffer *draw;
525 radeonContextPtr radeon;
526 char *regname;
527 struct radeon_bo *depth_bo = NULL, *bo;
528
529 if (RADEON_DEBUG & DEBUG_DRI)
530 fprintf(stderr, "enter %s, drawable %p\n", __func__, drawable);
531
532 draw = drawable->driverPrivate;
533 screen = context->driScreenPriv;
534 radeon = (radeonContextPtr) context->driverPrivate;
535
536 if (screen->dri2.loader
537 && (screen->dri2.loader->base.version > 2)
538 && (screen->dri2.loader->getBuffersWithFormat != NULL)) {
539 struct radeon_renderbuffer *depth_rb;
540 struct radeon_renderbuffer *stencil_rb;
541
542 i = 0;
543 if ((radeon->is_front_buffer_rendering ||
544 radeon->is_front_buffer_reading ||
545 !draw->color_rb[1])
546 && draw->color_rb[0]) {
547 attachments[i++] = __DRI_BUFFER_FRONT_LEFT;
548 attachments[i++] = radeon_bits_per_pixel(draw->color_rb[0]);
549 }
550
551 if (draw->color_rb[1]) {
552 attachments[i++] = __DRI_BUFFER_BACK_LEFT;
553 attachments[i++] = radeon_bits_per_pixel(draw->color_rb[1]);
554 }
555
556 depth_rb = radeon_get_renderbuffer(&draw->base, BUFFER_DEPTH);
557 stencil_rb = radeon_get_renderbuffer(&draw->base, BUFFER_STENCIL);
558
559 if ((depth_rb != NULL) && (stencil_rb != NULL)) {
560 attachments[i++] = __DRI_BUFFER_DEPTH_STENCIL;
561 attachments[i++] = radeon_bits_per_pixel(depth_rb);
562 } else if (depth_rb != NULL) {
563 attachments[i++] = __DRI_BUFFER_DEPTH;
564 attachments[i++] = radeon_bits_per_pixel(depth_rb);
565 } else if (stencil_rb != NULL) {
566 attachments[i++] = __DRI_BUFFER_STENCIL;
567 attachments[i++] = radeon_bits_per_pixel(stencil_rb);
568 }
569
570 buffers = (*screen->dri2.loader->getBuffersWithFormat)(drawable,
571 &drawable->w,
572 &drawable->h,
573 attachments, i / 2,
574 &count,
575 drawable->loaderPrivate);
576 } else if (screen->dri2.loader) {
577 i = 0;
578 if (draw->color_rb[0])
579 attachments[i++] = __DRI_BUFFER_FRONT_LEFT;
580 if (draw->color_rb[1])
581 attachments[i++] = __DRI_BUFFER_BACK_LEFT;
582 if (radeon_get_renderbuffer(&draw->base, BUFFER_DEPTH))
583 attachments[i++] = __DRI_BUFFER_DEPTH;
584 if (radeon_get_renderbuffer(&draw->base, BUFFER_STENCIL))
585 attachments[i++] = __DRI_BUFFER_STENCIL;
586
587 buffers = (*screen->dri2.loader->getBuffers)(drawable,
588 &drawable->w,
589 &drawable->h,
590 attachments, i,
591 &count,
592 drawable->loaderPrivate);
593 }
594
595 if (buffers == NULL)
596 return;
597
598 /* set one cliprect to cover the whole drawable */
599 drawable->x = 0;
600 drawable->y = 0;
601 drawable->backX = 0;
602 drawable->backY = 0;
603 drawable->numClipRects = 1;
604 drawable->pClipRects[0].x1 = 0;
605 drawable->pClipRects[0].y1 = 0;
606 drawable->pClipRects[0].x2 = drawable->w;
607 drawable->pClipRects[0].y2 = drawable->h;
608 drawable->numBackClipRects = 1;
609 drawable->pBackClipRects[0].x1 = 0;
610 drawable->pBackClipRects[0].y1 = 0;
611 drawable->pBackClipRects[0].x2 = drawable->w;
612 drawable->pBackClipRects[0].y2 = drawable->h;
613 for (i = 0; i < count; i++) {
614 switch (buffers[i].attachment) {
615 case __DRI_BUFFER_FRONT_LEFT:
616 rb = draw->color_rb[0];
617 regname = "dri2 front buffer";
618 break;
619 case __DRI_BUFFER_FAKE_FRONT_LEFT:
620 rb = draw->color_rb[0];
621 regname = "dri2 fake front buffer";
622 break;
623 case __DRI_BUFFER_BACK_LEFT:
624 rb = draw->color_rb[1];
625 regname = "dri2 back buffer";
626 break;
627 case __DRI_BUFFER_DEPTH:
628 rb = radeon_get_renderbuffer(&draw->base, BUFFER_DEPTH);
629 regname = "dri2 depth buffer";
630 break;
631 case __DRI_BUFFER_DEPTH_STENCIL:
632 rb = radeon_get_renderbuffer(&draw->base, BUFFER_DEPTH);
633 regname = "dri2 depth / stencil buffer";
634 break;
635 case __DRI_BUFFER_STENCIL:
636 rb = radeon_get_renderbuffer(&draw->base, BUFFER_STENCIL);
637 regname = "dri2 stencil buffer";
638 break;
639 case __DRI_BUFFER_ACCUM:
640 default:
641 fprintf(stderr,
642 "unhandled buffer attach event, attacment type %d\n",
643 buffers[i].attachment);
644 return;
645 }
646
647 if (rb == NULL)
648 continue;
649
650 if (rb->bo) {
651 uint32_t name = radeon_gem_name_bo(rb->bo);
652 if (name == buffers[i].name)
653 continue;
654 }
655
656 if (RADEON_DEBUG & DEBUG_DRI)
657 fprintf(stderr,
658 "attaching buffer %s, %d, at %d, cpp %d, pitch %d\n",
659 regname, buffers[i].name, buffers[i].attachment,
660 buffers[i].cpp, buffers[i].pitch);
661
662 rb->cpp = buffers[i].cpp;
663 rb->pitch = buffers[i].pitch;
664 rb->base.Width = drawable->w;
665 rb->base.Height = drawable->h;
666 rb->has_surface = 0;
667
668 if (buffers[i].attachment == __DRI_BUFFER_STENCIL && depth_bo) {
669 if (RADEON_DEBUG & DEBUG_DRI)
670 fprintf(stderr, "(reusing depth buffer as stencil)\n");
671 bo = depth_bo;
672 radeon_bo_ref(bo);
673 } else {
674 uint32_t tiling_flags = 0, pitch = 0;
675 int ret;
676
677 bo = radeon_bo_open(radeon->radeonScreen->bom,
678 buffers[i].name,
679 0,
680 0,
681 RADEON_GEM_DOMAIN_VRAM,
682 buffers[i].flags);
683
684 if (bo == NULL) {
685
686 fprintf(stderr, "failed to attach %s %d\n",
687 regname, buffers[i].name);
688
689 }
690
691 ret = radeon_bo_get_tiling(bo, &tiling_flags, &pitch);
692 if (tiling_flags & RADEON_TILING_MACRO)
693 bo->flags |= RADEON_BO_FLAGS_MACRO_TILE;
694 if (tiling_flags & RADEON_TILING_MICRO)
695 bo->flags |= RADEON_BO_FLAGS_MICRO_TILE;
696
697 }
698
699 if (buffers[i].attachment == __DRI_BUFFER_DEPTH) {
700 if (draw->base.Visual.depthBits == 16)
701 rb->cpp = 2;
702 depth_bo = bo;
703 }
704
705 radeon_renderbuffer_set_bo(rb, bo);
706 radeon_bo_unref(bo);
707
708 if (buffers[i].attachment == __DRI_BUFFER_DEPTH_STENCIL) {
709 rb = radeon_get_renderbuffer(&draw->base, BUFFER_STENCIL);
710 if (rb != NULL) {
711 struct radeon_bo *stencil_bo = NULL;
712
713 if (rb->bo) {
714 uint32_t name = radeon_gem_name_bo(rb->bo);
715 if (name == buffers[i].name)
716 continue;
717 }
718
719 stencil_bo = bo;
720 radeon_bo_ref(stencil_bo);
721 radeon_renderbuffer_set_bo(rb, stencil_bo);
722 radeon_bo_unref(stencil_bo);
723 }
724 }
725 }
726
727 driUpdateFramebufferSize(radeon->glCtx, drawable);
728 }
729
730 /* Force the context `c' to be the current context and associate with it
731 * buffer `b'.
732 */
733 GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv,
734 __DRIdrawablePrivate * driDrawPriv,
735 __DRIdrawablePrivate * driReadPriv)
736 {
737 radeonContextPtr radeon;
738 struct radeon_framebuffer *drfb;
739 struct gl_framebuffer *readfb;
740
741 if (!driContextPriv) {
742 if (RADEON_DEBUG & DEBUG_DRI)
743 fprintf(stderr, "%s ctx is null\n", __FUNCTION__);
744 _mesa_make_current(NULL, NULL, NULL);
745 return GL_TRUE;
746 }
747
748 radeon = (radeonContextPtr) driContextPriv->driverPrivate;
749 drfb = driDrawPriv->driverPrivate;
750 readfb = driReadPriv->driverPrivate;
751
752 if (driContextPriv->driScreenPriv->dri2.enabled) {
753 radeon_update_renderbuffers(driContextPriv, driDrawPriv);
754 if (driDrawPriv != driReadPriv)
755 radeon_update_renderbuffers(driContextPriv, driReadPriv);
756 _mesa_reference_renderbuffer(&radeon->state.color.rb,
757 &(radeon_get_renderbuffer(&drfb->base, BUFFER_BACK_LEFT)->base));
758 _mesa_reference_renderbuffer(&radeon->state.depth.rb,
759 &(radeon_get_renderbuffer(&drfb->base, BUFFER_DEPTH)->base));
760 } else {
761 radeon_make_renderbuffer_current(radeon, drfb);
762 }
763
764 if (RADEON_DEBUG & DEBUG_DRI)
765 fprintf(stderr, "%s ctx %p dfb %p rfb %p\n", __FUNCTION__, radeon->glCtx, drfb, readfb);
766
767 driUpdateFramebufferSize(radeon->glCtx, driDrawPriv);
768 if (driReadPriv != driDrawPriv)
769 driUpdateFramebufferSize(radeon->glCtx, driReadPriv);
770
771 _mesa_make_current(radeon->glCtx, &drfb->base, readfb);
772
773 _mesa_update_state(radeon->glCtx);
774
775 if (radeon->glCtx->DrawBuffer == &drfb->base) {
776 if (driDrawPriv->swap_interval == (unsigned)-1) {
777 int i;
778 driDrawPriv->vblFlags =
779 (radeon->radeonScreen->irq != 0)
780 ? driGetDefaultVBlankFlags(&radeon->
781 optionCache)
782 : VBLANK_FLAG_NO_IRQ;
783
784 driDrawableInitVBlank(driDrawPriv);
785 drfb->vbl_waited = driDrawPriv->vblSeq;
786
787 for (i = 0; i < 2; i++) {
788 if (drfb->color_rb[i])
789 drfb->color_rb[i]->vbl_pending = driDrawPriv->vblSeq;
790 }
791
792 }
793
794 radeon_window_moved(radeon);
795 radeon_draw_buffer(radeon->glCtx, &drfb->base);
796 }
797
798
799 if (RADEON_DEBUG & DEBUG_DRI)
800 fprintf(stderr, "End %s\n", __FUNCTION__);
801
802 return GL_TRUE;
803 }
804