src/mesa/drivers/dri/radeon/radeon_common_context.h

   1
   2 #ifndef COMMON_CONTEXT_H
   3 #define COMMON_CONTEXT_H
   4
   5 #include "main/mm.h"
   6 #include "math/m_vector.h"
   7 #include "tnl/t_context.h"
   8 #include "main/colormac.h"
   9
  10 #include "radeon_debug.h"
  11 #include "radeon_screen.h"
  12 #include "radeon_drm.h"
  13 #include "dri_util.h"
  14 #include "tnl/t_vertex.h"
  15 #include "swrast/s_context.h"
  16
  17 struct radeon_context;
  18
  19 #include "radeon_bo_gem.h"
  20 #include "radeon_cs_gem.h"
  21
  22 /* This union is used to avoid warnings/miscompilation
  23    with float to uint32_t casts due to strict-aliasing */
  24 typedef union { GLfloat f; uint32_t ui32; } float_ui32_type;
  25
  26 struct radeon_context;
  27 typedef struct radeon_context radeonContextRec;
  28 typedef struct radeon_context *radeonContextPtr;
  29
  30
  31 #define TEX_0   0x1
  32 #define TEX_1   0x2
  33 #define TEX_2   0x4
  34 #define TEX_3   0x8
  35 #define TEX_4   0x10
  36 #define TEX_5   0x20
  37
  38 /* Rasterizing fallbacks */
  39 /* See correponding strings in r200_swtcl.c */
  40 #define RADEON_FALLBACK_TEXTURE         0x0001
  41 #define RADEON_FALLBACK_DRAW_BUFFER     0x0002
  42 #define RADEON_FALLBACK_STENCIL         0x0004
  43 #define RADEON_FALLBACK_RENDER_MODE     0x0008
  44 #define RADEON_FALLBACK_BLEND_EQ        0x0010
  45 #define RADEON_FALLBACK_BLEND_FUNC      0x0020
  46 #define RADEON_FALLBACK_DISABLE         0x0040
  47 #define RADEON_FALLBACK_BORDER_MODE     0x0080
  48 #define RADEON_FALLBACK_DEPTH_BUFFER    0x0100
  49 #define RADEON_FALLBACK_STENCIL_BUFFER  0x0200
  50
  51 #define R200_FALLBACK_TEXTURE           0x01
  52 #define R200_FALLBACK_DRAW_BUFFER       0x02
  53 #define R200_FALLBACK_STENCIL           0x04
  54 #define R200_FALLBACK_RENDER_MODE       0x08
  55 #define R200_FALLBACK_DISABLE           0x10
  56 #define R200_FALLBACK_BORDER_MODE       0x20
  57
  58 #define RADEON_TCL_FALLBACK_RASTER            0x1 /* rasterization */
  59 #define RADEON_TCL_FALLBACK_UNFILLED          0x2 /* unfilled tris */
  60 #define RADEON_TCL_FALLBACK_LIGHT_TWOSIDE     0x4 /* twoside tris */
  61 #define RADEON_TCL_FALLBACK_MATERIAL          0x8 /* material in vb */
  62 #define RADEON_TCL_FALLBACK_TEXGEN_0          0x10 /* texgen, unit 0 */
  63 #define RADEON_TCL_FALLBACK_TEXGEN_1          0x20 /* texgen, unit 1 */
  64 #define RADEON_TCL_FALLBACK_TEXGEN_2          0x40 /* texgen, unit 2 */
  65 #define RADEON_TCL_FALLBACK_TCL_DISABLE       0x80 /* user disable */
  66 #define RADEON_TCL_FALLBACK_FOGCOORDSPEC      0x100 /* fogcoord, sep. spec light */
  67
  68 /* The blit width for texture uploads
  69  */
  70 #define BLIT_WIDTH_BYTES 1024
  71
  72 /* Use the templated vertex format:
  73  */
  74 #define COLOR_IS_RGBA
  75 #define TAG(x) radeon##x
  76 #include "tnl_dd/t_dd_vertex.h"
  77 #undef TAG
  78
  79 #define RADEON_RB_CLASS 0xdeadbeef
  80
  81 struct radeon_renderbuffer
  82 {
  83         struct swrast_renderbuffer base;
  84
  85         struct radeon_bo *bo;
  86         unsigned int cpp;
  87         /* unsigned int offset; */
  88         unsigned int pitch;
  89
  90         struct radeon_bo *map_bo;
  91         GLbitfield map_mode;
  92         int map_x, map_y, map_w, map_h;
  93         int map_pitch;
  94         void *map_buffer;
  95
  96         uint32_t draw_offset; /* FBO */
  97         /* boo Xorg 6.8.2 compat */
  98         int has_surface;
  99
 100         GLuint pf_pending;  /**< sequence number of pending flip */
 101         __DRIdrawable *dPriv;
 102 };
 103
 104 struct radeon_framebuffer
 105 {
 106         struct gl_framebuffer base;
 107
 108         struct radeon_renderbuffer *color_rb[2];
 109 };
 110
 111
 112 struct radeon_colorbuffer_state {
 113         int roundEnable;
 114         struct gl_renderbuffer *rb;
 115         uint32_t draw_offset; /* offset into color renderbuffer - FBOs */
 116 };
 117
 118 struct radeon_depthbuffer_state {
 119         struct gl_renderbuffer *rb;
 120 };
 121
 122 struct radeon_scissor_state {
 123         drm_clip_rect_t rect;
 124         GLboolean enabled;
 125
 126         GLuint numClipRects;    /* Cliprects active */
 127         GLuint numAllocedClipRects;     /* Cliprects available */
 128         drm_clip_rect_t *pClipRects;
 129 };
 130
 131 struct radeon_state_atom {
 132         struct radeon_state_atom *next, *prev;
 133         const char *name;       /* for debug */
 134         int cmd_size;           /* size in bytes */
 135         GLuint idx;
 136         GLuint is_tcl;
 137         GLuint *cmd;            /* one or more cmd's */
 138         GLuint *lastcmd;                /* one or more cmd's */
 139         GLboolean dirty;        /* dirty-mark in emit_state_list */
 140         int (*check) (struct gl_context *, struct radeon_state_atom *atom); /* is this state active? */
 141         void (*emit) (struct gl_context *, struct radeon_state_atom *atom);
 142 };
 143
 144 struct radeon_hw_state {
 145         /* Head of the linked list of state atoms. */
 146         struct radeon_state_atom atomlist;
 147         int max_state_size;     /* Number of bytes necessary for a full state emit. */
 148         int max_post_flush_size; /* Number of bytes necessary for post flushing emits */
 149         GLboolean is_dirty, all_dirty;
 150 };
 151
 152
 153 /* Texture related */
 154 typedef struct _radeon_texture_image radeon_texture_image;
 155
 156
 157 /**
 158  * This is a subclass of swrast_texture_image since we use swrast
 159  * for software fallback rendering.
 160  */
 161 struct _radeon_texture_image {
 162         struct swrast_texture_image base;
 163
 164         /**
 165          * If mt != 0, the image is stored in hardware format in the
 166          * given mipmap tree. In this case, base.Data may point into the
 167          * mapping of the buffer object that contains the mipmap tree.
 168          *
 169          * If mt == 0, the image is stored in normal memory pointed to
 170          * by base.Data.
 171          */
 172         struct _radeon_mipmap_tree *mt;
 173         struct radeon_bo *bo;
 174         GLboolean used_as_render_target;
 175 };
 176
 177
 178 static INLINE radeon_texture_image *get_radeon_texture_image(struct gl_texture_image *image)
 179 {
 180         return (radeon_texture_image*)image;
 181 }
 182
 183
 184 typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr;
 185
 186 #define RADEON_TXO_MICRO_TILE               (1 << 3)
 187
 188 /* Texture object in locally shared texture space.
 189  */
 190 struct radeon_tex_obj {
 191         struct gl_texture_object base;
 192         struct _radeon_mipmap_tree *mt;
 193
 194         /**
 195          * This is true if we've verified that the mipmap tree above is complete
 196          * and so on.
 197          */
 198         GLboolean validated;
 199         /* Minimum LOD to be used during rendering */
 200         unsigned minLod;
 201         /* Miximum LOD to be used during rendering */
 202         unsigned maxLod;
 203
 204         GLuint override_offset;
 205         GLboolean image_override; /* Image overridden by GLX_EXT_tfp */
 206         GLuint tile_bits;       /* hw texture tile bits used on this texture */
 207         struct radeon_bo *bo;
 208
 209         GLuint pp_txfilter;     /* hardware register values */
 210         GLuint pp_txformat;
 211         GLuint pp_txformat_x;
 212         GLuint pp_txsize;       /* npot only */
 213         GLuint pp_txpitch;      /* npot only */
 214         GLuint pp_border_color;
 215         GLuint pp_cubic_faces;  /* cube face 1,2,3,4 log2 sizes */
 216
 217         GLboolean border_fallback;
 218 };
 219
 220 static INLINE radeonTexObj* radeon_tex_obj(struct gl_texture_object *texObj)
 221 {
 222         return (radeonTexObj*)texObj;
 223 }
 224
 225 /* occlusion query */
 226 struct radeon_query_object {
 227         struct gl_query_object Base;
 228         struct radeon_bo *bo;
 229         int curr_offset;
 230         GLboolean emitted_begin;
 231
 232         /* Double linked list of not flushed query objects */
 233         struct radeon_query_object *prev, *next;
 234 };
 235
 236 /* Need refcounting on dma buffers:
 237  */
 238 struct radeon_dma_buffer {
 239         int refcount;           /* the number of retained regions in buf */
 240         drmBufPtr buf;
 241 };
 242
 243 struct radeon_aos {
 244         struct radeon_bo *bo; /** Buffer object where vertex data is stored */
 245         int offset; /** Offset into buffer object, in bytes */
 246         int components; /** Number of components per vertex */
 247         int stride; /** Stride in dwords (may be 0 for repeating) */
 248         int count; /** Number of vertices */
 249 };
 250
 251 #define DMA_BO_FREE_TIME 100
 252
 253 struct radeon_dma_bo {
 254   struct radeon_dma_bo *next, *prev;
 255   struct radeon_bo *bo;
 256   int expire_counter;
 257 };
 258
 259 struct radeon_dma {
 260         /* Active dma region.  Allocations for vertices and retained
 261          * regions come from here.  Also used for emitting random vertices,
 262          * these may be flushed by calling flush_current();
 263          */
 264         struct radeon_dma_bo free;
 265         struct radeon_dma_bo wait;
 266         struct radeon_dma_bo reserved;
 267         size_t current_used; /** Number of bytes allocated and forgotten about */
 268         size_t current_vertexptr; /** End of active vertex region */
 269         size_t minimum_size;
 270
 271         /**
 272          * If current_vertexptr != current_used then flush must be non-zero.
 273          * flush must be called before non-active vertex allocations can be
 274          * performed.
 275          */
 276         void (*flush) (struct gl_context *);
 277 };
 278
 279 /* radeon_swtcl.c
 280  */
 281 struct radeon_swtcl_info {
 282
 283         GLuint RenderIndex;
 284         GLuint vertex_size;
 285         GLubyte *verts;
 286
 287         /* Fallback rasterization functions
 288          */
 289         GLuint hw_primitive;
 290         GLenum render_primitive;
 291         GLuint numverts;
 292
 293         struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX];
 294         GLuint vertex_attr_count;
 295
 296         GLuint emit_prediction;
 297         struct radeon_bo *bo;
 298 };
 299
 300 #define RADEON_MAX_AOS_ARRAYS           16
 301 struct radeon_tcl_info {
 302         struct radeon_aos aos[RADEON_MAX_AOS_ARRAYS];
 303         GLuint aos_count;
 304         struct radeon_bo *elt_dma_bo; /** Buffer object that contains element indices */
 305         int elt_dma_offset; /** Offset into this buffer object, in bytes */
 306 };
 307
 308 struct radeon_ioctl {
 309         GLuint vertex_offset;
 310         GLuint vertex_max;
 311         struct radeon_bo *bo;
 312         GLuint vertex_size;
 313 };
 314
 315 #define RADEON_MAX_PRIMS 64
 316
 317 struct radeon_prim {
 318         GLuint start;
 319         GLuint end;
 320         GLuint prim;
 321 };
 322
 323 static INLINE GLuint radeonPackColor(GLuint cpp,
 324                                      GLubyte r, GLubyte g,
 325                                      GLubyte b, GLubyte a)
 326 {
 327         switch (cpp) {
 328         case 2:
 329                 return PACK_COLOR_565(r, g, b);
 330         case 4:
 331                 return PACK_COLOR_8888(a, r, g, b);
 332         default:
 333                 return 0;
 334         }
 335 }
 336
 337 #define MAX_CMD_BUF_SZ (16*1024)
 338
 339 #define MAX_DMA_BUF_SZ (64*1024)
 340
 341 struct radeon_store {
 342         GLuint statenr;
 343         GLuint primnr;
 344         char cmd_buf[MAX_CMD_BUF_SZ];
 345         int cmd_used;
 346         int elts_start;
 347 };
 348
 349 struct radeon_dri_mirror {
 350         __DRIcontext *context;  /* DRI context */
 351         __DRIscreen *screen;    /* DRI screen */
 352
 353         drm_context_t hwContext;
 354         drm_hw_lock_t *hwLock;
 355         int hwLockCount;
 356         int fd;
 357         int drmMinor;
 358 };
 359
 360 typedef void (*radeon_tri_func) (radeonContextPtr,
 361                                  radeonVertex *,
 362                                  radeonVertex *, radeonVertex *);
 363
 364 typedef void (*radeon_line_func) (radeonContextPtr,
 365                                   radeonVertex *, radeonVertex *);
 366
 367 typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *);
 368
 369 #define RADEON_MAX_BOS 32
 370 struct radeon_state {
 371         struct radeon_colorbuffer_state color;
 372         struct radeon_depthbuffer_state depth;
 373         struct radeon_scissor_state scissor;
 374 };
 375
 376 /**
 377  * This structure holds the command buffer while it is being constructed.
 378  *
 379  * The first batch of commands in the buffer is always the state that needs
 380  * to be re-emitted when the context is lost. This batch can be skipped
 381  * otherwise.
 382  */
 383 struct radeon_cmdbuf {
 384         struct radeon_cs_manager    *csm;
 385         struct radeon_cs            *cs;
 386         int size; /** # of dwords total */
 387         unsigned int flushing:1; /** whether we're currently in FlushCmdBufLocked */
 388 };
 389
 390 struct radeon_context {
 391    struct gl_context *glCtx;
 392    radeonScreenPtr radeonScreen;        /* Screen private DRI data */
 393
 394    /* Texture object bookkeeping
 395     */
 396    int                   texture_depth;
 397    float                 initialMaxAnisotropy;
 398    uint32_t              texture_row_align;
 399    uint32_t              texture_rect_row_align;
 400    uint32_t              texture_compressed_row_align;
 401
 402   struct radeon_dma dma;
 403   struct radeon_hw_state hw;
 404    /* Rasterization and vertex state:
 405     */
 406    GLuint TclFallback;
 407    GLuint Fallback;
 408    GLuint NewGLState;
 409    GLbitfield64 tnl_index_bitset;       /* index of bits for last tnl_install_attrs */
 410
 411    /* Drawable information */
 412    unsigned int lastStamp;
 413    drm_radeon_sarea_t *sarea;   /* Private SAREA data */
 414
 415    /* Mirrors of some DRI state */
 416    struct radeon_dri_mirror dri;
 417
 418    /* Busy waiting */
 419    GLuint do_usleeps;
 420    GLuint do_irqs;
 421    GLuint irqsEmitted;
 422    drm_radeon_irq_wait_t iw;
 423
 424    /* Derived state - for r300 only */
 425    struct radeon_state state;
 426
 427    struct radeon_swtcl_info swtcl;
 428    struct radeon_tcl_info tcl;
 429    /* Configuration cache
 430     */
 431    driOptionCache optionCache;
 432
 433    struct radeon_cmdbuf cmdbuf;
 434
 435    struct radeon_debug debug;
 436
 437   drm_clip_rect_t fboRect;
 438   GLboolean front_cliprects;
 439
 440    /**
 441     * Set if rendering has occured to the drawable's front buffer.
 442     *
 443     * This is used in the DRI2 case to detect that glFlush should also copy
 444     * the contents of the fake front buffer to the real front buffer.
 445     */
 446    GLboolean front_buffer_dirty;
 447
 448    /**
 449     * Track whether front-buffer rendering is currently enabled
 450     *
 451     * A separate flag is used to track this in order to support MRT more
 452     * easily.
 453     */
 454    GLboolean is_front_buffer_rendering;
 455
 456    /**
 457     * Track whether front-buffer is the current read target.
 458     *
 459     * This is closely associated with is_front_buffer_rendering, but may
 460     * be set separately.  The DRI2 fake front buffer must be referenced
 461     * either way.
 462     */
 463    GLboolean is_front_buffer_reading;
 464
 465    struct {
 466         struct radeon_query_object *current;
 467         struct radeon_state_atom queryobj;
 468    } query;
 469
 470    struct {
 471            void (*get_lock)(radeonContextPtr radeon);
 472            void (*update_viewport_offset)(struct gl_context *ctx);
 473            void (*emit_cs_header)(struct radeon_cs *cs, radeonContextPtr rmesa);
 474            void (*swtcl_flush)(struct gl_context *ctx, uint32_t offset);
 475            void (*pre_emit_atoms)(radeonContextPtr rmesa);
 476            void (*pre_emit_state)(radeonContextPtr rmesa);
 477            void (*fallback)(struct gl_context *ctx, GLuint bit, GLboolean mode);
 478            void (*free_context)(struct gl_context *ctx);
 479            void (*emit_query_finish)(radeonContextPtr radeon);
 480            void (*update_scissor)(struct gl_context *ctx);
 481            unsigned (*check_blit)(gl_format mesa_format, uint32_t dst_pitch);
 482            unsigned (*blit)(struct gl_context *ctx,
 483                         struct radeon_bo *src_bo,
 484                         intptr_t src_offset,
 485                         gl_format src_mesaformat,
 486                         unsigned src_pitch,
 487                         unsigned src_width,
 488                         unsigned src_height,
 489                         unsigned src_x_offset,
 490                         unsigned src_y_offset,
 491                         struct radeon_bo *dst_bo,
 492                         intptr_t dst_offset,
 493                         gl_format dst_mesaformat,
 494                         unsigned dst_pitch,
 495                         unsigned dst_width,
 496                         unsigned dst_height,
 497                         unsigned dst_x_offset,
 498                         unsigned dst_y_offset,
 499                         unsigned reg_width,
 500                         unsigned reg_height,
 501                         unsigned flip_y);
 502            unsigned (*is_format_renderable)(gl_format mesa_format);
 503    } vtbl;
 504 };
 505
 506 #define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx))
 507
 508 static inline __DRIdrawable* radeon_get_drawable(radeonContextPtr radeon)
 509 {
 510         return radeon->dri.context->driDrawablePriv;
 511 }
 512
 513 static inline __DRIdrawable* radeon_get_readable(radeonContextPtr radeon)
 514 {
 515         return radeon->dri.context->driReadablePriv;
 516 }
 517
 518 GLboolean radeonInitContext(radeonContextPtr radeon,
 519                             struct dd_function_table* functions,
 520                             const struct gl_config * glVisual,
 521                             __DRIcontext * driContextPriv,
 522                             void *sharedContextPrivate);
 523
 524 void radeonCleanupContext(radeonContextPtr radeon);
 525 GLboolean radeonUnbindContext(__DRIcontext * driContextPriv);
 526 void radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable,
 527                                  GLboolean front_only);
 528 GLboolean radeonMakeCurrent(__DRIcontext * driContextPriv,
 529                             __DRIdrawable * driDrawPriv,
 530                             __DRIdrawable * driReadPriv);
 531 extern void radeonDestroyContext(__DRIcontext * driContextPriv);
 532 void radeon_prepare_render(radeonContextPtr radeon);
 533
 534 #endif