src/mesa/drivers/dri/radeon/radeon_common_context.h

   1
   2 #ifndef COMMON_CONTEXT_H
   3 #define COMMON_CONTEXT_H
   4
   5 #include "main/mm.h"
   6 #include "math/m_vector.h"
   7 #include "texmem.h"
   8 #include "tnl/t_context.h"
   9 #include "main/colormac.h"
  10
  11 #include "radeon_screen.h"
  12 #include "radeon_drm.h"
  13 #include "dri_util.h"
  14 #include "tnl/t_vertex.h"
  15
  16 struct radeon_context;
  17
  18 #include "radeon_bocs_wrapper.h"
  19
  20 /* This union is used to avoid warnings/miscompilation
  21    with float to uint32_t casts due to strict-aliasing */
  22 typedef union { GLfloat f; uint32_t ui32; } float_ui32_type;
  23
  24 struct radeon_context;
  25 typedef struct radeon_context radeonContextRec;
  26 typedef struct radeon_context *radeonContextPtr;
  27
  28
  29 #define TEX_0   0x1
  30 #define TEX_1   0x2
  31 #define TEX_2   0x4
  32 #define TEX_3   0x8
  33 #define TEX_4   0x10
  34 #define TEX_5   0x20
  35
  36 /* Rasterizing fallbacks */
  37 /* See correponding strings in r200_swtcl.c */
  38 #define RADEON_FALLBACK_TEXTURE         0x0001
  39 #define RADEON_FALLBACK_DRAW_BUFFER     0x0002
  40 #define RADEON_FALLBACK_STENCIL         0x0004
  41 #define RADEON_FALLBACK_RENDER_MODE     0x0008
  42 #define RADEON_FALLBACK_BLEND_EQ        0x0010
  43 #define RADEON_FALLBACK_BLEND_FUNC      0x0020
  44 #define RADEON_FALLBACK_DISABLE         0x0040
  45 #define RADEON_FALLBACK_BORDER_MODE     0x0080
  46 #define RADEON_FALLBACK_DEPTH_BUFFER    0x0100
  47 #define RADEON_FALLBACK_STENCIL_BUFFER  0x0200
  48
  49 #define R200_FALLBACK_TEXTURE           0x01
  50 #define R200_FALLBACK_DRAW_BUFFER       0x02
  51 #define R200_FALLBACK_STENCIL           0x04
  52 #define R200_FALLBACK_RENDER_MODE       0x08
  53 #define R200_FALLBACK_DISABLE           0x10
  54 #define R200_FALLBACK_BORDER_MODE       0x20
  55
  56 #define RADEON_TCL_FALLBACK_RASTER            0x1 /* rasterization */
  57 #define RADEON_TCL_FALLBACK_UNFILLED          0x2 /* unfilled tris */
  58 #define RADEON_TCL_FALLBACK_LIGHT_TWOSIDE     0x4 /* twoside tris */
  59 #define RADEON_TCL_FALLBACK_MATERIAL          0x8 /* material in vb */
  60 #define RADEON_TCL_FALLBACK_TEXGEN_0          0x10 /* texgen, unit 0 */
  61 #define RADEON_TCL_FALLBACK_TEXGEN_1          0x20 /* texgen, unit 1 */
  62 #define RADEON_TCL_FALLBACK_TEXGEN_2          0x40 /* texgen, unit 2 */
  63 #define RADEON_TCL_FALLBACK_TCL_DISABLE       0x80 /* user disable */
  64 #define RADEON_TCL_FALLBACK_FOGCOORDSPEC      0x100 /* fogcoord, sep. spec light */
  65
  66 /* The blit width for texture uploads
  67  */
  68 #define BLIT_WIDTH_BYTES 1024
  69
  70 /* Use the templated vertex format:
  71  */
  72 #define COLOR_IS_RGBA
  73 #define TAG(x) radeon##x
  74 #include "tnl_dd/t_dd_vertex.h"
  75 #undef TAG
  76
  77 #define RADEON_RB_CLASS 0xdeadbeef
  78
  79 struct radeon_renderbuffer
  80 {
  81         struct gl_renderbuffer base;
  82         struct radeon_bo *bo;
  83         unsigned int cpp;
  84         /* unsigned int offset; */
  85         unsigned int pitch;
  86         unsigned int width;
  87         unsigned int height;
  88
  89         uint32_t draw_offset; /* FBO */
  90         /* boo Xorg 6.8.2 compat */
  91         int has_surface;
  92
  93         GLuint pf_pending;  /**< sequence number of pending flip */
  94         GLuint vbl_pending;   /**< vblank sequence number of pending flip */
  95         __DRIdrawablePrivate *dPriv;
  96 };
  97
  98 struct radeon_framebuffer
  99 {
 100         struct gl_framebuffer base;
 101
 102         struct radeon_renderbuffer *color_rb[2];
 103
 104         GLuint vbl_waited;
 105
 106         /* buffer swap */
 107         int64_t swap_ust;
 108         int64_t swap_missed_ust;
 109
 110         GLuint swap_count;
 111         GLuint swap_missed_count;
 112
 113         /* Drawable page flipping state */
 114         GLboolean pf_active;
 115         GLint pf_current_page;
 116         GLint pf_num_pages;
 117
 118 };
 119
 120
 121 struct radeon_colorbuffer_state {
 122         GLuint clear;
 123         int roundEnable;
 124         struct radeon_renderbuffer *rrb;
 125         uint32_t draw_offset; /* offset into color renderbuffer - FBOs */
 126 };
 127
 128 struct radeon_depthbuffer_state {
 129         GLuint clear;
 130         struct radeon_renderbuffer *rrb;
 131 };
 132
 133 struct radeon_scissor_state {
 134         drm_clip_rect_t rect;
 135         GLboolean enabled;
 136
 137         GLuint numClipRects;    /* Cliprects active */
 138         GLuint numAllocedClipRects;     /* Cliprects available */
 139         drm_clip_rect_t *pClipRects;
 140 };
 141
 142 struct radeon_stencilbuffer_state {
 143         GLuint clear;           /* rb3d_stencilrefmask value */
 144 };
 145
 146 struct radeon_stipple_state {
 147         GLuint mask[32];
 148 };
 149
 150 struct radeon_state_atom {
 151         struct radeon_state_atom *next, *prev;
 152         const char *name;       /* for debug */
 153         int cmd_size;           /* size in bytes */
 154         GLuint idx;
 155         GLuint is_tcl;
 156         GLuint *cmd;            /* one or more cmd's */
 157         GLuint *lastcmd;                /* one or more cmd's */
 158         GLboolean dirty;        /* dirty-mark in emit_state_list */
 159         int (*check) (GLcontext *, struct radeon_state_atom *atom); /* is this state active? */
 160         void (*emit) (GLcontext *, struct radeon_state_atom *atom);
 161 };
 162
 163 struct radeon_hw_state {
 164         /* Head of the linked list of state atoms. */
 165         struct radeon_state_atom atomlist;
 166         int max_state_size;     /* Number of bytes necessary for a full state emit. */
 167         GLboolean is_dirty, all_dirty;
 168 };
 169
 170
 171 /* Texture related */
 172 typedef struct _radeon_texture_image radeon_texture_image;
 173
 174 struct _radeon_texture_image {
 175         struct gl_texture_image base;
 176
 177         /**
 178          * If mt != 0, the image is stored in hardware format in the
 179          * given mipmap tree. In this case, base.Data may point into the
 180          * mapping of the buffer object that contains the mipmap tree.
 181          *
 182          * If mt == 0, the image is stored in normal memory pointed to
 183          * by base.Data.
 184          */
 185         struct _radeon_mipmap_tree *mt;
 186         struct radeon_bo *bo;
 187
 188         int mtlevel; /** if mt != 0, this is the image's level in the mipmap tree */
 189         int mtface; /** if mt != 0, this is the image's face in the mipmap tree */
 190 };
 191
 192
 193 static INLINE radeon_texture_image *get_radeon_texture_image(struct gl_texture_image *image)
 194 {
 195         return (radeon_texture_image*)image;
 196 }
 197
 198
 199 typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr;
 200
 201 #define RADEON_TXO_MICRO_TILE               (1 << 3)
 202
 203 /* Texture object in locally shared texture space.
 204  */
 205 struct radeon_tex_obj {
 206         struct gl_texture_object base;
 207         struct _radeon_mipmap_tree *mt;
 208
 209         /**
 210          * This is true if we've verified that the mipmap tree above is complete
 211          * and so on.
 212          */
 213         GLboolean validated;
 214
 215         GLuint override_offset;
 216         GLboolean image_override; /* Image overridden by GLX_EXT_tfp */
 217         GLuint tile_bits;       /* hw texture tile bits used on this texture */
 218         struct radeon_bo *bo;
 219
 220         GLuint pp_txfilter;     /* hardware register values */
 221         GLuint pp_txformat;
 222         GLuint pp_txformat_x;
 223         GLuint pp_txsize;       /* npot only */
 224         GLuint pp_txpitch;      /* npot only */
 225         GLuint pp_border_color;
 226         GLuint pp_cubic_faces;  /* cube face 1,2,3,4 log2 sizes */
 227
 228         GLuint pp_txfilter_1;   /*  r300 */
 229
 230         GLboolean border_fallback;
 231
 232
 233 };
 234
 235 static INLINE radeonTexObj* radeon_tex_obj(struct gl_texture_object *texObj)
 236 {
 237         return (radeonTexObj*)texObj;
 238 }
 239
 240 /* Need refcounting on dma buffers:
 241  */
 242 struct radeon_dma_buffer {
 243         int refcount;           /* the number of retained regions in buf */
 244         drmBufPtr buf;
 245 };
 246
 247 struct radeon_aos {
 248         struct radeon_bo *bo; /** Buffer object where vertex data is stored */
 249         int offset; /** Offset into buffer object, in bytes */
 250         int components; /** Number of components per vertex */
 251         int stride; /** Stride in dwords (may be 0 for repeating) */
 252         int count; /** Number of vertices */
 253 };
 254
 255 struct radeon_dma {
 256         /* Active dma region.  Allocations for vertices and retained
 257          * regions come from here.  Also used for emitting random vertices,
 258          * these may be flushed by calling flush_current();
 259          */
 260         struct radeon_bo *current; /** Buffer that DMA memory is allocated from */
 261         int current_used; /** Number of bytes allocated and forgotten about */
 262         int current_vertexptr; /** End of active vertex region */
 263
 264         /**
 265          * If current_vertexptr != current_used then flush must be non-zero.
 266          * flush must be called before non-active vertex allocations can be
 267          * performed.
 268          */
 269         void (*flush) (GLcontext *);
 270
 271         /* Number of "in-flight" DMA buffers, i.e. the number of buffers
 272          * for which a DISCARD command is currently queued in the command buffer
 273 .
 274          */
 275         GLuint nr_released_bufs;
 276 };
 277
 278 /* radeon_swtcl.c
 279  */
 280 struct radeon_swtcl_info {
 281
 282         GLuint RenderIndex;
 283         GLuint vertex_size;
 284         GLubyte *verts;
 285
 286         /* Fallback rasterization functions
 287          */
 288         GLuint hw_primitive;
 289         GLenum render_primitive;
 290         GLuint numverts;
 291
 292         struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX];
 293         GLuint vertex_attr_count;
 294
 295 };
 296
 297 #define RADEON_MAX_AOS_ARRAYS           16
 298 struct radeon_tcl_info {
 299         struct radeon_aos aos[RADEON_MAX_AOS_ARRAYS];
 300         GLuint aos_count;
 301         struct radeon_bo *elt_dma_bo; /** Buffer object that contains element indices */
 302         int elt_dma_offset; /** Offset into this buffer object, in bytes */
 303 };
 304
 305 struct radeon_ioctl {
 306         GLuint vertex_offset;
 307         struct radeon_bo *bo;
 308         GLuint vertex_size;
 309 };
 310
 311 #define RADEON_MAX_PRIMS 64
 312
 313 struct radeon_prim {
 314         GLuint start;
 315         GLuint end;
 316         GLuint prim;
 317 };
 318
 319 static INLINE GLuint radeonPackColor(GLuint cpp,
 320                                      GLubyte r, GLubyte g,
 321                                      GLubyte b, GLubyte a)
 322 {
 323         switch (cpp) {
 324         case 2:
 325                 return PACK_COLOR_565(r, g, b);
 326         case 4:
 327                 return PACK_COLOR_8888(a, r, g, b);
 328         default:
 329                 return 0;
 330         }
 331 }
 332
 333 #define MAX_CMD_BUF_SZ (16*1024)
 334
 335 #define MAX_DMA_BUF_SZ (64*1024)
 336
 337 struct radeon_store {
 338         GLuint statenr;
 339         GLuint primnr;
 340         char cmd_buf[MAX_CMD_BUF_SZ];
 341         int cmd_used;
 342         int elts_start;
 343 };
 344
 345 struct radeon_dri_mirror {
 346         __DRIcontextPrivate *context;   /* DRI context */
 347         __DRIscreenPrivate *screen;     /* DRI screen */
 348
 349    /**
 350     * DRI drawable bound to this context for drawing.
 351     */
 352         __DRIdrawablePrivate *drawable;
 353
 354    /**
 355     * DRI drawable bound to this context for reading.
 356     */
 357         __DRIdrawablePrivate *readable;
 358
 359         drm_context_t hwContext;
 360         drm_hw_lock_t *hwLock;
 361         int fd;
 362         int drmMinor;
 363 };
 364
 365 #define DEBUG_TEXTURE   0x001
 366 #define DEBUG_STATE     0x002
 367 #define DEBUG_IOCTL     0x004
 368 #define DEBUG_PRIMS     0x008
 369 #define DEBUG_VERTS     0x010
 370 #define DEBUG_FALLBACKS 0x020
 371 #define DEBUG_VFMT      0x040
 372 #define DEBUG_CODEGEN   0x080
 373 #define DEBUG_VERBOSE   0x100
 374 #define DEBUG_DRI       0x200
 375 #define DEBUG_DMA       0x400
 376 #define DEBUG_SANITY    0x800
 377 #define DEBUG_SYNC      0x1000
 378 #define DEBUG_PIXEL     0x2000
 379 #define DEBUG_MEMORY    0x4000
 380
 381
 382 typedef void (*radeon_tri_func) (radeonContextPtr,
 383                                  radeonVertex *,
 384                                  radeonVertex *, radeonVertex *);
 385
 386 typedef void (*radeon_line_func) (radeonContextPtr,
 387                                   radeonVertex *, radeonVertex *);
 388
 389 typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *);
 390
 391 #define RADEON_MAX_BOS 24
 392 struct radeon_state {
 393         struct radeon_colorbuffer_state color;
 394         struct radeon_depthbuffer_state depth;
 395         struct radeon_scissor_state scissor;
 396         struct radeon_stencilbuffer_state stencil;
 397
 398         struct radeon_cs_space_check bos[RADEON_MAX_BOS];
 399         int validated_bo_count;
 400 };
 401
 402 /**
 403  * This structure holds the command buffer while it is being constructed.
 404  *
 405  * The first batch of commands in the buffer is always the state that needs
 406  * to be re-emitted when the context is lost. This batch can be skipped
 407  * otherwise.
 408  */
 409 struct radeon_cmdbuf {
 410         struct radeon_cs_manager    *csm;
 411         struct radeon_cs            *cs;
 412         int size; /** # of dwords total */
 413         unsigned int flushing:1; /** whether we're currently in FlushCmdBufLocked */
 414 };
 415
 416 struct radeon_context {
 417    GLcontext *glCtx;
 418    radeonScreenPtr radeonScreen;        /* Screen private DRI data */
 419
 420    /* Texture object bookkeeping
 421     */
 422    int                   texture_depth;
 423    float                 initialMaxAnisotropy;
 424    uint32_t              texture_row_align;
 425
 426   struct radeon_dma dma;
 427   struct radeon_hw_state hw;
 428    /* Rasterization and vertex state:
 429     */
 430    GLuint TclFallback;
 431    GLuint Fallback;
 432    GLuint NewGLState;
 433    DECLARE_RENDERINPUTS(tnl_index_bitset);      /* index of bits for last tnl_install_attrs */
 434
 435    /* Drawable, cliprect and scissor information */
 436    GLuint numClipRects; /* Cliprects for the draw buffer */
 437    drm_clip_rect_t *pClipRects;
 438    unsigned int lastStamp;
 439    GLboolean lost_context;
 440    drm_radeon_sarea_t *sarea;   /* Private SAREA data */
 441
 442    /* Mirrors of some DRI state */
 443    struct radeon_dri_mirror dri;
 444
 445    /* Busy waiting */
 446    GLuint do_usleeps;
 447    GLuint do_irqs;
 448    GLuint irqsEmitted;
 449    drm_radeon_irq_wait_t iw;
 450
 451    /* Derived state - for r300 only */
 452    struct radeon_state state;
 453
 454    struct radeon_swtcl_info swtcl;
 455    struct radeon_tcl_info tcl;
 456    /* Configuration cache
 457     */
 458    driOptionCache optionCache;
 459
 460    struct radeon_cmdbuf cmdbuf;
 461
 462   drm_clip_rect_t fboRect;
 463   GLboolean constant_cliprect; /* use for FBO or DRI2 rendering */
 464   GLboolean front_cliprects;
 465
 466   struct {
 467       struct gl_fragment_program *bitmap_fp;
 468       struct gl_vertex_program *passthrough_vp;
 469
 470       struct gl_fragment_program *saved_fp;
 471       GLboolean saved_fp_enable;
 472       struct gl_vertex_program *saved_vp;
 473       GLboolean saved_vp_enable;
 474
 475       GLint saved_vp_x, saved_vp_y;
 476       GLsizei saved_vp_width, saved_vp_height;
 477       GLenum saved_matrix_mode;
 478    } meta;
 479
 480    struct {
 481            void (*get_lock)(radeonContextPtr radeon);
 482            void (*update_viewport_offset)(GLcontext *ctx);
 483            void (*emit_cs_header)(struct radeon_cs *cs, radeonContextPtr rmesa);
 484            void (*swtcl_flush)(GLcontext *ctx, uint32_t offset);
 485            void (*pre_emit_atoms)(radeonContextPtr rmesa);
 486            void (*pre_emit_state)(radeonContextPtr rmesa);
 487            void (*fallback)(GLcontext *ctx, GLuint bit, GLboolean mode);
 488            void (*free_context)(GLcontext *ctx);
 489    } vtbl;
 490 };
 491
 492 #define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx))
 493
 494 /**
 495  * This function takes a float and packs it into a uint32_t
 496  */
 497 static INLINE uint32_t radeonPackFloat32(float fl)
 498 {
 499         union {
 500                 float fl;
 501                 uint32_t u;
 502         } u;
 503
 504         u.fl = fl;
 505         return u.u;
 506 }
 507
 508 /* This is probably wrong for some values, I need to test this
 509  * some more.  Range checking would be a good idea also..
 510  *
 511  * But it works for most things.  I'll fix it later if someone
 512  * else with a better clue doesn't
 513  */
 514 static INLINE uint32_t radeonPackFloat24(float f)
 515 {
 516         float mantissa;
 517         int exponent;
 518         uint32_t float24 = 0;
 519
 520         if (f == 0.0)
 521                 return 0;
 522
 523         mantissa = frexpf(f, &exponent);
 524
 525         /* Handle -ve */
 526         if (mantissa < 0) {
 527                 float24 |= (1 << 23);
 528                 mantissa = mantissa * -1.0;
 529         }
 530         /* Handle exponent, bias of 63 */
 531         exponent += 62;
 532         float24 |= (exponent << 16);
 533         /* Kill 7 LSB of mantissa */
 534         float24 |= (radeonPackFloat32(mantissa) & 0x7FFFFF) >> 7;
 535
 536         return float24;
 537 }
 538
 539 GLboolean radeonInitContext(radeonContextPtr radeon,
 540                             struct dd_function_table* functions,
 541                             const __GLcontextModes * glVisual,
 542                             __DRIcontextPrivate * driContextPriv,
 543                             void *sharedContextPrivate);
 544
 545 void radeonCleanupContext(radeonContextPtr radeon);
 546 GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv);
 547 void radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable);
 548 GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv,
 549                             __DRIdrawablePrivate * driDrawPriv,
 550                             __DRIdrawablePrivate * driReadPriv);
 551 extern void radeonDestroyContext(__DRIcontextPrivate * driContextPriv);
 552
 553 /* ================================================================
 554  * Debugging:
 555  */
 556 #define DO_DEBUG                1
 557
 558 #if DO_DEBUG
 559 extern int RADEON_DEBUG;
 560 #else
 561 #define RADEON_DEBUG            0
 562 #endif
 563
 564 #endif