src/mesa/drivers/dri/radeon/radeon_common_context.h

   1
   2 #ifndef COMMON_CONTEXT_H
   3 #define COMMON_CONTEXT_H
   4
   5 #include "main/mm.h"
   6 #include "math/m_vector.h"
   7 #include "tnl/t_context.h"
   8 #include "main/colormac.h"
   9
  10 #include "radeon_debug.h"
  11 #include "radeon_screen.h"
  12 #include "radeon_drm.h"
  13 #include "dri_util.h"
  14 #include "tnl/t_vertex.h"
  15 #include "swrast/s_context.h"
  16
  17 struct radeon_context;
  18
  19 #include "radeon_bo_gem.h"
  20 #include "radeon_cs_gem.h"
  21
  22 /* This union is used to avoid warnings/miscompilation
  23    with float to uint32_t casts due to strict-aliasing */
  24 typedef union { GLfloat f; uint32_t ui32; } float_ui32_type;
  25
  26 struct radeon_context;
  27 typedef struct radeon_context radeonContextRec;
  28 typedef struct radeon_context *radeonContextPtr;
  29
  30
  31 #define TEX_0   0x1
  32 #define TEX_1   0x2
  33 #define TEX_2   0x4
  34 #define TEX_3   0x8
  35 #define TEX_4   0x10
  36 #define TEX_5   0x20
  37
  38 /* Rasterizing fallbacks */
  39 /* See correponding strings in r200_swtcl.c */
  40 #define RADEON_FALLBACK_TEXTURE         0x0001
  41 #define RADEON_FALLBACK_DRAW_BUFFER     0x0002
  42 #define RADEON_FALLBACK_STENCIL         0x0004
  43 #define RADEON_FALLBACK_RENDER_MODE     0x0008
  44 #define RADEON_FALLBACK_BLEND_EQ        0x0010
  45 #define RADEON_FALLBACK_BLEND_FUNC      0x0020
  46 #define RADEON_FALLBACK_DISABLE         0x0040
  47 #define RADEON_FALLBACK_BORDER_MODE     0x0080
  48 #define RADEON_FALLBACK_DEPTH_BUFFER    0x0100
  49 #define RADEON_FALLBACK_STENCIL_BUFFER  0x0200
  50
  51 #define R200_FALLBACK_TEXTURE           0x01
  52 #define R200_FALLBACK_DRAW_BUFFER       0x02
  53 #define R200_FALLBACK_STENCIL           0x04
  54 #define R200_FALLBACK_RENDER_MODE       0x08
  55 #define R200_FALLBACK_DISABLE           0x10
  56 #define R200_FALLBACK_BORDER_MODE       0x20
  57
  58 #define RADEON_TCL_FALLBACK_RASTER            0x1 /* rasterization */
  59 #define RADEON_TCL_FALLBACK_UNFILLED          0x2 /* unfilled tris */
  60 #define RADEON_TCL_FALLBACK_LIGHT_TWOSIDE     0x4 /* twoside tris */
  61 #define RADEON_TCL_FALLBACK_MATERIAL          0x8 /* material in vb */
  62 #define RADEON_TCL_FALLBACK_TEXGEN_0          0x10 /* texgen, unit 0 */
  63 #define RADEON_TCL_FALLBACK_TEXGEN_1          0x20 /* texgen, unit 1 */
  64 #define RADEON_TCL_FALLBACK_TEXGEN_2          0x40 /* texgen, unit 2 */
  65 #define RADEON_TCL_FALLBACK_TCL_DISABLE       0x80 /* user disable */
  66 #define RADEON_TCL_FALLBACK_FOGCOORDSPEC      0x100 /* fogcoord, sep. spec light */
  67
  68 /* The blit width for texture uploads
  69  */
  70 #define BLIT_WIDTH_BYTES 1024
  71
  72 /* Use the templated vertex format:
  73  */
  74 #define COLOR_IS_RGBA
  75 #define TAG(x) radeon##x
  76 #include "tnl_dd/t_dd_vertex.h"
  77 #undef TAG
  78
  79 #define RADEON_RB_CLASS 0xdeadbeef
  80
  81 struct radeon_renderbuffer
  82 {
  83         struct gl_renderbuffer base;
  84         struct radeon_bo *bo;
  85         unsigned int cpp;
  86         /* unsigned int offset; */
  87         unsigned int pitch;
  88
  89         struct radeon_bo *map_bo;
  90         GLbitfield map_mode;
  91         int map_x, map_y, map_w, map_h;
  92         int map_pitch;
  93         void *map_buffer;
  94
  95         uint32_t draw_offset; /* FBO */
  96         /* boo Xorg 6.8.2 compat */
  97         int has_surface;
  98
  99         GLuint pf_pending;  /**< sequence number of pending flip */
 100         __DRIdrawable *dPriv;
 101 };
 102
 103 struct radeon_framebuffer
 104 {
 105         struct gl_framebuffer base;
 106
 107         struct radeon_renderbuffer *color_rb[2];
 108 };
 109
 110
 111 struct radeon_colorbuffer_state {
 112         GLuint clear;
 113         int roundEnable;
 114         struct gl_renderbuffer *rb;
 115         uint32_t draw_offset; /* offset into color renderbuffer - FBOs */
 116 };
 117
 118 struct radeon_depthbuffer_state {
 119         GLuint clear;
 120         struct gl_renderbuffer *rb;
 121 };
 122
 123 struct radeon_scissor_state {
 124         drm_clip_rect_t rect;
 125         GLboolean enabled;
 126
 127         GLuint numClipRects;    /* Cliprects active */
 128         GLuint numAllocedClipRects;     /* Cliprects available */
 129         drm_clip_rect_t *pClipRects;
 130 };
 131
 132 struct radeon_stencilbuffer_state {
 133         GLuint clear;           /* rb3d_stencilrefmask value */
 134 };
 135
 136 struct radeon_state_atom {
 137         struct radeon_state_atom *next, *prev;
 138         const char *name;       /* for debug */
 139         int cmd_size;           /* size in bytes */
 140         GLuint idx;
 141         GLuint is_tcl;
 142         GLuint *cmd;            /* one or more cmd's */
 143         GLuint *lastcmd;                /* one or more cmd's */
 144         GLboolean dirty;        /* dirty-mark in emit_state_list */
 145         int (*check) (struct gl_context *, struct radeon_state_atom *atom); /* is this state active? */
 146         void (*emit) (struct gl_context *, struct radeon_state_atom *atom);
 147 };
 148
 149 struct radeon_hw_state {
 150         /* Head of the linked list of state atoms. */
 151         struct radeon_state_atom atomlist;
 152         int max_state_size;     /* Number of bytes necessary for a full state emit. */
 153         int max_post_flush_size; /* Number of bytes necessary for post flushing emits */
 154         GLboolean is_dirty, all_dirty;
 155 };
 156
 157
 158 /* Texture related */
 159 typedef struct _radeon_texture_image radeon_texture_image;
 160
 161
 162 /**
 163  * This is a subclass of swrast_texture_image since we use swrast
 164  * for software fallback rendering.
 165  */
 166 struct _radeon_texture_image {
 167         struct swrast_texture_image base;
 168
 169         /**
 170          * If mt != 0, the image is stored in hardware format in the
 171          * given mipmap tree. In this case, base.Data may point into the
 172          * mapping of the buffer object that contains the mipmap tree.
 173          *
 174          * If mt == 0, the image is stored in normal memory pointed to
 175          * by base.Data.
 176          */
 177         struct _radeon_mipmap_tree *mt;
 178         struct radeon_bo *bo;
 179         GLboolean used_as_render_target;
 180 };
 181
 182
 183 static INLINE radeon_texture_image *get_radeon_texture_image(struct gl_texture_image *image)
 184 {
 185         return (radeon_texture_image*)image;
 186 }
 187
 188
 189 typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr;
 190
 191 #define RADEON_TXO_MICRO_TILE               (1 << 3)
 192
 193 /* Texture object in locally shared texture space.
 194  */
 195 struct radeon_tex_obj {
 196         struct gl_texture_object base;
 197         struct _radeon_mipmap_tree *mt;
 198
 199         /**
 200          * This is true if we've verified that the mipmap tree above is complete
 201          * and so on.
 202          */
 203         GLboolean validated;
 204         /* Minimum LOD to be used during rendering */
 205         unsigned minLod;
 206         /* Miximum LOD to be used during rendering */
 207         unsigned maxLod;
 208
 209         GLuint override_offset;
 210         GLboolean image_override; /* Image overridden by GLX_EXT_tfp */
 211         GLuint tile_bits;       /* hw texture tile bits used on this texture */
 212         struct radeon_bo *bo;
 213
 214         GLuint pp_txfilter;     /* hardware register values */
 215         GLuint pp_txformat;
 216         GLuint pp_txformat_x;
 217         GLuint pp_txsize;       /* npot only */
 218         GLuint pp_txpitch;      /* npot only */
 219         GLuint pp_border_color;
 220         GLuint pp_cubic_faces;  /* cube face 1,2,3,4 log2 sizes */
 221
 222         GLboolean border_fallback;
 223 };
 224
 225 static INLINE radeonTexObj* radeon_tex_obj(struct gl_texture_object *texObj)
 226 {
 227         return (radeonTexObj*)texObj;
 228 }
 229
 230 /* occlusion query */
 231 struct radeon_query_object {
 232         struct gl_query_object Base;
 233         struct radeon_bo *bo;
 234         int curr_offset;
 235         GLboolean emitted_begin;
 236
 237         /* Double linked list of not flushed query objects */
 238         struct radeon_query_object *prev, *next;
 239 };
 240
 241 /* Need refcounting on dma buffers:
 242  */
 243 struct radeon_dma_buffer {
 244         int refcount;           /* the number of retained regions in buf */
 245         drmBufPtr buf;
 246 };
 247
 248 struct radeon_aos {
 249         struct radeon_bo *bo; /** Buffer object where vertex data is stored */
 250         int offset; /** Offset into buffer object, in bytes */
 251         int components; /** Number of components per vertex */
 252         int stride; /** Stride in dwords (may be 0 for repeating) */
 253         int count; /** Number of vertices */
 254 };
 255
 256 #define DMA_BO_FREE_TIME 100
 257
 258 struct radeon_dma_bo {
 259   struct radeon_dma_bo *next, *prev;
 260   struct radeon_bo *bo;
 261   int expire_counter;
 262 };
 263
 264 struct radeon_dma {
 265         /* Active dma region.  Allocations for vertices and retained
 266          * regions come from here.  Also used for emitting random vertices,
 267          * these may be flushed by calling flush_current();
 268          */
 269         struct radeon_dma_bo free;
 270         struct radeon_dma_bo wait;
 271         struct radeon_dma_bo reserved;
 272         size_t current_used; /** Number of bytes allocated and forgotten about */
 273         size_t current_vertexptr; /** End of active vertex region */
 274         size_t minimum_size;
 275
 276         /**
 277          * If current_vertexptr != current_used then flush must be non-zero.
 278          * flush must be called before non-active vertex allocations can be
 279          * performed.
 280          */
 281         void (*flush) (struct gl_context *);
 282 };
 283
 284 /* radeon_swtcl.c
 285  */
 286 struct radeon_swtcl_info {
 287
 288         GLuint RenderIndex;
 289         GLuint vertex_size;
 290         GLubyte *verts;
 291
 292         /* Fallback rasterization functions
 293          */
 294         GLuint hw_primitive;
 295         GLenum render_primitive;
 296         GLuint numverts;
 297
 298         struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX];
 299         GLuint vertex_attr_count;
 300
 301         GLuint emit_prediction;
 302         struct radeon_bo *bo;
 303 };
 304
 305 #define RADEON_MAX_AOS_ARRAYS           16
 306 struct radeon_tcl_info {
 307         struct radeon_aos aos[RADEON_MAX_AOS_ARRAYS];
 308         GLuint aos_count;
 309         struct radeon_bo *elt_dma_bo; /** Buffer object that contains element indices */
 310         int elt_dma_offset; /** Offset into this buffer object, in bytes */
 311 };
 312
 313 struct radeon_ioctl {
 314         GLuint vertex_offset;
 315         GLuint vertex_max;
 316         struct radeon_bo *bo;
 317         GLuint vertex_size;
 318 };
 319
 320 #define RADEON_MAX_PRIMS 64
 321
 322 struct radeon_prim {
 323         GLuint start;
 324         GLuint end;
 325         GLuint prim;
 326 };
 327
 328 static INLINE GLuint radeonPackColor(GLuint cpp,
 329                                      GLubyte r, GLubyte g,
 330                                      GLubyte b, GLubyte a)
 331 {
 332         switch (cpp) {
 333         case 2:
 334                 return PACK_COLOR_565(r, g, b);
 335         case 4:
 336                 return PACK_COLOR_8888(a, r, g, b);
 337         default:
 338                 return 0;
 339         }
 340 }
 341
 342 #define MAX_CMD_BUF_SZ (16*1024)
 343
 344 #define MAX_DMA_BUF_SZ (64*1024)
 345
 346 struct radeon_store {
 347         GLuint statenr;
 348         GLuint primnr;
 349         char cmd_buf[MAX_CMD_BUF_SZ];
 350         int cmd_used;
 351         int elts_start;
 352 };
 353
 354 struct radeon_dri_mirror {
 355         __DRIcontext *context;  /* DRI context */
 356         __DRIscreen *screen;    /* DRI screen */
 357
 358         drm_context_t hwContext;
 359         drm_hw_lock_t *hwLock;
 360         int hwLockCount;
 361         int fd;
 362         int drmMinor;
 363 };
 364
 365 typedef void (*radeon_tri_func) (radeonContextPtr,
 366                                  radeonVertex *,
 367                                  radeonVertex *, radeonVertex *);
 368
 369 typedef void (*radeon_line_func) (radeonContextPtr,
 370                                   radeonVertex *, radeonVertex *);
 371
 372 typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *);
 373
 374 #define RADEON_MAX_BOS 32
 375 struct radeon_state {
 376         struct radeon_colorbuffer_state color;
 377         struct radeon_depthbuffer_state depth;
 378         struct radeon_scissor_state scissor;
 379         struct radeon_stencilbuffer_state stencil;
 380 };
 381
 382 /**
 383  * This structure holds the command buffer while it is being constructed.
 384  *
 385  * The first batch of commands in the buffer is always the state that needs
 386  * to be re-emitted when the context is lost. This batch can be skipped
 387  * otherwise.
 388  */
 389 struct radeon_cmdbuf {
 390         struct radeon_cs_manager    *csm;
 391         struct radeon_cs            *cs;
 392         int size; /** # of dwords total */
 393         unsigned int flushing:1; /** whether we're currently in FlushCmdBufLocked */
 394 };
 395
 396 struct radeon_context {
 397    struct gl_context *glCtx;
 398    radeonScreenPtr radeonScreen;        /* Screen private DRI data */
 399
 400    /* Texture object bookkeeping
 401     */
 402    int                   texture_depth;
 403    float                 initialMaxAnisotropy;
 404    uint32_t              texture_row_align;
 405    uint32_t              texture_rect_row_align;
 406    uint32_t              texture_compressed_row_align;
 407
 408   struct radeon_dma dma;
 409   struct radeon_hw_state hw;
 410    /* Rasterization and vertex state:
 411     */
 412    GLuint TclFallback;
 413    GLuint Fallback;
 414    GLuint NewGLState;
 415    GLbitfield64 tnl_index_bitset;       /* index of bits for last tnl_install_attrs */
 416
 417    /* Drawable information */
 418    unsigned int lastStamp;
 419    drm_radeon_sarea_t *sarea;   /* Private SAREA data */
 420
 421    /* Mirrors of some DRI state */
 422    struct radeon_dri_mirror dri;
 423
 424    /* Busy waiting */
 425    GLuint do_usleeps;
 426    GLuint do_irqs;
 427    GLuint irqsEmitted;
 428    drm_radeon_irq_wait_t iw;
 429
 430    /* Derived state - for r300 only */
 431    struct radeon_state state;
 432
 433    struct radeon_swtcl_info swtcl;
 434    struct radeon_tcl_info tcl;
 435    /* Configuration cache
 436     */
 437    driOptionCache optionCache;
 438
 439    struct radeon_cmdbuf cmdbuf;
 440
 441    struct radeon_debug debug;
 442
 443   drm_clip_rect_t fboRect;
 444   GLboolean front_cliprects;
 445
 446    /**
 447     * Set if rendering has occured to the drawable's front buffer.
 448     *
 449     * This is used in the DRI2 case to detect that glFlush should also copy
 450     * the contents of the fake front buffer to the real front buffer.
 451     */
 452    GLboolean front_buffer_dirty;
 453
 454    /**
 455     * Track whether front-buffer rendering is currently enabled
 456     *
 457     * A separate flag is used to track this in order to support MRT more
 458     * easily.
 459     */
 460    GLboolean is_front_buffer_rendering;
 461
 462    /**
 463     * Track whether front-buffer is the current read target.
 464     *
 465     * This is closely associated with is_front_buffer_rendering, but may
 466     * be set separately.  The DRI2 fake front buffer must be referenced
 467     * either way.
 468     */
 469    GLboolean is_front_buffer_reading;
 470
 471    struct {
 472         struct radeon_query_object *current;
 473         struct radeon_state_atom queryobj;
 474    } query;
 475
 476    struct {
 477            void (*get_lock)(radeonContextPtr radeon);
 478            void (*update_viewport_offset)(struct gl_context *ctx);
 479            void (*emit_cs_header)(struct radeon_cs *cs, radeonContextPtr rmesa);
 480            void (*swtcl_flush)(struct gl_context *ctx, uint32_t offset);
 481            void (*pre_emit_atoms)(radeonContextPtr rmesa);
 482            void (*pre_emit_state)(radeonContextPtr rmesa);
 483            void (*fallback)(struct gl_context *ctx, GLuint bit, GLboolean mode);
 484            void (*free_context)(struct gl_context *ctx);
 485            void (*emit_query_finish)(radeonContextPtr radeon);
 486            void (*update_scissor)(struct gl_context *ctx);
 487            unsigned (*check_blit)(gl_format mesa_format, uint32_t dst_pitch);
 488            unsigned (*blit)(struct gl_context *ctx,
 489                         struct radeon_bo *src_bo,
 490                         intptr_t src_offset,
 491                         gl_format src_mesaformat,
 492                         unsigned src_pitch,
 493                         unsigned src_width,
 494                         unsigned src_height,
 495                         unsigned src_x_offset,
 496                         unsigned src_y_offset,
 497                         struct radeon_bo *dst_bo,
 498                         intptr_t dst_offset,
 499                         gl_format dst_mesaformat,
 500                         unsigned dst_pitch,
 501                         unsigned dst_width,
 502                         unsigned dst_height,
 503                         unsigned dst_x_offset,
 504                         unsigned dst_y_offset,
 505                         unsigned reg_width,
 506                         unsigned reg_height,
 507                         unsigned flip_y);
 508            unsigned (*is_format_renderable)(gl_format mesa_format);
 509    } vtbl;
 510 };
 511
 512 #define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx))
 513
 514 static inline __DRIdrawable* radeon_get_drawable(radeonContextPtr radeon)
 515 {
 516         return radeon->dri.context->driDrawablePriv;
 517 }
 518
 519 static inline __DRIdrawable* radeon_get_readable(radeonContextPtr radeon)
 520 {
 521         return radeon->dri.context->driReadablePriv;
 522 }
 523
 524 GLboolean radeonInitContext(radeonContextPtr radeon,
 525                             struct dd_function_table* functions,
 526                             const struct gl_config * glVisual,
 527                             __DRIcontext * driContextPriv,
 528                             void *sharedContextPrivate);
 529
 530 void radeonCleanupContext(radeonContextPtr radeon);
 531 GLboolean radeonUnbindContext(__DRIcontext * driContextPriv);
 532 void radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable,
 533                                  GLboolean front_only);
 534 GLboolean radeonMakeCurrent(__DRIcontext * driContextPriv,
 535                             __DRIdrawable * driDrawPriv,
 536                             __DRIdrawable * driReadPriv);
 537 extern void radeonDestroyContext(__DRIcontext * driContextPriv);
 538 void radeon_prepare_render(radeonContextPtr radeon);
 539
 540 #endif