src/mesa/drivers/dri/radeon/radeon_common_context.h

   1
   2 #ifndef COMMON_CONTEXT_H
   3 #define COMMON_CONTEXT_H
   4
   5 #include "main/mm.h"
   6 #include "math/m_vector.h"
   7 #include "texmem.h"
   8 #include "tnl/t_context.h"
   9 #include "main/colormac.h"
  10
  11 #include "radeon_screen.h"
  12 #include "radeon_drm.h"
  13 #include "dri_util.h"
  14 #include "tnl/t_vertex.h"
  15
  16 /* This union is used to avoid warnings/miscompilation
  17    with float to uint32_t casts due to strict-aliasing */
  18 typedef union { GLfloat f; uint32_t ui32; } float_ui32_type;
  19
  20 struct radeon_context;
  21 typedef struct radeon_context radeonContextRec;
  22 typedef struct radeon_context *radeonContextPtr;
  23
  24
  25 #define TEX_0   0x1
  26 #define TEX_1   0x2
  27 #define TEX_2   0x4
  28 #define TEX_3   0x8
  29 #define TEX_4   0x10
  30 #define TEX_5   0x20
  31
  32 /* Rasterizing fallbacks */
  33 /* See correponding strings in r200_swtcl.c */
  34 #define RADEON_FALLBACK_TEXTURE         0x0001
  35 #define RADEON_FALLBACK_DRAW_BUFFER     0x0002
  36 #define RADEON_FALLBACK_STENCIL         0x0004
  37 #define RADEON_FALLBACK_RENDER_MODE     0x0008
  38 #define RADEON_FALLBACK_BLEND_EQ        0x0010
  39 #define RADEON_FALLBACK_BLEND_FUNC      0x0020
  40 #define RADEON_FALLBACK_DISABLE         0x0040
  41 #define RADEON_FALLBACK_BORDER_MODE     0x0080
  42
  43 #define R200_FALLBACK_TEXTURE           0x01
  44 #define R200_FALLBACK_DRAW_BUFFER       0x02
  45 #define R200_FALLBACK_STENCIL           0x04
  46 #define R200_FALLBACK_RENDER_MODE       0x08
  47 #define R200_FALLBACK_DISABLE           0x10
  48 #define R200_FALLBACK_BORDER_MODE       0x20
  49
  50 #define RADEON_TCL_FALLBACK_RASTER            0x1 /* rasterization */
  51 #define RADEON_TCL_FALLBACK_UNFILLED          0x2 /* unfilled tris */
  52 #define RADEON_TCL_FALLBACK_LIGHT_TWOSIDE     0x4 /* twoside tris */
  53 #define RADEON_TCL_FALLBACK_MATERIAL          0x8 /* material in vb */
  54 #define RADEON_TCL_FALLBACK_TEXGEN_0          0x10 /* texgen, unit 0 */
  55 #define RADEON_TCL_FALLBACK_TEXGEN_1          0x20 /* texgen, unit 1 */
  56 #define RADEON_TCL_FALLBACK_TEXGEN_2          0x40 /* texgen, unit 2 */
  57 #define RADEON_TCL_FALLBACK_TCL_DISABLE       0x80 /* user disable */
  58 #define RADEON_TCL_FALLBACK_FOGCOORDSPEC      0x100 /* fogcoord, sep. spec light */
  59
  60 /* The blit width for texture uploads
  61  */
  62 #define BLIT_WIDTH_BYTES 1024
  63
  64 /* Use the templated vertex format:
  65  */
  66 #define COLOR_IS_RGBA
  67 #define TAG(x) radeon##x
  68 #include "tnl_dd/t_dd_vertex.h"
  69 #undef TAG
  70
  71 struct radeon_renderbuffer
  72 {
  73         struct gl_renderbuffer base;
  74         struct radeon_bo *bo;
  75         unsigned int cpp;
  76         /* unsigned int offset; */
  77         unsigned int pitch;
  78         unsigned int width;
  79         unsigned int height;
  80
  81         /* boo Xorg 6.8.2 compat */
  82         int has_surface;
  83
  84         __DRIdrawablePrivate *dPriv;
  85 };
  86
  87 struct radeon_colorbuffer_state {
  88         GLuint clear;
  89         int roundEnable;
  90         struct radeon_renderbuffer *rrb;
  91 };
  92
  93 struct radeon_depthbuffer_state {
  94         GLuint clear;
  95         GLfloat scale;
  96         struct radeon_renderbuffer *rrb;
  97 };
  98
  99 struct radeon_scissor_state {
 100         drm_clip_rect_t rect;
 101         GLboolean enabled;
 102
 103         GLuint numClipRects;    /* Cliprects active */
 104         GLuint numAllocedClipRects;     /* Cliprects available */
 105         drm_clip_rect_t *pClipRects;
 106 };
 107
 108 struct radeon_stencilbuffer_state {
 109         GLboolean hwBuffer;
 110         GLuint clear;           /* rb3d_stencilrefmask value */
 111 };
 112
 113 struct radeon_stipple_state {
 114         GLuint mask[32];
 115 };
 116
 117 struct radeon_state_atom {
 118         struct radeon_state_atom *next, *prev;
 119         const char *name;       /* for debug */
 120         int cmd_size;           /* size in bytes */
 121         GLuint idx;
 122         GLuint is_tcl;
 123         GLuint *cmd;            /* one or more cmd's */
 124         GLuint *lastcmd;                /* one or more cmd's */
 125         GLboolean dirty;        /* dirty-mark in emit_state_list */
 126         int (*check) (GLcontext *, struct radeon_state_atom *atom); /* is this state active? */
 127         void (*emit) (GLcontext *, struct radeon_state_atom *atom);
 128 };
 129
 130 struct radeon_hw_state {
 131         /* Head of the linked list of state atoms. */
 132         struct radeon_state_atom atomlist;
 133         int max_state_size;     /* Number of bytes necessary for a full state emit. */
 134         GLboolean is_dirty, all_dirty;
 135 };
 136
 137
 138 /* Texture related */
 139 typedef struct _radeon_texture_image radeon_texture_image;
 140
 141 struct _radeon_texture_image {
 142         struct gl_texture_image base;
 143
 144         /**
 145          * If mt != 0, the image is stored in hardware format in the
 146          * given mipmap tree. In this case, base.Data may point into the
 147          * mapping of the buffer object that contains the mipmap tree.
 148          *
 149          * If mt == 0, the image is stored in normal memory pointed to
 150          * by base.Data.
 151          */
 152         struct _radeon_mipmap_tree *mt;
 153         struct radeon_bo *bo;
 154
 155         int mtlevel; /** if mt != 0, this is the image's level in the mipmap tree */
 156         int mtface; /** if mt != 0, this is the image's face in the mipmap tree */
 157 };
 158
 159
 160 static INLINE radeon_texture_image *get_radeon_texture_image(struct gl_texture_image *image)
 161 {
 162         return (radeon_texture_image*)image;
 163 }
 164
 165
 166 typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr;
 167
 168 #define RADEON_TXO_MICRO_TILE               (1 << 3)
 169
 170 /* Texture object in locally shared texture space.
 171  */
 172 struct radeon_tex_obj {
 173         struct gl_texture_object base;
 174         struct _radeon_mipmap_tree *mt;
 175
 176         /**
 177          * This is true if we've verified that the mipmap tree above is complete
 178          * and so on.
 179          */
 180         GLboolean validated;
 181
 182         GLuint override_offset;
 183         GLboolean image_override; /* Image overridden by GLX_EXT_tfp */
 184         GLuint tile_bits;       /* hw texture tile bits used on this texture */
 185         struct radeon_bo *bo;
 186
 187         GLuint pp_txfilter;     /* hardware register values */
 188         GLuint pp_txformat;
 189         GLuint pp_txformat_x;
 190         GLuint pp_txsize;       /* npot only */
 191         GLuint pp_txpitch;      /* npot only */
 192         GLuint pp_border_color;
 193         GLuint pp_cubic_faces;  /* cube face 1,2,3,4 log2 sizes */
 194
 195         GLuint pp_txfilter_1;   /*  r300 */
 196
 197         GLboolean border_fallback;
 198
 199
 200 };
 201
 202 static INLINE radeonTexObj* radeon_tex_obj(struct gl_texture_object *texObj)
 203 {
 204         return (radeonTexObj*)texObj;
 205 }
 206
 207 /* Need refcounting on dma buffers:
 208  */
 209 struct radeon_dma_buffer {
 210         int refcount;           /* the number of retained regions in buf */
 211         drmBufPtr buf;
 212 };
 213
 214 struct radeon_aos {
 215         struct radeon_bo *bo; /** Buffer object where vertex data is stored */
 216         int offset; /** Offset into buffer object, in bytes */
 217         int components; /** Number of components per vertex */
 218         int stride; /** Stride in dwords (may be 0 for repeating) */
 219         int count; /** Number of vertices */
 220 };
 221
 222 struct radeon_dma {
 223         /* Active dma region.  Allocations for vertices and retained
 224          * regions come from here.  Also used for emitting random vertices,
 225          * these may be flushed by calling flush_current();
 226          */
 227         struct radeon_bo *current; /** Buffer that DMA memory is allocated from */
 228         int current_used; /** Number of bytes allocated and forgotten about */
 229         int current_vertexptr; /** End of active vertex region */
 230
 231         /**
 232          * If current_vertexptr != current_used then flush must be non-zero.
 233          * flush must be called before non-active vertex allocations can be
 234          * performed.
 235          */
 236         void (*flush) (GLcontext *);
 237
 238         /* Number of "in-flight" DMA buffers, i.e. the number of buffers
 239          * for which a DISCARD command is currently queued in the command buffer
 240 .
 241          */
 242         GLuint nr_released_bufs;
 243 };
 244
 245 /* radeon_swtcl.c
 246  */
 247 struct radeon_swtcl_info {
 248
 249         GLuint RenderIndex;
 250         GLuint vertex_size;
 251         GLubyte *verts;
 252
 253         /* Fallback rasterization functions
 254          */
 255         GLuint hw_primitive;
 256         GLenum render_primitive;
 257         GLuint numverts;
 258
 259         struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX];
 260         GLuint vertex_attr_count;
 261
 262 };
 263
 264 struct radeon_ioctl {
 265         GLuint vertex_offset;
 266         struct radeon_bo *bo;
 267         GLuint vertex_size;
 268 };
 269
 270 #define RADEON_MAX_PRIMS 64
 271
 272 struct radeon_prim {
 273         GLuint start;
 274         GLuint end;
 275         GLuint prim;
 276 };
 277
 278 static INLINE GLuint radeonPackColor(GLuint cpp,
 279                                      GLubyte r, GLubyte g,
 280                                      GLubyte b, GLubyte a)
 281 {
 282         switch (cpp) {
 283         case 2:
 284                 return PACK_COLOR_565(r, g, b);
 285         case 4:
 286                 return PACK_COLOR_8888(a, r, g, b);
 287         default:
 288                 return 0;
 289         }
 290 }
 291
 292 #define MAX_CMD_BUF_SZ (16*1024)
 293
 294 #define MAX_DMA_BUF_SZ (64*1024)
 295
 296 struct radeon_store {
 297         GLuint statenr;
 298         GLuint primnr;
 299         char cmd_buf[MAX_CMD_BUF_SZ];
 300         int cmd_used;
 301         int elts_start;
 302 };
 303
 304 struct radeon_dri_mirror {
 305         __DRIcontextPrivate *context;   /* DRI context */
 306         __DRIscreenPrivate *screen;     /* DRI screen */
 307
 308    /**
 309     * DRI drawable bound to this context for drawing.
 310     */
 311         __DRIdrawablePrivate *drawable;
 312
 313    /**
 314     * DRI drawable bound to this context for reading.
 315     */
 316         __DRIdrawablePrivate *readable;
 317
 318         drm_context_t hwContext;
 319         drm_hw_lock_t *hwLock;
 320         int fd;
 321         int drmMinor;
 322 };
 323
 324 #define DEBUG_TEXTURE   0x001
 325 #define DEBUG_STATE     0x002
 326 #define DEBUG_IOCTL     0x004
 327 #define DEBUG_PRIMS     0x008
 328 #define DEBUG_VERTS     0x010
 329 #define DEBUG_FALLBACKS 0x020
 330 #define DEBUG_VFMT      0x040
 331 #define DEBUG_CODEGEN   0x080
 332 #define DEBUG_VERBOSE   0x100
 333 #define DEBUG_DRI       0x200
 334 #define DEBUG_DMA       0x400
 335 #define DEBUG_SANITY    0x800
 336 #define DEBUG_SYNC      0x1000
 337 #define DEBUG_PIXEL     0x2000
 338 #define DEBUG_MEMORY    0x4000
 339
 340
 341
 342 typedef void (*radeon_tri_func) (radeonContextPtr,
 343                                  radeonVertex *,
 344                                  radeonVertex *, radeonVertex *);
 345
 346 typedef void (*radeon_line_func) (radeonContextPtr,
 347                                   radeonVertex *, radeonVertex *);
 348
 349 typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *);
 350
 351 struct radeon_state {
 352         struct radeon_colorbuffer_state color;
 353         struct radeon_depthbuffer_state depth;
 354         struct radeon_scissor_state scissor;
 355         struct radeon_stencilbuffer_state stencil;
 356 };
 357
 358 /**
 359  * This structure holds the command buffer while it is being constructed.
 360  *
 361  * The first batch of commands in the buffer is always the state that needs
 362  * to be re-emitted when the context is lost. This batch can be skipped
 363  * otherwise.
 364  */
 365 struct radeon_cmdbuf {
 366         struct radeon_cs_manager    *csm;
 367         struct radeon_cs            *cs;
 368         int size; /** # of dwords total */
 369         unsigned int flushing:1; /** whether we're currently in FlushCmdBufLocked */
 370 };
 371
 372 struct radeon_context {
 373    GLcontext *glCtx;
 374    radeonScreenPtr radeonScreen;        /* Screen private DRI data */
 375
 376    /* Texture object bookkeeping
 377     */
 378    int                   texture_depth;
 379    float                 initialMaxAnisotropy;
 380
 381   struct radeon_dma dma;
 382   struct radeon_hw_state hw;
 383    /* Rasterization and vertex state:
 384     */
 385    GLuint TclFallback;
 386    GLuint Fallback;
 387    GLuint NewGLState;
 388    DECLARE_RENDERINPUTS(tnl_index_bitset);      /* index of bits for last tnl_install_attrs */
 389
 390    /* Page flipping */
 391    GLuint doPageFlip;
 392
 393    /* Drawable, cliprect and scissor information */
 394    GLuint numClipRects; /* Cliprects for the draw buffer */
 395    drm_clip_rect_t *pClipRects;
 396    unsigned int lastStamp;
 397    GLboolean lost_context;
 398    drm_radeon_sarea_t *sarea;   /* Private SAREA data */
 399
 400    /* Mirrors of some DRI state */
 401    struct radeon_dri_mirror dri;
 402
 403    /* Busy waiting */
 404    GLuint do_usleeps;
 405    GLuint do_irqs;
 406    GLuint irqsEmitted;
 407    drm_radeon_irq_wait_t iw;
 408
 409    /* buffer swap */
 410    int64_t swap_ust;
 411    int64_t swap_missed_ust;
 412
 413    GLuint swap_count;
 414    GLuint swap_missed_count;
 415
 416    /* Derived state - for r300 only */
 417    struct radeon_state state;
 418
 419    struct radeon_swtcl_info swtcl;
 420    /* Configuration cache
 421     */
 422    driOptionCache optionCache;
 423
 424    struct radeon_cmdbuf cmdbuf;
 425
 426    struct {
 427            void (*get_lock)(radeonContextPtr radeon);
 428            void (*update_viewport_offset)(GLcontext *ctx);
 429            void (*update_draw_buffer)(GLcontext *ctx);
 430            void (*emit_cs_header)(struct radeon_cs *cs, radeonContextPtr rmesa);
 431            void (*swtcl_flush)(GLcontext *ctx, uint32_t offset);
 432            void (*pre_emit_atoms)(radeonContextPtr rmesa);
 433            void (*pre_emit_state)(radeonContextPtr rmesa);
 434    } vtbl;
 435 };
 436
 437 #define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx))
 438
 439 /**
 440  * This function takes a float and packs it into a uint32_t
 441  */
 442 static INLINE uint32_t radeonPackFloat32(float fl)
 443 {
 444         union {
 445                 float fl;
 446                 uint32_t u;
 447         } u;
 448
 449         u.fl = fl;
 450         return u.u;
 451 }
 452
 453 /* This is probably wrong for some values, I need to test this
 454  * some more.  Range checking would be a good idea also..
 455  *
 456  * But it works for most things.  I'll fix it later if someone
 457  * else with a better clue doesn't
 458  */
 459 static INLINE uint32_t radeonPackFloat24(float f)
 460 {
 461         float mantissa;
 462         int exponent;
 463         uint32_t float24 = 0;
 464
 465         if (f == 0.0)
 466                 return 0;
 467
 468         mantissa = frexpf(f, &exponent);
 469
 470         /* Handle -ve */
 471         if (mantissa < 0) {
 472                 float24 |= (1 << 23);
 473                 mantissa = mantissa * -1.0;
 474         }
 475         /* Handle exponent, bias of 63 */
 476         exponent += 62;
 477         float24 |= (exponent << 16);
 478         /* Kill 7 LSB of mantissa */
 479         float24 |= (radeonPackFloat32(mantissa) & 0x7FFFFF) >> 7;
 480
 481         return float24;
 482 }
 483
 484 GLboolean radeonInitContext(radeonContextPtr radeon,
 485                             struct dd_function_table* functions,
 486                             const __GLcontextModes * glVisual,
 487                             __DRIcontextPrivate * driContextPriv,
 488                             void *sharedContextPrivate);
 489
 490 void radeonCleanupContext(radeonContextPtr radeon);
 491 GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv);
 492 void radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable);
 493 GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv,
 494                             __DRIdrawablePrivate * driDrawPriv,
 495                             __DRIdrawablePrivate * driReadPriv);
 496
 497 /* ================================================================
 498  * Debugging:
 499  */
 500 #define DO_DEBUG                1
 501
 502 #if DO_DEBUG
 503 extern int RADEON_DEBUG;
 504 #else
 505 #define RADEON_DEBUG            0
 506 #endif
 507
 508 #endif